An Optoelectronic Clock Recovery Circuit Using a Resonant Tunneling Diode and a Uni-Traveling-Carrier Photodiode

Transcription

1 1494 IEICE TRANS. ELECTRON., VOL.E82 C, NO.8 AUGUST 1999 PAPER Joint Special Issue on Recent Progress in Optoelectronics and Communications An Optoelectronic Clock Recovery Circuit Using a Resonant Tunneling Diode and a Uni-Traveling-Carrier Photodiode Koichi MURATA a), Kimikazu SANO, Tomoyuki AKEYOSHI, Naofumi SHIMIZU, Eiichi SANO, Masafumi YAMAMOTO, and Tadao ISHIBASHI, Members SUMMARY A clock recovery circuit is a key component in optical communication systems. In this paper, an optoelectronic clock recovery circuit is reported that monolithically integrates a resonant tunneling diode (RTD) and a uni-traveling-carrier photodiode (UTC-PD). The circuit is an injection-locked-type RTD oscillator that uses the photo-current generated by the UTC-PD. Fundamental and sub-harmonic clock extraction is confirmed for the first time with good clock recovery circuit characteristics. The IC extracts an electrical GHz clock signal from Gbit/s RZ optical data streams with the wide locking range of 450 MHz and low power dissipation of 1.3 mw. Furthermore, the extraction of a sub-harmonic clock from 23.1-Gbit/s and Gbit/s input data streams is also confirmed in the wider locking range of 600 MHz. The RMS jitter as determined from a single sideband phase noise measurement is extremely low at less than 200 fs in both cases of clock and sub-harmonic clock extraction. To our knowledge, the product of the output power and operating frequency of the circuit is the highest ever reported for injectionlocked-type RTD oscillators. These characteristics indicate the feasibility of the optoelectronic clock recovery circuit for use in future ultra-high-speed fully monolithic receivers. key words: optoelectronic integrated circuit, clock recovery circuit, resonant tunneling diode, uni-traveling-carrier photodiode, optical communication systems 1. Introduction Tera-bit throughput back-bone networks are needed to support the rapid expansion of the multimedia world. Ultra-high-speed electronic and/or optoelectronic circuits are indispensable for the development of the high throughput network elements, especially the optical receivers of the transmission systems. Up to now, 40- Gbit/s class electronic integrated circuits fabricated with 0.1-µm gate-length InAlAs/InGaAs/InP HEMTs have been demonstrated for next generation optical receivers [1]. Realization of over 40-Gbit/s receivers is blocked by the parasitics associated with device struc- Manuscript received December 16, Manuscript revised March 5, The authors are with NTT Network Innovation Laboratories, Yokosuka-shi, Japan. The authors are with NTT Photonics Laboratories, Atsugi-shi, Japan. The author is with NTT Electronics Technology Corporation, Atsugi-shi, Japan. a) murata@exa.onlab.ntt.co.jp This paper is also published in the IEICE Trans. Commun., Vol. E82-B, No.8, pp , August ture [2] and/or interconnection in the chip [3], excessive power consumption and electrical I/O bandwidth. To solve these problems, an optoelectronic circuit that uses a resonant tunneling diode (RTD), and a new type of wideband and high-saturation-power photo detector called the uni-traveling-carrier photodiode (UTC-PD) [4] is a promising candidate because of the high-speed characteristics [5], [6] of these devices and its simple circuit configuration. For example, an RTD/UTC-PD integrated circuit, which consists of only three active devices, demultiplexing an 80-Gbit/s optical signal into 40-Gbit/s electrical signal at an extremely low power of 7.75 mw has been demonstrated [7]. The clock recovery circuit is another key component to realize the receivers. Among various clock recovery circuits that use techniques such as phase-locked loop (PLL) and resonators, the optical injection-locked RTD oscillator is suitable for the 3R receiver configuration described in the next section. Recently, several kinds of optical injection-locked RTD oscillators [8] [10] have been reported, and phase locking to optical sinusoidal input has been demonstrated. However, clock extraction from an optical data signal such as pseudo random bit sequence (PRBS) and sub-harmonic clock extraction have not been reported. Moreover, the clock recovery circuit characteristics of locking range and phase noise have not been discussed. This paper describes an optoelectronic clock recovery circuit that monolithically integrates an RTD and a UTC-PD on an InP substrate. This is the first trial of a circuit fabricated using the monolithic process. The circuit is based on an injection-locked-type RTD oscillator [11], [12] using the photo-current generated by a UTC-PD. The RTD oscillator is superior to the conventional resonator type RTD oscillators [8] [10] in terms of electrical output power. The fabricated circuit successfully extracted an electrical clock and sub-harmonic clock signal from RZ optical input data streams with wide locking range, extreme low RMS jitter and low power dissipation. In the next section, we propose a 100-Gbit/s class low power 3R receiver configuration that utilizes the monolithic process of the RTDs and the UTC-PDs. The requirements of the clock recovery circuit based on the

2 MURATA et al: AN OPTOELECTRONIC CLOCK RECOVERY CIRCUIT 1495 Fig. 1 3R Receiver configuration. receiver configuration are then discussed. The circuit configuration and operating principle of the clock recovery circuit are also described. Experimental results including process technology, measurement setup, and circuit performances are discussed in Sect Clock Recovery Circuit 2.1 3R Receiver Configuration Figure 1 shows our goal: a 100-Gbit/s class 3R receiver configuration that uses a 1-chip optoelectronic circuit monolithically fabricated with RTD and UTC- PD. The receiver consists of an optical amplifier for reshaping and a 1-chip optoelectronic integrated circuit (OEIC) for regeneration, demultiplexing, and retiming. The optical signal is amplified by the optical amplifier, divided into two, and then input to both the demultiplexer and clock recovery circuit. The optical data signal is directly demultiplexed into lower-speed n-bit parallel electrical signals by the demultiplexer. Here, the RTD/UTC-PD integrated demultiplexer [7] is a promising candidate for the core circuit of the demultiplexer because the circuit offers direct demultiplexing from high-speed optical signal into lower speed electrical signal with ultra-low power consumption. A demultiplexer that sets n core circuits in parallel is an simple example. In this configuration, the demultiplexer has n-bit high-speed optical data input ports, n-bit electrical clock input ports, and n-bit demultiplexed data output ports. In order to achieve full-demultiplexing operation, which means that the demultiplexer outputs n-bit demultiplexed data signals simultaneously, n-bit parallel clock signals whose frequency is n times lower than the input data bit-rate, must be input to the demultiplexer. The clock recovery circuit directly extracts the electrical sub-harmonic clock signal from the input optical data stream, and distributes it to the demultiplexer. In this receiver configuration, high-speed serial to low-speed parallel conversion is performed inside the chip. That is, the input optical signal may have bitrates of the order of 100-Gbit/s, but the speed of the external and internal electrical signals of the OEIC are n times lower than the input bit-rate. Therefore, this circuit architecture does not need an over 50-GHz electrical I/O interface, and the conventional package technology [13] for 40-Gbit/s class IC with V-connectors is applicable. In the 3R receiver configuration, there are three main requirements for the clock recovery circuit. 1) The most important function is sub-harmonic clock signal extraction from the input data signal with good clock recovery characteristics such as wide locking range to cover actual system margins, low RMS jitter, and a wide tunable range in terms of output clock frequency. 2) Low power consumption is also important to allow monolithic integration with the other regenerating and demultiplexing function blocks. 3) Third is parallel clock signal distribution with sufficient output power to drive the demultiplexer. Injection-locked-type RTD oscillators are promising to meet the first requirement because they generally have higher-order harmonic components due to the inherent high-speed switching characteristic of the RTD. Actually, sub-harmonic clock extraction with extreme low RMS-jitter has been demonstrated using an electrical injection-locked RTD oscillator [14]. For the second requirement, a simple circuit configuration with only two active devices, an RTD and a UTC-PD, as described later, is attractive to achieve low power consumption and monolithic integration. We detail the optoelectronic clock recovery circuit and its experimentally determined characteristics in the following sections. 2.2 Circuit Configuration Figure 2(a) shows a circuit diagram of the clock recovery circuit. The circuit consists of an oscillator [11], [12], which is constructed with an RTD and a transmission line, and a UTC-PD. In the RTD oscillator, the RTD is biased in the negative differential resistance (NDR) region, and the collector is connected to the transmission line whose other terminal is connected to the ground. Here, τ D refers to the propagation delay time of the line. As described in Ref. [12], the dynamic operating points of the RTD oscillator lie in the positive differential resistance region, which is different from previously reported resonator type RTD oscillators [8] [10]. The circuit configuration does not require DC stability in the NDR region, which makes it possible to use a large-size RTD. As a result, the circuit can offer higher output power than conventional RTD oscillators which must use a small-size RTD in order to suppress the circuit instability due to the steep slope in the NDR region. The circuit operation is as follows. Once the first switch occurs, a pulse travels down the line, and is reflected from the short end. The pulse then arrives back at the RTD with inverted polarity after the period of

3 1496 IEICE TRANS. ELECTRON., VOL.E82 C, NO.8 AUGUST 1999 (a) (b) Fig. 2 (a) Circuit diagram of the clock recovery circuit, (b) Microphotograph of the clock recovery circuit. twice τ D. If the reflected pulse has a large enough amplitude, it will trigger a second switching event in the RTD with opposite polarity to the first. The switching event launches a second pulse down the line that subsequently induces a third switching, and so on. The essential synchronization principle is injection locking of the RTD oscillator using the photo current generated by the UTC-PD. Here, the use of the UTC-PD is important to achieve fast photo-response at low bias voltages [4] corresponding to the NDR region of the RTD. The self-oscillation of the RTD oscillator was theoretically analyzed in [15], and the oscillating frequency is given with elementary transmission-line theory by 1 F OSC = (1) 2 (τ RT D +2 τ D ) Here, τ RT D refers to the switching time of the RTD. In the present circuit, the transmission line is a coplanar wave guide monolithically fabricated on an InP substrate. We aimed at the oscillation frequency of 20 GHz for the first step. After roughly estimating the oscillation frequency using Eq. (1), circuit parameters were optimized using HSPICE simulations with precise RTD and UTC-PD device models and an equivalent circuit model of the transmission line. The physical length and characteristic impedance Z 0 of the transmission line were designed to be 1150 µm and 50 Ω, respectively. The active areas of the RTD and UTC-PD were 6 and 20 µm 2, respectively. The bias voltage V was V. Here, the oscillating frequency can be tuned by adjusting the bias voltage, because the negative differential resistance and the capacitance of the RTD has a bias dependency, which results in a change in RTD switching time, τ RT D. A microphotograph of the clock recovery circuit is shown in Fig. 2(b). The chip size was Fig. 3 Schematic cross section of the monolithically fabricated RTD and UTC-PD. 1.9 mm 0.5 mm. 3. Experimental Results 3.1 Process Technology Figure 3 shows a schematic cross section view of the monolithically integrated RTD and UTC-PD on an InP substrate [7], [16]. First, the UTC-PD layer was grown by MOCVD on a semi-insulating InP substrate. This layer consists of an n + -InP sub-collector layer, an n-inp collection layer, a p-in 0.53 Ga 0.47 As photo-absorption layer, a p + -In 0.6 Ga 0.4 As 0.85 P 0.15 barrier layer, and a p + -In 0.53 Ga 0.47 As cap layer. After thermal cleaning of the MOCVD-grown UTC- PD surface, a p + -InGaAs buffer layer, an i-inalas barrier layer, an i-alas etch stopper, and RTD layers were regrown by MBE. The RTD structure consists of an n + -In 0.53 Ga 0.47 As collector-contact layer, an n-in 0.53 Ga 0.47 As collector layer, an i- In 0.53 Ga 0.47 As spacer, an undoped double-barrier structure with an In 0.53 Ga 0.47 As (1.33 nm)/inas (1.77 nm)/in 0.53 Ga 0.47 As (1.33 nm) strained well sandwiched by AlAs (1.6 nm) barriers, an i-in 0.53 Ga 0.47 As spacer, an n-in 0.53 Ga 0.47 As emitter layer, and finally an n + -In 0.53 Ga 0.47 As emitter-contact layer. The RTD was formed into mesa structures by conventional wet-etching. Here, the i-alas layer was used as an etch stopper for the selective wet etching with citric acid/hydrogen peroxide solutions. After removing the etch stopper and the i-inalas barrier layer, the UTC-PD device was fabricated. All electrodes were formed by metal evaporation and defined by the conventional lift-off technique. The measured I-V characteristic of the RTD is

4 MURATA et al: AN OPTOELECTRONIC CLOCK RECOVERY CIRCUIT 1497 Fig. 4 I-V characteristic of the RTD. Fig. 6 Spectrum of the RTD oscillator under self-oscillation. Fig. 5 3-dB bandwidths of the UTC-PD. Fig. 7 Fundamental oscillation frequency tunable range. shown in Fig. 4. The peak current density was A/cm 2. The ratio of the peak and valley current was over 12. The NDR characteristics were observed in the bias voltage range from 0.35 to 0.7 V. No degradation in these characteristics was observed compared to the those of conventional MBE-grown RTDs directly on InP substrate. Figure 5 shows the measured dependence of 3-dB bandwidths of the UTC-PD on bias voltage for various output current (I p ) levels [16]. The responsivity of the UTC-PD was 0.26 A/W at a wavelength of 1.55 µm. The 3-dB bandwidth was around 80 GHz even at the low bias voltage of 0.4 V, which is as low as the circuit operating condition. This is wide enough to obtain injection current for the clock recovery operation at 40-Gbit/s or over optical data input. 3.2 Measurement Setup The IC was tested on a wafer. The input RZ optical data stream (λ =1.55 µm) was generated by an electrooptic pulse pattern generator that output a Gbit/s optical data stream [17]. The pulse width of the RZ optical data input was less than 10 ps, and the data sequence was PRBS. The input optical signal illuminated the UTC-PD from the backside of the wafer. In order to confirm the synchronized output clock signal, we used a digitizing oscilloscope which was triggered by the electrooptic pulse pattern generator. In the self-oscillation state, the RTD oscillator exhibited up to third order harmonic in the frequency range from 30 Hz to 50 GHz as shown in Fig. 6. The fundamental oscillation frequency was GHz, and first order and third order harmonics were 23.1 GHz and 46.2 GHz, respectively. In order to confirm sub-harmonic clock extraction, experiments were executed around the input data bit-rates of Gbit/s, 23.1 Gbit/s and 46.2 Gbit/s. 3.3 Circuit Performance The measured tunable range of the fundamental oscillation frequency in the self-oscillation state is shown in Fig. 7. The relatively wide tuning range of 500 MHz around the center frequency of GHz was obtained by adjusting the bias voltage of the RTD oscillator. Figures 8(a) and (b), respectively, show input and output waveforms when an Gbit/s optical data stream was input. The input waveform was monitored using a 25-GHz bandwidth photo detector. Figures 8(c) and (d) also show input and output waveforms when a 46.2-Gbit/s optical data stream was input. An GHz clock signal synchronized to the input optical data was successfully obtained at both data bit-rates. We also confirmed clock extraction for the input bit-rate of 23.1 Gbit/s. The output voltage swing was 150 mv p p. The IC operated with the extremely low power dissipation of 1.3 mw. Figures 9(a) and (b) show, respectively, the spectrum of the clock recovery circuit output in a lockedstate and measured single sideband (SSB) phase noise

5 1498 IEICE TRANS. ELECTRON., VOL.E82 C, NO.8 AUGUST 1999 Fig. 10 Locking range of the clock recovery circuit. Fig. 8 Operating waveforms of the clock recovery circuit. (a) Gbit/s input optical data stream, (b) GHz clock signal extracted from Gbit/s optical data, (c) 46.2-Gbit/s input optical data stream, (d) GHz clock signal extracted from 46.2-Gbit/s optical data. Fig. 11 Performance of various optical injection locking oscillators. (a) small at less than 200 fs in both clock and sub-harmonic clock extraction. Figure 10 shows the relationship between the minimum optical input power and input data bit-rate when the extracted clock signal was observed in the above mentioned experimental setup. The locking range for the fundamental self-oscillation frequency was 450 MHz with the input optical power of +10 dbm, and that for both of the first order and third order harmonics was 600 MHz with the same input optical power. The minimum input optical power as low as 6 dbm was obtained at the optimum locking bit-rate of Gbit/s. 3.4 Discussion (b) Fig. 9 (a) Spectrum of the clock recovery circuit output (in the locked state), (b) SSB phase noise in the locked state. with the offset frequency range of 10 Hz to 1 MHz, when an Gbit/s optical data stream was input. The phase noise of the extracted clock signal was quite low, 123 dbc/hz, even with 1 MHz offset. The RMS jitter as determined from the SSB measurement was quite Figure 11 shows the relationship between the output frequency and power of the previously reported optical injection locking oscillators fabricated with a variety of devices [8], [10], [18] [24]. This figure indicates that oscillators using three terminal devices are superior to RTD oscillators in terms of output power. This is due to the high gain characteristic of three terminal devices. Our circuit achieves the highest speed and output power performance yet reported for optical injectionlocked-type RTD oscillators [8] [10]. Furthermore, its oscillation frequency is comparable to that of threeterminal oscillators. Its high output power performance

6 MURATA et al: AN OPTOELECTRONIC CLOCK RECOVERY CIRCUIT 1499 is basically derived from the oscillator circuit configuration as previously described. Our optical injection locking RTD oscillator achieves high frequency oscillation performance for several reasons. First is the use of the UTC-PD. In the case of the indirect optical injection locking circuit, the bandwidth of the photodiode must cover that of the input data signals. At present, the bandwidth of the UTC-PD does not restrict circuit performance because the bandwidth is over 80 GHz which assures photo response to 80 Gbit/s class RZ data signal input. Concerning the RTD oscillator, the length of the transmission line is the main factor determining the fundamental oscillation frequency while the RTD switching time determines the limit of the higher-order frequency component of the output signal. The monolithic integration with the transmission line contributes to the suppression of the parasitics associated with the bonding wire. Such parasitics often degrade the oscillation frequency in the case of the discrete configuration of the RTD oscillator [11]. The use of RTD, which offers a high current density, is also important in achieving higher-order sub-harmonic clock extraction. This is because the switching time is determined by the product of the negative resistance and capacitance of the RTD, which can be reduced by using high current density devices. In that sense, the high current density of our RTD device, which is 10 or 100 times higher than other RTDs [10], [11], is another key to achieving excellent higher-order sub-harmonic clock extraction performance. The clock recovery circuit exhibited clock and subharmonic clock extraction with a wide tunable range, a wide locking range, a low power consumption, a low optical input power, and an extreme low phase noise. These circuit features almost satisfy the first and second requirements for using the circuit in the proposed 3R receiver, which are described in the previous section. The remaining issues are the three of accurate oscillation frequency design, higher operating frequency, and higher output power with parallel signal distribution. In fact, the measured oscillation frequency was approximately half the designed one. Furthermore, 1 V p p voltage clock signal with 50 Ω load is required to drive the demultiplexer circuit [7]. In terms of the first issue, the suppression of parasitic effect is important. The cause of the degradation of the operating frequency was revealed by circuit simulations that included the extrinsic circuit elements of probing systems. Circuit configurations to suppress the parasitic effect due to the probe system have already investigated. We are now preparing to examine the improved circuit experimentally. For the second issue, shortening the transmission line is effective. According to HSPICE simulations of the improved circuit, the RTD oscillator is expected to oscillate at over 80 GHz if the transmission line is shortened, which is sufficient for a 100-Gbit/s class receiver. In terms of the third issue, incorporation of a transistor circuit into the RTD/UTC-PD circuit is promising because conventional transistor circuits offer superior signal distribution and drivability compared to RTD circuits. In this case, the high-speed optical serial to low-speed electrical parallel conversion is performed by the RTD/UTC- PD circuit, and the low-speed electrical signal interface, amplification and distribution are performed by conventional transistor circuits. Even if we assume monolithic fabrication with 0.1-µm InP HEMTs, the simulated power consumption of the optoelectronic receiver circuit is as low as 2 W, which is much lower than that of a conventional receiver based on 40-Gbit/s discrete ICs [1]. 4. Conclusion We described an optoelectronic clock recovery circuit fabricated by monolithically integrating an RTD and a UTC-PD. The fabricated circuit successfully extracted an electrical clock and sub-harmonic clock signals from RZ optical data streams with a wide tunable range, a wide locking range, a low power consumption, a low optical input power, and an extreme low phase noise. In terms of operating speed and output power, our circuit exhibited the highest performance yet reported for optical injection-locked-type RTD oscillators. Its circuit characteristics basically satisfy many of the requirements specified for realizing our proposed 3R receiver. The clock recovery circuit can be extended to higher bit-rates by optimizing the circuit design of the RTD oscillator. Furthermore, its output power will be further improved by monolithic integration with transistor circuits. We believe the clock recovery circuit is a promising candidate to realize a low-power 100-Gbit/s class fully monolithic optoelectronic receiver circuit. Acknowledgement The authors would like to thank I. Kobayashi and K. Yamasaki for their continual encouragement throughout this work. We also thank T. Otsuji and T. Furuta for their suggestions about measurement setups, N. Watanabe for MOCVD growth, and J. Osaka for MBE growth. References [1] M. Yoneyama, A. Sano, K. Hagimoto, T. Otsuji, K. Murata, Y. Imai, S. Yamaguchi, T. Enoki, and E. Sano, Optical repeater circuit design based on InAlAs/InGaAs HEMT digital IC technology, IEEE Trans. Microwave Theory & Tech., vol.45, no.12, pp , [2] T. Enoki, H. Yokoyama, Y. Umeda, and T. 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7 1500 IEICE TRANS. ELECTRON., VOL.E82 C, NO.8 AUGUST 1999 HEMTs, Tech. Dig. 25th EUMC, pp , [4] T. Ishibashi, N. Shimizu, S. Kodama, H. Ito, T. Nagatsuma, and T. Furuta, Uni-traveling-carrier photodiodes, Tech. Dig. Ultrafast Electronics and Optoelectronics, UWA2-1, pp , [5] N. Shimizu, T. Nagatsuma, T. Waho, M. Shinagawa, M. Yaita, and M. Yamamoto, A new method for characterizing ultrafast resonant-tunneling diodes with electro-optic sampling, Opt. Quantum Electron., vol.28, pp , [6] N. Shimizu, N. Watanabe, T. Furuta, and T. Ishibashi, InP-InGaAs uni-traveling-carrier photodiode with improved 3-dB bandwidth of over 150 GHz, IEEE Photonics Tech. Lett., vol.10, no.3, pp , [7] K. Sano, K. Murata, T. Akeyoshi, N. Shimizu, T. Otsuji, M. Yamamoto, T. Ishibashi, and E. Sano, Ultra-fast optoelectronic circuit using resonant tunneling diodes and a unitraveling-carrier photodiode, IEE Electron. Lett., vol.34, no.2, pp , [8] T.P. Higgins, J.F. Harvey, D.J. Sturzebecher, A.C. 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Forrest, Initial observations of optical injection locking of GaAs metal semiconductor field effect transistor oscillators, Appl. Phys. Lett., vol.38, no.5, pp , [19] D. Sommer and N.J. Gomes, Optical injection locking of microstrip MESFET oscillator using heterojunction phototransistors, IEE Electron. Lett., vol.30, no.13, pp , [20] R. Esman, L. Goldberg, and J.F. Weller, Optical phase control of an optically injection-locked FET microwave oscillator, IEEE Trans. Microwave Theory & Tech., vol.37, no.10, pp , [21] S.R. Cochran and S.Y. Wang, Efficient optical injection locking of electronic oscillators, Microwave Journal, pp , May [22] D. Yang, P. Bhattacharya, R. Lai, T. Brock, and A. Paolella, Optical control and injection locking of monolithically integrated In 0.53 Ga 0.47 As/In 0.52 Al 0.48 As MODFET oscillators, IEEE Trans. Electron Devices, vol.42, no.1, pp.31 37, [23] J.F. Cadiou, J. Guena, E. Penard, P. Legaud, C. Minot, J.F. Palmier, H. Le Person, and J.C. Harmand, Direct optical injection locking of 20 GHz superlattice oscillators, IEE Electron. Lett., vol.30, no.20, pp , [24] M. Karakücük, W. Li, P. Freeman, J. East, G.I. Haddad, and P. Bhattacharya, Transparent emitter contact HBT s for direct optical injection locking of oscillators, IEEE MTT-S Digest, pp , Koichi Murata was born in Osaka, Japan, in He received the B.S. and M.S. degrees in mechanical engineering from Nagoya University, Nagoya, Japan, in 1987 and 1989, respectively. In 1989 he joined NTT LSI Laboratories, Atsugi, Japan. He is currently a senior research engineer at NTT Network Innovation Laboratories, Yokosuka, Japan. He has been engaged in research and development of ultra-high speed digital ICs for optical communication systems. His current research interest includes optoelectronic IC design and high-speed optical transmission systems. Mr. Murata is a member of IEEE. Kimikazu Sano was born in Tokyo, Japan, on September 25, He received the B.S. and M.S. degrees in electrical engineering from Waseda University, Tokyo, in 1994 and 1996, respectively. In 1996, he joined NTT System Electronics Laboratories, Atsugi, Japan. In 1997, he moved to NTT Optical Network Systems Laboratories (now NTT Network Innovation Laboratories), Yokosuka, Japan. He has been engaged in research of ultra-fast electronic and optoelectronic circuit design. Mr. Sano is a member of IEEE and the Japan Society of Applied Physics.

8 MURATA et al: AN OPTOELECTRONIC CLOCK RECOVERY CIRCUIT 1501 Tomoyuki Akeyoshi received the B.E., M.S., and Ph.D. degrees in electric and computer engineering from Yokohama National University, Kanagawa, Japan, in 1986, 1988, and 1991, respectively. In 1991, he joined the NTT LSI Laboratories, Atsugi, Japan, where he worked on resonant-tunneling logic gates with resonant-tunneling transistors. He is currently a research engineer in the Quantum Effect Devices research group at NTT Photonics Laboratories. His current research interests include ultrahigh-speed digital applications and fabrication technology of RTDs in combination with conventional devices. He is a member of the IEEE and the Japan Society of Applied Physics. Naofumi Shimizu was born in Osaka, Japan, in September He received the B.S. and M.S. degrees in engineering physics from Kyoto University, Kyoto, Japan, in 1986 and 1988, respectively. In 1988, he joined NTT LSI Laboratories, Kanagawa, Japan. He was engaged in research and development on III- V high-speed devices. Since 1998, he has been with NTT Lightwave Communications Laboratory, where he has been engaged in research on high-speed lightwave transport systems. Eiichi Sano was born in Shizuoka, Japan, on December 4, He received the B.S., M.S., and Ph.D. degrees from the University of Tokyo, Tokyo, Japan, in 1975, 1977, and 1998, respectively. In 1977, he joined the Electrical Communication Laboratories, NTT, Tokyo, Japan. He has been engaged in the research on MOS device physics, performance limits of mixed analog/digital MOS ULSI s, ultrafast MSM photodetectors and electrooptic sampling for measuring high-speed devices. His current research interests include high-speed electronic and optoelectronic devices for optical communication. Dr. Sano is a member of the Institute of Electrical and Electronic Engineers (IEEE). Masafumi Yamamoto was born in Hokkaido, Japan, on April 6, in He received the B.S., M.S., and Ph.D. degrees in Physics from Hokkaido University, Sapporo, Japan, in 1973, 1975, and 1978, respectively. In 1978, he joined Musashino Electrical Communication Laboratories, Nippon Telegraph and Telephone Public Corporation, Tokyo, where he was engaged in the research and development of Josephson-junction devices and circuits. In 1983, he moved to Atsugi Electrical Communication Laboratories, NTT, in Kanagawa Prefecture, where he was engaged in the research and development of quantum interference devices using quantum wires, and ultrahigh-speed electronic and optoelectronic circuits using resonant tunneling diodes in combination with HEMT s or photodiodes. He is currently an Executive Engineer in NTT Electronics Corporation, Atsugi, Japan. Dr. Yamamoto is a member of the Institute of Electrical and Electronics Engineers and the Japan Society of Applied Physics. Tadao Ishibashi received the B.S., M.S. and Ph.D. degrees in applied physics from Hokkaido University in 1971, 1973, and 1986, respectively. He joined NTT Laboratories, Musashino, Tokyo, in 1973, becoming involved in the development of semiconductor devices and related material processing. His work included submillimeter-wave Si IMPATT diode oscillators, LPE growth of InP materials, their application to field effect transistors, MBE growth of MQW-LDs, and GaAs-based and InP-based heterostructure bipolar transistor ICs. He is currently working on ultrahigh-speed optoelectronic devices and thier integration. During 1991 to 1992, he stayed at Max-Planck-Institute, Stuttgart, as a visiting scientist. He received the Ichimura Award in 1992 for the development of ballistic collection transistors.