Evaluation Board for AK8130 AKD8130
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1 ASAHI KASEI EMD CORPORATION Evaluation Board for AK8130 AKD8130 Description The AKD8130 is an evaluation board for AK8130 clock generator family. Therefore, it is easy to evaluate the jitters and VCXO performance. 4 types of boards are prepared depending on crystal foot pattern. Ordering guide AKD813X_C X: Device type 0:AK8130 0A:AK8130A 0B:AK8130B C: Crystal type N: Non Crystal A: 49 Surface mount type B: terminal C: terminal D: terminal Block Diagram AK8130 Evaluation Board VSS CLK1 VIN1.65V AK8130 CLK2 CLK3 CLK4 REFOUT AK8145miniBoard AK8142 CLK1 AK811x PIC AK8142 CLK2-1 -
2 Functions 3.PWM Filter 3. VIN Direct Input 5.Crystal 1.Power 2.DIPSW 6.AK811x 4.Dummy Capacitors Figure 1. AKD8130 top view 1. Power Supply Please connect the lead line to PAD (3V) and VSSPAD (GND). 2. DIPSW Setting DISPSW6-10 are connected to the mode setting pins of AK8130 and AK811x. If these pins are controlled with general-purpose port, microprocessor or other methods, please keep these pins open. (HIGH) Table1.1 SW SW6 SW7 SW8 SW9 SW10 OPEN Connect to: AK8130 Pin2 AK8130 Pin3 AK8130 Pin14 AK811x Pin5 AK811x Pin4 GND (LO) - 2 -
3 3. Smoothing filter for PWM signal There are patterns to configure a passive smoothing filter for PWM signal which is supplied to control the oscillation frequency of VCXO. It is necessary to mount resistor and condenser on these patterns and also input PWM signal between VIN and VSS12 pins when this filter is employed. It is also possible to control the voltage without using this filter. In this case, please input DC voltage directly to CN2 pin over VSS8 pin. 4. Dummy capacitor loads There are several dummy capacitor loads, C23 through C27. It is useful to measure clock performance or current consumption by loading capacitor which is virtually assumed in the system. It is important to take line capacitance into account and it is approximately 5pF. Consequently if there is 25pF capacitance assumed in the system, another 20pF capacitor needs to be mounted. Each clock outputs from AK8130 lead to J8 through J12. Chassis mount test jacks for miniature probe (Tektronix ) are available by mounting there. Table1.2 Jn/Cn J8/C8 J9/C9 J10/C10 J11/C11 J12/C12 Connect to: AK8130 Pin11 AK8130 Pin10 AK8130 Pin7 AK8130 Pin8 AK8130 Pin9 5. Quartz oscillator foot pattern There are 4 types of boards depending on quartz oscillator. VCXO is controlled its oscillation frequency by capacitance fluctuation of quartz oscillator. Therefore parasitic capacitance exists on the line pattern affects the oscillation performance. However in this board, ground patterns under quartz oscillator and Pin1/Pin16 is removed to minimize the unwanted affection. It is possible to check and tune characteristics of VCXO by using this board because those characteristics are adjustable by changing load capacitor, C17 and C18, to the suitable value. Please refer VCXO characteristic as a example. 6. AK811x foot pattern It is possible to mount AK811x series 1ch-PLL on this board
4 Jitter measurement Device:AK8130B Condition: S2/S1/S0=HHH, Dummy capacitor=0pf - 4 -
5 Pullable Range Profile tested Device:AK8130 Δf(ppm) MHz VCXO Characteristics NDK AT-41CD2(CL=12.0pF) (Cext1=18.0pF,Cext2=5.0pF) -50 AT-41CD2 NDK Motional inductance L1 mh 2 Motional capacitance C1 ff 17.3 Equivalent resistance R1 Ω 8.7 Shunt capacitance C0 pf 4.2 Load capacitance@27m CL pf 12 Cext1 C17 pf 18.0 Cext2 C18 pf MHz VCXO Characteristics NDK NX5032GA (CL=8.0pF) (Cext1=12.0pF, Cext2=1.0pF) NX5032GA NDK Motional inductance L1 mh 5.71 Motional capacitance C1 ff 6.09 Equivalent resistance R1 Ω 10 Shunt capacitance C0 pf 1.5 Load CL pf 8.0 Cext1 C17 pf 12.0 Cext2 C18 pf MHz VCXO Characteristics KDS SMD49 (CL=8.7pF) (Cext1=15.0pF, Cext2=1.0pF) SMD49 KDS Motional inductance L1 mh 4.4 Motional capacitance C1 ff 7.9 Equivalent resistance R1 Ω 6.0 Shunt capacitance C0 pf 1.8 Load capacitance@ 27M CL pf 8.7 Cext1 C17 pf 15.0 Cext2 C18 pf SMD49 (CL:1pF) Cext1=1pF, Cext2=5.0pF SMD49 KDS Motional inductance L1 mh 4.4 Motional capacitance C1 ff 7.9 Equivalent resistance R1 Ω 6.0 Shunt capacitance C0 pf 1.8 Load capacitance@ 27M CL pf 1 Cext1 C17 pf 1 Cext2 C18 pf
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FX-700 Low Jitter Frequency Translator
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AN2441 Application note
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ICS512 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
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Description. Benefits. Low Jitter PLL With Modulation Control. Input Decoder SSEL0 SSEL1. Figure 1. Block Diagram. Rev 2.6, August 1, 2010 Page 1 of 8
Low Jitter and Power Clock Generator with SSCG Key Features Low power dissipation - 13.5mA-typ CL=15pF - 18.0mA-max CL=15pF 3.3V +/-10% power supply range 27.000MHz crystal or clock input 27.000MHz REFCLK
Logic & Supply Voltage: L = LVHCMOS +3.3V at 15pF N=LVHCMOS +2.5V at 15pF R = LVHCMOS +1.8V at 15pF
Description Q-Tech s surface-mount QTCC230 oscillators consist of an IC 3.3Vdc, 2.5Vdc, and 1.8Vdc clock square wave generator and a miniature strip AT quartz crystal built in a low profile ceramic package