Si5316-EVB Si5319-EVB Si5322/23-EVB Si5324-EVB Si5325/26-EVB Si5327-EVB Si5316, Si5319, Si5322/23, Si5324, Si5325/26, AND Si5327 EVB USER S GUIDE

Transcription

1 Si56-EVB Si59-EVB Si5/-EVB Si5-EVB Si55/6-EVB Si57-EVB Si56, Si59, Si5/, Si5, Si55/6, ND Si57 EVB USER S GUIDE. Introduction The Si56-EVB, Si59-EVB, Si5/-EVB, Si5-EVB, Si55/6-EVB, and Si57-EVB provide platforms for evaluating Silicon Laboratories' Si56, Si59, Si5/Si5, Si5, Si55/Si56, and Si57 ny-frequency Precision lock Timing Is. The Si56, Si5, and Si5 are controlled directly using configuration pins on the devices, while the Si59, Si5, Si55, Si56, and Si57 are controlled by a microprocessor or MU (micro-controller unit) via an I or SPI interface. The Si56 is a jitter attenuator with a loop bandwidth ranging from 60 Hz to 8. khz. The Si5 and Si55 are low jitter clock multipliers with a loop bandwidth ranging from 0 khz to. MHz. The Si59, Si5, and Si56 are jitter-attenuating clock multipliers, with a loop bandwidth ranging from 60 Hz to 8. khz. The Si5 and Si57 have features and capabilities very similar to the Si56, but they have much lower loop bandwidths that range from to 55 Hz. The Si56 device can optionally be configured to operate as a Si55, so a single evaluation board is available to evaluate both devices. Likewise, the Si5 can be configured to operate as a Si5, so the two devices share a single evaluation board. The Si5x/x ny-frequency Precision locks are based on Silicon Laboratories' third-generation DSPLL technology, which provides any-frequency synthesis in a highly integrated PLL solution that eliminates the need for external VXO and loop filter components. The devices have excellent phase noise and jitter performance. The Si56 is a jitter attenuator that supports jitter generation of 0. ps RMS (typ) across the khz 0 MHz and 50 khz 80 MHz jitter filter bandwidths. The Si59, Si5, and Si56 jitter attenuating clock multipliers support jitter generation of 0. ps RMS (typ) across the khz 0 MHz and 50 khz 80 MHz jitter filter bandwidths. The Si5 and Si57 are jitter attenuating clock multipliers supporting jitter attenuation of 0. ps RMS (typ) and 0.5 ps RMS (typ) across the khz to 0 MHz and 50 khz to 80 MHz bands. The Si5 and Si55 support jitter generation of 0.6 ps RMS (typ) across the khz 0 MHz and 50 khz 80 MHz jitter filter bandwidths. For all devices, the DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. These devices are ideal for providing clock multiplication/clock division, jitter attenuation, and clock distribution in mid-range and high-performance timing applications. Top Bottom Figure. Si5x QFN EVB Rev. 0.6 / opyright 0 by Silicon Labs Si5x/x-EVB

2 Si5x-EVB Si5x-EVB Table. Features by Part Number Device PN # lock Inputs # lock Outputs ontrol Input Freq (MHz) Output Freq (MHz) Jitter Generation ( khz 0 MHz) ny-frequency Precision lock Multipliers Si5 Pin 5 to to ps rms typ 0 khz. MHz Y N LOS 6 x 6 6-QFN Si55 I or SPI 0 to 70 0 to ps rms typ 0 khz. MHz Y N LOS, FOS 6 x 6 6-QFN ny-frequency Precision lock Multipliers with Jitter ttenuation Si56 Pin 9 to 70 9 to ps rms typ 60 Hz 8. khz N N LOL, LOS 6 x 6 6-QFN Si59 I or SPI.00 to to ps rms typ 60 Hz 8. khz Y N LOL, LOS 6 x 6 6-QFN Si5 Pin.008 to to ps rms typ 60 Hz 8. khz Y Y LOL, LOS 6 x 6 6-QFN Si5 I or SPI.00 to to ps rms typ 55 Hz Y Y LOL, LOS, FOS 6x6 6-QFN Si56 I or SPI.00 to to ps rms typ 60 Hz 8. khz Y Y LOL, LOS, FOS 6x6 6-QFN Si57 I or SPI.00 to to ps rms typ 55 Hz Y Y LOL, LOS 6 x 6 6-QFN Prog. Loop BW lock Mult. Hitless Switching larms Package. pplications The Si5x/x ny-frequency Precision locks have a comprehensive feature set, including any-frequency synthesis, multiple clock inputs, multiple clock outputs, alarm and status outputs, hitless switching between input clocks, programmable output clock signal format (LVPEL, LVDS, ML, MOS), output phase adjustment between output clocks, and output phase adjustment between all output clocks and the selected reference input clock (phase increment/decrement). For more details, consult the Silicon Laboratories timing products website at ll six evaluation boards (EVBs) have an MU (805F0) that support USB communications with a P host. For the pin controlled parts (Si56, Si5, and Si5), the pin settings of the devices are determined by the MU and the P resident software that is provided with the EVB. For the MU controlled parts (Si59, Si5, Si55, Si56, and Si57), the devices are controlled and monitored through the serial port (either SPI or I ). PLD sits between the MU and the ny-frequency Precision lock device that performs voltage level translation and stores the pin configuration data for the pin controlled devices. Jumper plugs are provided so that the user can bypass the MU/PLD to manually control the pin controlled devices. Ribbon headers and SM connectors are included so that external clock in, clock out, and status pins can be easily accessed by the user. For the MU controlled devices (Si59, Si5, Si55, Si56, and Si57), the user also has the option of bypassing the MU and controlling the parts from an external serial device. On-board termination is included so that the user can evaluate single-ended or differential as well as ac or dc coupled clock inputs and outputs. separate DUT (Device Under Test) power supply connector is included so that the ny-frequency Precision locks can be run at either.8,.5 or. V, while the USB MU remains at. V. LEDs are provided for convenient monitoring of key status signals. Rev. 0.6

3 Si5x-EVB Si5x-EVB. Features The Si56-EVB, Si59-EVB, Si5/-EVB, Si5-EVB, Si55/6-EVB, and Si57-EVB each include the following: D with documentation and EVB software including the DSPLLsim configuration software utility USB cable EVB circuit board including an Si56 (Si56-EVB), Si59 (Si59-EVB), Si5 (Si5/-EVB), Si5 (Si5-EVB), Si56 (Si55/6-EVB), or Si57 (Si57-EVB). User's Guide (this document). Si56-EVB, Si59-EVB, Si5/-EVB, Si5-EVB, Si55/6-EVB, and Si57-EVB Quick Start. D-ROM is included with the evaluation board. On this D, there is a file named install_instructions.pdf. This file gives the detailed instructions on how to install the drivers and software that control the evaluation board.. onnect the two power supplies to the EVB. One is. V and the other is.8,.5, or. V. The DUT is powered by the.8/.5/. V supply.. Turn on the power supplies.. onnect a USB cable from the EVB to the P where the software was installed. 5. Install USB driver. 6. Launch software by clicking on Start Programs Silicon Laboratories Precision lock EVB Software and selecting one of the programs. 5. Functional Description The Si5x/x-EVB software allows for a complete and simple evaluation of the functions, features, and performance of the Si5x/x ny-frequency Precision locks. 5.. Narrowband versus Wideband Operation This document describes six evaluation boards: Si56, Si59, Si5/, Si5, Si55/6, and Si57. The Si56 and Si5/ evaluation boards are for pin controlled clock parts and the Si59, Si5, Si55/6, and Si57 are for clock parts that are to be controlled by an MU over a serial port. The Si56-EVB, Si59-EVB, Si5-EVB, and Si57-EVB support only one part, while the two other boards each support two parts: one that is wideband (the Si5 and the Si55) and one that is narrowband (the Si5 and the Si56). The narrowband parts are both capable of operating in the wideband mode, so evaluation of the wideband parts can be done by using a narrowband part in wideband mode. s such, these evaluation boards are only populated with narrowband parts. The Si5-EVB and Si57-EVB are special cases because the Si5 and Si57 have a lower loop bandwidth and do not support wideband operation. Because of the lower loop bandwidth, the lock times are increased and the Si5 and Si57 will be more sensitive to X-XB reference crystal temperature changes. For this reason, a 0 ppm crystal is used on the SI5-EVB. It should be noted that the 0 ppm crystal is used for its temperature stability, not its absolute accuracy. If the crystal will undergo significant changes in temperature, it is suggested that the crystal be thermally insulated by covering it with foam tape or some other means. To evaluate Si5 device operation using the Si5/-EVB, the RTE[:0] pins must be set to LL using the jumpers provided. To evaluate Si55 device operation using the Si55/6-EVB, the Precision lock EVB Software should be configured for wideband mode. For details, see the Precision lock EVB Software documentation. Rev. 0.6

4 Si5x-EVB Si5x-EVB 5.. Block Diagram Figure is a block diagram of the evaluation board. The MU communicates to the host P over a USB connection. The MU controls and monitors the Si5x through the PLD. The PLD, among other tasks, translates the signals at the MU voltage level of. V to the Si5x's voltage level, which is nominally.,.5, or.8 V. The user has access to all of the Si5x's pins using the various jumper settings as well as through the host P via the MU and PLD. 5.. Si5x Input and Output locks Figure. Si5x QFN Block Diagram The Si5x has two differential inputs that are ac terminated to 50 and then ac coupled to the part. Single-ended operation can be implemented by simply not connecting to one of the two of the differential pairs bypassing the unused input to ground with a capacitor. When operating with clock inputs of MHz or less in frequency, the appropriate dc blocking capacitors (9,,, and 6) located on the bottom of the board should be replaced with 0 resistors. The reason for this is that the capacitive reactance of the ac coupling capacitors becomes significant at low frequencies. It is also important that the KIN signal meet the minimum rise time of ns (KNtrf) even though the input frequency is low. The two clock outputs (one for the Si56-EVB and Si59-EVB) are all differential, ac-coupled and configured for driving 50 transmission lines. When using single ended outputs, it is important that the unused half of the output be terminated. Two jumpers are provided to assist in monitoring the Si5x power: When R7 is removed, J0 can be used to measure the device current. J can be used at any time to monitor the supply voltage at the device. The Si56, Si59, Si5, Si56, and Si57 require that an external reference be provided to enable the devices to operate as narrowband jitter attenuators with loop bandwidths as low as 60 Hz ( Hz for the Si5 and Si57). The external reference source can be either a crystal, a standalone oscillator or some other clock source. The range of acceptable reference frequencies is described in the ny-frequency Precision locks Family Reference Manual (Si5xxRM.pdf). The EVBs are shipped with a third overtone.85 MHz crystal that is used in the majority of applications. J and J are used when the Si5x is to be configured in narrowband mode with an external reference oscillator (i.e. without using the.85 MHz crystal). The Si57-EVB is shipped with a 0 MHz fundamental mode crystal. The RTE pins should also be configured for the desired mode, using the jumper plugs at J9 (see Table 6). For unused inputs and outputs, please refer to the ny-frequency Precision locks Family Reference Manual (Si5xxRM.pdf). Rev. 0.6

5 Si5x-EVB Si5x-EVB Table shows how the various components should be configured for the three modes of operation. For a differential external reference, connect the balanced input signals to J and J. For single-ended operation, connect the input signal to J and disconnect J. R5 is provided so that a different termination scheme can be used. If R5 is populated, then remove R9 and R Two and Three Level Inputs The two-level and three-level inputs can all be manually configured by installing jumper plugs at J9. The two level inputs are either H or L. For the three-level inputs, the M level is achieved by not installing a jumper plug at a given location. J9 can also be used as a connection to an external circuit that controls these pins. J7 is a ten pin ribbon header that is provided so that an external processor can control the Si5x over either the SPI or I bus. J is another ten pin ribbon header that brings out all of the status outputs from the Si5x. Note that some pins are shared and serve as both inputs and outputs, depending on how the device is configured. For users that wish to remotely access the input and output pins settings as well as serial ports with external hardware, all three of these headers can be connected to ribbon cables PLD and Power Table. Reference Input Mode Mode Xtal Ext Ref Wide Band Input N J N Input N J N 0 install install 5 install R install R5 install RTE0 M H RTE M H RTE 5 L N Notes:. Xtal is.85 MHz third overtone; 0 MHz fundamental for the Si57-EVB. For external reference frequencies and RTE pin settings, see the Si5xx-RM ny-frequency Precision lock Family Reference Manual.. N No connect.. Do not install this component. 5. RTE options for Si57 only. This PLD is required for the MU to control the Si5x. The PLD provides two main functions: it translates the voltage level from. V (the MU voltage) to the Si5x voltage (either.8,.5, or. V). The MU communicates to the PLD with the SPI signals SS_PLD_B (slave select), MISO (master in, slave out), MOSI (master out, slave in), and SLK. The MU can talk to PLD-resident registers that are connected to pins that control the Si5x's pins, mainly for pin control mode. When the MU wishes to access a Si5x register, the SPI signals are passed through the PLD, while being level translated, to the Si5x. The PLD is an EE device that retains its code and is loaded through the JTG port (J7). The core of the PLD runs at.8 V, which is provided by voltage regulator U6. The PLD also logically connects many of the LEDs to the appropriate Si5x pins. Rev

6 Si5x-EVB Si5x-EVB +. V DUT_PWR SS_PLD_B SS_B SLK SLK MU PLD Si55, Si56 MOSI SDI MISO SDO Figure. SPI Mode Serial Data Flow This evaluation board requires two power inputs +. V for the MU and either.8,.5, or. V for the ny-frequency Precision lock part. The power connector is J0. The grounds for the two supplies are tied together on the EVB. There are eight LEDs, as described in Table. The Evaluation board has a serial port connector (J7) that supports the following: ontrol by the MU/PLD of an ny-frequency part on an external target board. ontrol of the ny-frequency part that is on the Eval board through an external SPI or I port. For details, see J7 (Table 5). Though they are not needed on this Evaluation Board because the PLD has low output leakage current, some applications will require the use of external pullup and pulldown resistors when three level pins are being driven by external logic drivers. This is particularly true for the pin-controlled parts: the Si56, Si5 and Si5. onsult the Si5xx-RM ny-frequency Precision lock Family Reference Manual for details MU The MU is responsible for connecting the evaluation board to the P so that P resident software can be used to control and monitor the Si5x. The USB connector is J and the debug port, by which the MU is flashed, is J. The reset switch, SW, resets the MU, but not the PLD. The MU is a self-contained USB master and runs all of the code required to control and monitor the Si5x, both in the MU mode and in the pin-controlled modes. U contains a unique serial number for each board and U is an EEPROM that is used to store configuration information for the board. The board powers up in free run mode with a configuration that is outlined in "ppendix Powerup and Factory Default Settings" on page. For the pin controlled parts (Si56-EVB and Si5/-EVB), the contents of U configure the board on powerup so that jumper plugs may be used. If DSPLLsim is subsequently run, the jumper plugs should be removed before DSPLLsim downloads the configuration to the EVB so that the jumpers do not conflict with the PLD outputs. For microprocessor parts, U configures the EVB for a specific frequency plan as described in "ppendix Powerup and Factory Default Settings" on page. LVPEL outputs will not function at.8 V. If the Si5x part is to be operate at.8 V, the output format needs to be changed by altering either the SFOUT pins (Si56//) or the SFOUT register bits (Si59/ 5/6/7). 6 Rev. 0.6

7 Si5x-EVB Si5x-EVB 6. onnectors and LEDs 6.. LEDs There are eight LEDs on the board which provide a quick and convenient means of determining board status. Table. LED Status and Description LED olor Label D Green. V D Green DUT_PWR D5 Red LOL D Red B D6 Red B D Green D7 Yellow PLD D8 Yellow MU Rev

8 Si5x-EVB Si5x-EVB 6.. User Jumpers and Headers Use the following to locate the jumpers described in Figure : Ext Ref, J, J and level Inputs, J9 R9, R5, 5 on top; R, R5, R6, 0 on bot J0 J8 Status, J Serial port, J7 J5, R6 J0, R7 Figure. onnectors, Jumper Header Locations J0 assists in measuring the ny-frequency Precision lock current draw. If J0 is to be used, R7 should be removed. 8 Rev. 0.6

9 Si5x-EVB Si5x-EVB J is a 0 pin ribbon header that provides an external path to monitor the status pins. Table. Status Header, J J Pin omment J. LOL J. B J.5 B J.7 S_ clock active J.9 DUT_PWR J7 is a 0 pin ribbon header that provides an external path to serially communicate with the ny-frequency Precision lock. To control the ny-frequency part that is on the Evaluation Board from an external serial port, open the Register Programmer, connect to the Evaluation Board, go to Options in the top toolbar, and select Switch To External ontrol Mode. To control an ny-frequency part that is on an external target board from the Evaluation Board using its serial port, tie pin 9 of J7 low so that the on-board ny-frequency part is constantly being held in reset. This will force it to disable its SD_SDO output buffer. This will work only for Evaluation Boards that have Rev or higher ny-frequency parts. Table 5. External Serial Port onnector, J7 J7 Pin omment J7. SD_SDO J7. SL_SLK J7.5 SDI J7.7 _SS J7.9 DUT_RST_B not reset J9 is a three-pin by twenty header that is used to establish input levels for the pin controlled two and three-level inputs using jumper plugs. It also provides a means of externally driving the two and three-level input signals. Table 6. Two and Three Level Input Jumper Headers, J9 J9 Pin J9 Pin omment J9.B UTOSEL J9.B not used J9.B MODE J9.B SFOUT0 J9.B 0_FRQSEL0 J9.B SFOUT J9.B _FRQSEL J9.B RTE0 J9.5B _SS_FRQSEL J9.5B RTE J9.6B SDI_FRQSEL J9.6B DBL_BY J9.7B SL_SLK_BWSEL0 J9.7B not used J9.8B SD_SDO_BWSEL J9.8B IN J9.9B S_ J9.9B DE J9.0B FRQTBL J9.0B not used J is used to monitor the ny-frequency Precision lock voltage. J and J are edge mount SM connectors that are used, if so configured, to supply an external single-ended or differential reference oscillator. Rev

10 Si5x-EVB Si5x-EVB 7. EVB Software Installation The release notes and the procedure for installing the EVB software can be found on the release D included with the EVB. These items can also be downloaded from the Silabs web site: Follow the links for -PLL Jitter attenuators, and look under the Tools tab. 7.. Precision lock EVB Software Description There are several programs to control the Precision lock device. Each provides a different kind of access to the device. Refer to the online help in each program by clicking Help Help in the menu for more information on how to use the software. Note: Some of the Precision lock devices do not have a register map, so some programs may not be applicable to them. Program Table 7. User pplications Description Register Viewer The Register Viewer displays the current register map data in a table format sorted by register address to provide an overview of the device s state. This program can save and print the register map. Register Programmer The Register Programmer provides low-level register control of the device. Single and batch operations are provided to read from and write to the device. Register map files can be saved and opened in the batch mode. Setting Utility DSPLLsim This application allows for quick access to each control on the Precision lock device (either pin- or register-based). It can save and open text files as well. The DSPLLsim provides high-level control of the Precision lock device. It has the frequency planning wizard as well as control of the pins and registers in a organized, intuitive manner. 0 Rev. 0.6

11 Si5x-EVB Si5x-EVB 8. Schematics RTE0 RTE J8 SM_EDGE KIN+ J9 SM_EDGE KIN- J5 SM_EDGE KIN- IN DE UTOSEL DBL_BY SD_SDO_BWSEL SL_SLK_BWSEL0 SDI_FRQSEL _SS_FRQSEL _FRQSEL 0_FRQSEL0 FRQTBL MODE DUT_RST_B 9.9 R5 5 0NF DUT_PWR to measure DUT supply current Note to power plane 0 0NF Locate next to U install for I DUT_PWR R7.5K 9 UTOSEL SFOUT 0 SFOUT SFOUT0 FRQTBL LOL 8 LOL KOUT+ KOUT+ KOUT- KOUT- ground pins Note J Ext Ref In - SM_EDGE 9.9 R R7 R8 J6 SM_EDGE # mounting holes H # J J 5 0NF 6 00N J8 SM_EDGE J 7 0NF 00N VDD VDD VDD N 7 8 GND GND GND5 Rate Rate0 5 00N X XB R7.5K Si5x KIN+ KIN- KIN_+ KIN_- KOUT+ KOUT- KOUT+ KOUT IN 9 U5 DE SFOUT0 INT_B B DBL_BY B B SD_SDO_BWSEL SL_SLK_BWSEL0 7 SDI_FRQSEL 6 _SS_FRQSEL 5 _FRQSEL KSEL/K_TV S_ 0_FRQSEL0 6 MODE RST J6 SM_EDGE J8 SM_EDGE J J SM_EDGE Ext Ref In R6 00N 9.9 R8 00N 00N 6 R NF 0 0NF J0 5 00N UF R5 R 8 00N J 00N 9 # J7 J0 J5 J5 J J SM_EDGE KIN+ 0NF L Ferrite 00 R5 R NF X GND.85 MHz 00N H H H # Notes:. hange for Si5, Si55, and External Reference.. for Si56. Rev. 0.6

12 Si5x-EVB Si5x-EVB Figure 5. Si5x Rev. 0.6

13 Si5x-EVB Si5x-EVB Rev. 0.6 VP8 TMS TDO TK VUX TDI VP DUT_PWR DUT_PWR VP DUT_PWR VP REG_DR0 REG_DR REG_DR REG_DR SS_PLD_B MOSI SLK MISO PLD_IRQ REG_DR PLD_LED PLD_LED PLD_LED0 MU_SPRE PLD_RST_B PLD_LED MU_SPRE LOL 0_FRQSEL0 _FRQSEL _SS_FRQSEL SDI_FRQSEL SL_SLK_BWSEL0 SD_SDO_BWSEL DUT_RST_B MODE RTE0 RTE DBL_BY UTOSEL FRQTBL SFOUT0 SFOUT S_ IN DE B B PLD_SPRE PLD_SPRE PLD_SPRE PLD_SPRE PLD_SPRE5 PLD_SPRE6 PLD_SPRE7 PLD_SPRE8 PLD_SPRE9 PLD_SPRE0 PLD_SPRE PLD_SPRE PLD_SPRE PLD_SPRE PLD_LED0 MU_LED PLD_LED PLD_LED PLD_SPRE5 PLD_SPRE6 PLD_LED PLD_LED PLD_LED DUT_PWR +.V.8V DUT_PWRreturn DUT_PWR.Vreturn.V EVB main power +.V JTG connector MU PLD B B LOL DUT_PWR.V R6 R50x R6 R50x R5 R5 R56 R56 D7 Yel D7 Yel R7 0 R7 0 0NF 0NF 9 00N 9 00N + UF + UF Q BSS8 Q BSS8 UF UF D5 Red D5 Red R 0k R 0k 0 UF 0 UF 0NF 0NF 5 UF 5 UF D8 Yel D8 Yel J9 BOM = J9 BOM = R9 R9 R 66.5 R 66.5 R0 R0 IN7 9 IN6 8 IN5 7 IN 6 IN 5 IN IN IN0 O7 O6 O5 O Q 5 O 6 O 7 O0 8 Vcc 0 GND 0 OE OE 9 Buffer U9 7LX5 Buffer U9 7LX5 0NF 0NF 0NF 0NF + 7 UF + 7 UF R58 K R58 K * * * * J0 Phoenix screw * * * * J0 Phoenix screw + 0UF + 0UF 6 0NF 6 0NF UF UF 0 00N 0 00N D6 Red D6 Red D Grn D Grn R 0k R 0k 8 0NF 8 0NF R59 R J7 SMT J7 SMT R5 R50x R5 R50x In Gnd EN FB Out 5 Vreg U6 TPS760 Vreg U6 TPS UF + 6 UF L Ferrite L Ferrite FN5_M_GK FN5_M6_GK0 FN6_M_DRST FN6_M_GK 7 FN6_M_DGE 8 FN6_M 9 FN6_M6 0 FN7_M5 9 FN7_M6 8 FN7_M 7 FN7_M 6 FN7_M 5 FN7_M FN8_M6 FN8_M FN8_M FN8_M 5 FN8_M 6 FN8_M5 7 FN_M 5 FN_M 5 FN_M6 55 FN_M 56 FN_M 5 FN_M 50 FN_M5 9 FN_M 6 FN_M5 FN5_M 58 FN5_M 59 FN5_M 60 FN5_M 6 FN5_M5 6 FN5_M6 6 FN6_M5 FN6_M6 FN6_M FN6_M 0 FN6_M 9 FN_M_GSR 99 FN_M6 97 FN_M 96 FN_M 95 FN_M 9 FN_M_GTS FN_M_GTS FN_M5_GTS0 FN_M_GTS FN_M 6 FN_M5 7 FN_M5 9 FN_M 9 FN_M 9 FN_M6 90 FN_M 8 FN_M 9 FN_M 0 FN_M5 FN_M6 FN_M FN9_M 78 FN9_M 79 FN9_M 80 FN9_M6 8 FN9_M 8 FN0_M 77 FN0_M 76 FN0_M 7 FN0_M 7 FN0_M5 7 FN0_M6 7 FN0_M 70 FN_M 85 FN_M 86 FN_M 87 FN_M 89 FN_M 68 FN_M 67 FN_M 66 FN_M5 65 Bank Bank U8 X8 Bank Bank U8 X8 D Grn D Grn R8 R8 00N 00N TK 8 TDI 5 TDO 8 TMS 7 VUX 5 U8B X8 U8B X8 D Red D Red D Grn D Grn GND GND 5 GND GND 6 GND5 69 GND7 8 GND8 00 GND6 75 V 6 V 57 VIO- 0 VIO- 8 VIO- 5 VIO- 88 VIO- 98 U8 X8 U8 X UF + 5 0UF R55 0k R55 0k R5 0 R5 0 Figure 6. PLD and Power

14 Si5x-EVB Si5x-EVB VP SLK MISO MOSI PLD_IRQ MU_SPRE MU_SPRE SS_PLD_B PLD_SPRE PLD_SPRE PLD_SPRE PLD_SPRE PLD_SPRE5 PLD_SPRE6 PLD_SPRE7 PLD_SPRE8 PLD_SPRE9 PLD_SPRE0 Spares VP VP Install.5K pullups for I operation. On MU: P0.0 = SD P0. = SL MU debug PLD_SPRE6 PLD_SPRE5 PLD_SPRE PLD_SPRE PLD_SPRE PLD_SPRE VP reset PLD_RST_B VBUS USB VP EVB_SER_NUM serial number R 9.9 R5 0k J6 0_M_Header_SMT BOM = 8 UF R R6 0k.5K P.7 P.6 P.5 P. P. P. P. P.0 P.7 P.6 P.5 P. P. P. P. P _M_Header_SMT GND P.0 P. P. P. P. P.5 P.6 P.7 Vdd 0 REGIN RST/K D VBUS D+ 8 D- 9 U7 6 P0.0 5 P0. P0. P0. P0. P0.5 8 P0.6 7 P0.7 6 P.0 5 P. P. P. P. P.5 0 P.6 9 P F0 Si805F0 7 00N R K 8 UF NO SW J USB D- V D+ Gnd 6 5 S S U 9.9 R 7. R 7. R Vss Vcc 8 D 5 lk 6 Q S EEPROM W HOLD 7 M9500 R R 00N K R R9 R0 K 0 R 9 00N SN B Gnd B Gnd N N Gnd N N Gnd R6 0k U USB lamp U USB lamp SN N U Vcc R I/O Ser No. N N N 5 GND R7 00N 0k Figure 7. MU J R K 0 R REG_DR REG_DR REG_DR REG_DR REG_DR0 R0 K MU_LED DS Rev. 0.6

15 Si5x-EVB Si5x-EVB Note DUT_RST_B Status R5 DUT_PWR J 0_M_Header_SMT R8x R B B LOL R0 6.7K DE IN DBL_BY RTE RTE0 SFOUT SFOUT0 FRQTBL S_ SD_SDO_BWSEL SL_SLK_BWSEL0 SDI_FRQSEL _SS_FRQSEL R57 0 _FRQSEL 0_FRQSEL0 MODE SPI, I J7 UTOSEL R8x R5 R R9 DUT_PWR R8 R9 0k 0_M_Header_SMT Note: for Si56, Si5, and Si5. Figure 8. Two and Three Level Inputs R50 0k DUT_PWR R8 00 J B 9 9 9B 8 8 8B 7 7 7B 6 6 6B 5 5 5B B B B B 0 0 0B 9 9 9B 8 8 8B 7 7 7B 6 6 6B 5 5 5B B B B B R 0k 0x_M_HDR_SMT two level inputs three level inputs Rev

16 Si5x-EVB Si5x-EVB 9. Bill of Materials Table 8. Si5x/x Bill of Materials Item Qty Reference Part Mfgr MfgrPartNum 9,,,6,7,8,9,,9, 0,,7,9,,,, 6,9,,,,6,8,,5, 7,0,,, 00 nf Venkel 060X7R60-0KNE 0 nf Venkel 060X7R60-0KNE 7 0,,5,,8,8,5 µf Venkel 060X7R6R-05KNE 5 7,,6 µf Venkel T0006TM6MBR 6,5 0 µf Panasonic EEE-H0JXP 7 D,D,D Grn Lumex SML-LXT0805GW-TR 8 D,D5,D6 Red Lumex SML-LXT0805SRW-TR 9 D7,D8 Yel Lumex SML-LXT0805YW-TR 0 H,H,H,H # mounting hole 0 J,J,J6,J8,J6,J8,J,J5,J8, J9 SM_EDGE Johnson J USB FI BLF 9 J,J5,J7,J0,J,J,J5,J,J Jmpr_pin J9 0x_M_HDR_SMT Samtec TSM-0-0-L-TV 5 J Jmpr_pin 6 J,J7,J 0_M_Header_SMT Samtec HTST-05-0-lm-dv-a 9 J7 SMT Sullins GZ6SBN-M0 0 J0 Phoenix screw Phoenix MKDSN.5/-5.08 L,L Ferrite Venkel FB06-7H Q BSS8 On Semi BSS8LTG 5 R,R0,R0,R,R58 k Venkel R060-6W-00FT R,R 7. Venkel R060-6W-7RFT 6 0 R5,R6,R7,R,R,R,R, 0 k Venkel R60-6W-00FT R9,R50,R55 8 R9,R,R,R,R,R,R6,R 9.9 Venkel R060-6W-9R9FT,R5,R6,R8 9 7 R5,R0,R7,R9,R5,R56,R59 0 Venkel R060-6W-000T 5 R7,R,R,R5,R57 0 Venkel R060-6W-0R0FT R 66.5 Venkel R060-6W-66R5FT R5,R6 R50x Panasonic EXB-8V5JV R8 00 Venkel R060-6W-000FT 6 R0 6.7 k Venkel R060-6W-67FT 6 Rev. 0.6

17 Si5x-EVB Si5x-EVB 7 R,R5 R8x Panasonic EXB-8V80JV 8 R5 Venkel R060-6W-0FT 9 SW NO Mountain Switch 0-06-EV 0 U,U SN650 TI SN650DBVT U M9500 ST Micro M9500-WMN6P U DS Maxim/Dallas DSP U5 Si56-X-GM* Silicon Labs Si56-X-GM U6 TPS760 TI TPS760DBVT 5 U7 Si805F0 Silicon Labs 805F0-GQ 6 U8 X8 Xilinx X8-7VQG00I 7 U9 7LX5 Fairchild 7LX5MT_NL 8 X.85 MHz TX 7M000 9 X for the Si5.85 MHz 0 ppm NDK EXS00-S X for the Si57 0 MHz NDK NX5S MHZ Not Populated Table 8. Si5x/x Bill of Materials (ontinued) Item Qty Reference Part Mfgr MfgrPartNum 5,0 0 nf Venkel 060X7R60-0KNE 7 J9,J0 Jmpr_pin 8 J6 0_M_Header_SMT Samtec HTST-05-0-lm-dv-a 5 R k Venkel R060-6W-00FT 7 6 R8,R8,R9,R,R8,R9 0 Venkel R060-6W-000T 0 R6,R7,R7.5 k Venkel R060-6W-50FT 5 R5 00 Venkel R060-6W-000FT Note: X denotes the product revision. onsult the ordering guide in the Si56 data sheet for the latest product revision. For the Si5/-EVB, substitute Si5-X-GM. For the Si56-EVB, substitute Si56--GM. For the Si59-EVB, substitute Si59-X-GM. For the Si5-EVB, substitute Si5-X-GM. For the Si57-EVB, substitute Si57-X-GM. Rev

18 Si5x-EVB Si5x-EVB 0. Layout Figure 9. Silkscreen Top Figure 0. Layer 8 Rev. 0.6

19 Si5x-EVB Si5x-EVB Figure. Layer, Ground Plane Figure. Layer Rev

20 Si5x-EVB Si5x-EVB Figure. Layer,. V Power Figure. Layer 5 0 Rev. 0.6

21 Si5x-EVB Si5x-EVB Figure 5. Layer 6, DUT Power Figure 6. Layer 7, Ground Plane Rev. 0.6

22 Si5x-EVB Si5x-EVB Figure 7. Layer 8 Figure 8. Silkscreen Bottom Rev. 0.6

23 PPENDIX POWERUP ND FTORY DEFULT SETTINGS Si5x-EVB Si5x-EVB For the Si5-EVB, Si55/6-EVB, and Si57-EVB, the power up settings are as follows: 9. MHz input on KIN KIN is not used because of free run mode 55.5 MHz output on KOUT 6.08 MHz output on KOUT Loop BW of 70 Hz (Si55/6-EVB) Loop BW of 7 Hz (Si5-EVB and Si57-EVB) LVPEL outputs for KOUT and KOUT For the Si5/-EVB, the factory jumper settings are as follows: Pin Jumper omment UTOSEL H automatic, revertive none FRQSEL0 none FRQSEL = LMLM FRQSEL L 9. MHz input FRQSEL none 55.5 MHz output FRQSEL L BWSEL0 H BW is 96 Hz, the minimum BWSEL H S_ none S_ is an output, not an input FRQTBL L SONET frequency table none SFOUT0 H PEL outputs SFOUT none RTE0 none.85 MHz ref xtal RTE none DBL_BY L KOUT enabled none IN none DE none none For the Si59-EVB, the power up settings are as follows: Free run mode, based on the.85 MHz crystal 9. MHz on KOUT Loop BW of 0 Hz LVEPL output for KOUT Rev. 0.6

24 Si5x-EVB Si5x-EVB For the Si56-EVB, the factory jumper settings are as follows: pin jumper comment none none FRQSEL0 L FRQSEL = LL FRQSEL L 9. MHz input/output KDIV L div by KDIV L div by BWSEL0 H BW is 00 Hz, the minimum BWSEL H S L select KIN none none SFOUT0 H PEL output SFOUT none RTE0 none.85 MHz ref xtal RTE none DBL_BY L KOUT enabled none none none Rev. 0.6

25 Si5x-EVB Si5x-EVB DOUMENT HNGE LIST Revision 0. to Revision 0. dded Si59-EVB. dd "ppendix Powerup and Factory Default Settings" on page. Revision 0. to Revision 0. Updated for free run mode. Revision 0. to Revision 0. dded Si5-EVB Revision 0. to Revision 0.5 dded Si57-EVB. hanged any-rate to any-frequency. Revision 0.5 to Revision 0.6 Removed software installation instructions and directed reader to refer to release D or download from Silicon Labs web site. Rev

26 Si5x-EVB Si5x-EVB ONTT INFORMTION Silicon Laboratories Inc. 00 West esar havez ustin, TX 7870 Tel: +(5) Fax: +(5) Toll Free: +(877) -0 Please visit the Silicon Labs Technical Support web page: and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. dditionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 6 Rev. 0.6