Supertex inc. HV9973. Isolated, Constant Current LED Driver HV9973. Features. General Description. Applications. Typical Application Circuit

Transcription

1 Isolated, Constant Current LED Driver Features Programmable true constant current operation ±3% LED current accuracy Adaptive to external component tolerances and parasitics Primary-side current sensing Output open circuit protection Output short circuit protection Input under voltage lockout PWM dimming / enable VDC input Applications Lighting fixtures with 6-50W power range General Description The is a primary-side control IC for driving a discontinuous conduction mode DCM) flyback LED driver. The IC is optimized for operation at a constant full-load switching frequency of 100kHz and the high input DC voltage range of VDC. It maintains 3% variation of the LED current setting, and features tight line and load regulation. The proprietary primary-side output current control employed in the makes the output current setting insensitive to most component tolerances and parasitics without use of an opto-coupler feedback. The LED driver is fully protected against output open and short circuit conditions and input under-voltage. It also offers a logic input for dimming the LED light output by means of pulsewidth modulation of the output current. The is ideally suited for driving high-brightness LEDs in low-power lighting fixtures such as incandescent bulb retrofits. Typical Application Circuit V IN R IN VIN PWMD VD GATE GND CS BIAS VDD R S R BIAS C DD

2 Ordering Information Pin Configuration Part Number Package Option Packing LG-G 8-Lead SOIC 500/Reel -G indicates package is RoHS compliant Green ) VIN VD VDD GND PWMD BIAS CS 4 5 GATE 8-Lead SOIC Absolute Maximum Ratings* Parameter VIN, VD, BIAS current VDD voltage VDD current Value ±5.0mA -0.3V to VDD SHUNT) 10mA Product Marking YWW H9973 LLLL Y Last Digit of Year Sealed WW Week Sealed L Lot Number Green Packaging Package may or may not include the following marks Si or 8-Lead SOIC GATE voltage -0.3V to V DD +0.3V CS, PWMD voltage -0.3V to 6.0V Continuous power dissipation T A +5 C) derate 6.3mW/ C above +5 C) 630mW Typical Thermal Resistance Package 8-Lead SOIC θ ja 101 O C/W Junction temperature Storage temperature range +15 C -65 C to +150 C * All voltages referenced to GND pin. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics Specifications are at T A 5 C, V DD 10V, I IN 00µA, C GATE 750pF, BIAS open, unless otherwise noted). Sym Description Min Typ Max Units Conditions Power Supply VDD) V DDSHUNT) Shunt voltage * V --- V DDSTART) Start voltage * V V DD rising V DDSTOP) Under voltage threshold * V V DD falling I DDQ Supply standby current ma Gate open I DDQSTART) Start-up current * μa V DD 10V Notes * Specifications which apply over the full operating ambient temperature range of -40 O C < T A < +15 O C. Parameters guaranteed by design

3 Electrical Characteristics Sym Description Min Typ Max Units Conditions Feed Forward Inputs VD, VIN) and Oscillator I IN Operating current range * μa --- I D Operating current range * μa --- ΔQ INMAX) V IN Input charge swing * pf I IN 00μA, I D 0 K Osc Oscillator coefficient * V D VD voltage * mv --- F SSTART) Start-up frequency khz --- K C Effective integrator capacitance ratio V IN to V D Bias Current Generator BIAS) V BIAS Output voltage * mv --- GATE Output T RISE GATE output rise time ns --- T FALL GATE output fall time ns --- Current Sense Comparator V CSTH) CS trip threshold * mv --- T DELAY Propagation delay CS to GATE * ns V CS - V CSTH) ) 0mV T BLANK Leading edge blanking delay * ns --- VIN Under Voltage Comparator I INUVLO) V IN undervoltage threshold current μa V IN falling ΔI INUVLO) V DD undervoltage lockout hysteresis μa V IN rising Open Circuit Protection I DOV) Output open circuit threshold μa --- PWM Dimming V PWMD,HI PWMD input high voltage * V --- V PWMD,LO PWMD input low voltage * V --- Effective Current Sense Reference Voltage V EFF Effective reference voltage mv ΔV EFF /V EFF I IN, I D regulation of V EFF % Notes * specifications which apply over the full operating ambient temperature range of -40 O C < T A < +15 O C. Parameters guaranteed by design. 1. Effective output current V EFF 0.5 V CS K Osc. Trimmed to the product of V CS K Osc. I IN 16.5μA, I D 10μA, See Note 1. 15μA I IN 185μA, 40μA I D 10μA 3

4 Functional Block Diagram VD VIN VDD UVLO 11V i D i IN Start-Up Oscillator Shunt Reg..44V Current Mirror S&H Shutdown PWMD i IN GATE i IN i D - i BIAS <i D - i BIAS > sampled) UV Power-On Reset UV VIN UVLO Oscillator & Parasitics Compensator Q R S + - L/E Blanking 1.V CLK CS i UV OVP Shutdown Q S Power-On Reset BIAS R <i D - i BIAS > sampled) 1.V i OVP GND i BIAS BIAS 4

5 Functional Description Power Topology and Control Method The regulates the constant output current of a discontinuous conduction mode DCM) flyback converter. Although it can be used in other applications, it is optimized for operating from a high DC line input voltage of VDC. The is a fully integrated peak-current PWM controller IC. It does not require an optocoupler feedback, and includes protection from output open-circuit, short-circuit, and input under-voltage conditions. A proprietary control scheme permits accurate primary-side control of output current, insensitive to most circuit parasitics, external component tolerances and output voltage variation. Output current of an flyback converter can be expressed as where V OR n V O ) 6) In the equation 5), L m is magnetizing inductance of the transformer primary winding, and V F is the forward voltage drop at the output rectifier diode. Note that the switching frequency is not a function of the internal timing components of the or the absolute value of R IN and ). Proper selection of maximum switching frequency F SMAX) at full load, in combination with maximum V ORMAX) is critical for proper operation of the. The oscillator circuit ramp may saturate when the maximum charge swing ΔQ INMAX) 400pC is exceeded at V IN. Therefore, the circuit components should be selected such that I n K PK Osc 1) ΔQ IN V IN T ON ΔQ INMAX) 7) R IN Where K Osc 0.57 is an oscillator coefficient, n is flyback transformer turns ratio of primary to secondary winding, and where I PK is peak primary winding current given by I PK V CSTH) R S In ), V CSTH) is the reference voltage of the current sense comparator at CS, and R S is the current sense resistance. Combining 1) and ), we can write the output current as V n K CSTH) Osc n V EFF R S R S The effective reference voltage V EFF 347mV. Hence, the desired LED current is programmed by merely selecting the current sense resistor as ) 3) R S n V EFF 4) Note that the output current of the LED driver is independent of the input and output voltage, the switching frequency or the transformer inductance. The switching frequency at a given output voltage V O can be estimated as F S n V + V ) K O F Osc V K OR Osc L m I PK L m I PK 5) Note, that the is protected against incorrect oscillator setup. When saturation of the oscillator ramp occurs, the shuts off and attempts to go through a start-up cycle again. The transformer magnetic flux equals the volt-seconds at the transformer winding in the DCM flyback converter V IN T ON L M I PK 8) Therefore, the charge swing ΔQ IN varies only as a function of external component tolerances and circuit parasitic, and it is the same for all V IN and V O operating conditions. Combining equations 5), 7) and 8), and taking into consideration tolerances for L m, R S and V CSTH), we get the following design criterion V ORMAX) K OscMAX) L mmax) V CSTH)MAX R SMAX) ΔQ F INMAX) SMAX) R INMIN) L mmin) V CSTH)MIN R SMIN) 9) The equation 9) gives the condition for selecting proper ratio of V ORmax) /F SMAX), which guarantees ΔQ IN Q INMAX). Selection of the resistor R IN is dictated by the desired input under-voltage UV). The recommended selection of R IN.0MΩ produces a UV shutdown at V IN < 40VDC. As an example, we can assume the tolerances of L m and R S as ±10% and ±1% correspondingly. We shall also limit the switching frequency under F SMAX) 130KHz. With these assumption, the equation 9) gives V ORMAX) 134.1V. Apparently, there 5

6 is also limitation on V OR)MAX related to open circuit protection V OR)MAX < R INMIN) I DOV)MIN 9A). In our case V OR)MAX < 10.V and the least of two values should be used. With some margin we should choose V OR)MAX 10V. The above example takes full advantage of the available V IN input dynamic range, and, therefore, achieves the most accurate control over the LED current. For this reason, we will use V ORMAX) 10V and F SMAX) 130KHz in the following equations, as our recommended design inputs. Given, the primary-to-secondary turn ratio is determined simply as V ORMAX) 10V n 10) V OMAX) ) V OMAX) ) The maximum magnetizing inductance of the primary winding L mmax) is obtained by combining the equations ), 7) and 8) L mmax) ΔQ INMAX) R INMIN) R SMIN) V CSTH)MAX 11) If we assume the primary inductance tolerance of ±10%, the nominal value of L m is determined simply as L m L mmax) 1.1 1) Selection of the maximum magnetizing inductance in accordance with 11) guarantees DCM operation in the entire working range of the input voltage with the proper selection of the input under-voltage and output over-voltage thresholds. See Input Under-Voltage Protection and Output Open and Short Circuit Protection below.) Due to presence of the leakage inductance L LK, a voltage spike occurs at the primary winding of the transformer. Although the eliminates the effect of the leakage inductance on the LED current, the duration of this spike should be minimized for best efficiency. The time t LK is the leakage spike duration, determined by L LK I PK t LK 13) V Z n V OMAX) ) Here, L LK is primary winding leakage inductance, V Z is the Zener clamp voltage. Hence, the Zener clamp voltage V Z should be selected significantly higher than n V OMAX) ). V Z must also exceed the open-circuit protection threshold. The is powered by an internal shunt regulator, clamping VDD at V DDREG) 11V. The IC shuts down when the voltage at VDD falls below V DDUV) 7.0V. Under steadystate operation, the IC is powered by an auxiliary bootstrap winding through a ballast resistor D. The primary-to-auxiliary winding turn ratio and the value of D should be selected carefully to ensure operation throughout the input and output voltage range with minimum power dissipation in D. Note that the polarity of the auxiliary winding is opposite of the polarity of the secondary winding, such that the auxiliary winding voltage is positive during the on time. The following formulas are providing optimal values for and D, given the output voltage range V OMIN), V OMAX) and the input voltage range V INMIN), V INMAX) V INMIN) V INMAX) V V V V DDUV) INMAX) INMIN) DDREG) D W DD V DDUV) V DDREG) V INMIN) V INMAX) 14) 15) n V OMAX) ) K Osc 16) D V INMAX) where W DD is power dissipation in D, and I DDQ is the quiescent current of the. n V OMIN) ) K Osc I DDQ + Q GATE V OMIN) ) F SMAX) VOMAX) ) V INMAX) V DDREG) Start-Up Upon applying the input AC power, the input current of VIN is diverted into the hold-up capacitor connected at VDD. The consumes less than 60µA in this mode, and its GATE output is off. When a threshold of V DD 10.5V is reached at VDD, VIN is disconnected from VDD, and the GATE output turns on. The GATE turns off upon reaching V CSTH) 1.V at CS. The frequency of the GATE pulses is determined by the oscillator circuit or by the 10kHz start-up clock, whichever frequency is higher. The hold-up capacitor connected at VDD must store enough energy to supply power to the until adequate bootstrap power supply becomes available. The stops switching and makes another attempt to charge the hold-up capacitor, if the voltage at VDD falls below 7.0V. Although the resistor R IN serves a different purpose in operation, its value must be selected with care to ensure the required 60µA start-up current at V INMIN). 6

7 Current Sense Comparator The peak current comparator is using an external sense resistor R S to compare the primary winding current to the reference voltage V CSTH) 1.V. The corresponding peak current I PK is given by equation ). When the current in the primary winding exceeds I PK, the comparator resets the PWM flip-flop circuit, and the output pulse is terminated. The next cycle begins upon receiving a clock signal from an internal oscillator circuit. A 300ns leading-edge blanking delay is applied to prevent false triggering of the current sense comparator. Oscillator Circuit Upon the end of the start-up cycle, the input current of V IN is reverted to a current mirror circuit for generating the current i IN in accordance with the following equation i IN V IN 1V V IN R IN R IN 17) Accordingly, the input current i D is derived by connecting a resistor from the bootstrap winding to V D. However, since >> 1 normally, the voltage V AUX is much higer in comparison to the voltage at the VD pin V D.44V). Hence, the current i D through the resistor can be expressed as i D V D V AUX 18) From this equation, the current i D is not directly proportional to V AUX. The offset current is given by the following equation i OS V D 19) The cancels out this offset internally by subtracting a current of the same magnitude as i OS. This correction current is programmed by connecting a resistor at the BIAS pin in accordance with V BIAS i OR V V D AUX V AUX 3.5 R BIAS ) Sampled during the conduction time of the transformer secondary winding, this current represents the reflected output voltage V O ), where V F is the voltage drop across the output rectified diode. The value of should scale with R IN in accordance with R IN K C k 3) In 3), k is the coupling coefficient between the primary and the bootstrap windings. The coupling coefficient can be determined by measuring the leakage inductance L SAUX) of the auxiliary winding with respect to the primary winding and calculating it in accordance with the equation k 1 L SAUX) L AUX 4) Here, L AUX is the bootstrap winding inductance. Since the value of the k is normally very close to 1, then k 1 could be used as a first approximation. With proper selection of the resistor in accordance with 3), the oscillator circuit then generates switching frequency F S n V + V ) K R O F Osc S L m V CSTH) 5) Output Open and Short Circuit Protection The provides a very reliable open circuit protection. If the sampled current i OR exceeds the 140µA threshold, the is forced to go through a power-up cycle again. The corresponding output voltage threshold can be calculated as i BIAS V BIAS 0) 3.5 i OS V OLIM) 66.5µA VF 6) n In 0), V BIAS V D / is the voltage at the BIAS pin. Combining the equations 19) and 0) gives formula for calculating R BIAS simply as R BIAS 7 1) The resulting current i OR i D - i OS ) represents the instantaneous voltage across the transformer bootstrap winding Normal operation resumes when the adequate LED load is connected. Output short circuit protection is inherent to the since the switching frequency is directly proportional to the output voltage. Moreover, loss of output voltage is likely to cause insufficient bootstrap power at VDD, resulting in a hiccup operating mode and repetitive restart attempts. 7

8 Input Under-Voltage Protection The GATE output of the becomes inhibited when the input current at VIN falls below 10µA. The GATE output is enabled again when the VIN current exceeds 140µA. The corresponding input under-voltage thresholds can be calculated as V INSTOP) R IN 10µA 7) V INSTART) R IN 140µA 8) R-C Snubber Design Considerations Detection of t LK given by the equation 13) is crucial for proper operation of the. Upon the turn-off of the switching MOSFET, the voltage spike caused by the transformer leakage inductance is followed by high-frequency oscillation. The oscillation occurs at the transformer windings with the period equal to π L LK C OSS, where C OSS is the output capacitance of the MOSFET. This oscillation is damped naturally by copper and core losses of the transformer, and it subsides during conduction time of the secondary winding. However, extra damping is usually required. Insufficiently damped, the post-spike oscillation may adversely affect accuracy of the output current regulation as well as EMI performance of the LED driver. Damping of the post-spike oscillation is achieved by connecting of a snubber network R SN, C SN ) across the switching MOSFET. Selection of the R SN and C SN values is based on achieving sufficient damping while minimizing the power losses in the snubber network. At the same time, the oscillation should not be over-damped, as this will prevent detection of t LK. We recommend the following choice of the snubber network components C SN C OSS 9) than being wired to ground or across the primary winding. Otherwise, the current from C SN may cause false tripping of the CS comparator. Power dissipation in R SN can be estimated by the following formula W RSN C SN V INMAX) F SMAX) 31) Layout Considerations The signal inputs VIN and VD operate at relatively low input current ranging from hundreds down to tens of microamps. Therefore, proximity of the switching potential of the MOSFET drain can cause a displacement current in VD and VIN affecting the normal operation of the. Proper PCB layout should avoid direct proximity of the VD and VIN inputs to the high-voltage switching potential. The resistor should be placed as close as possible to the VD input. Otherwise, a long VD trace can be susceptible to noise coupling, or it can introduce parasitic capacitance with respect to ground capable of distorting the VD input signal. Design example The following example illustrates LED driver design with for the following conditions 1. Input V INMIN) 40V, V INMAX) 375V. Output V OMIN) 6.0V, V OMAX) 18V, V F 0.7V, 0.5A 3. Maximum switching frequency F SMAX) 130kHz 4. V INSTOP) 40V Design 1. Using formula 7), calculate value of the resistor R IN R IN V INSTOP).0MΩ 10µA R SN 1.6 L LK 30) C SN. Using formula 9), calculate V ORMAX) Note that the output capacitance C OSS is a nonlinear function of the drain voltage. Most datasheets give the C OSS value at the drain voltage of V DS 5V. Typically, the output capacitance characteristic as a function of V DS is provided in the MOSFET datasheet as well. The equation 9) should use the C OSS value at V DS V INMIN) + n V OMIN) ), or at the highest V DS given in the plot, whichever voltage is lower. Also note that the R-C snubber network must be connected between the drain and the source of the MOSFET, rather V OR ΔQ INMAX) F SMAX) R IN 77.6% 134.1V K OscMAX) Using formula 9A), calculate V OR)MAX base on OV protection V OR R INMIN) I DOV)MIN 131.7V Choose V OR)MAX 10V based on 8-10% margin from lower value. 8

9 3. Using formula 10), calculate primary-to-secondary turns ratio of the flyback transformer V ORMAX) 115V n V OMAX) ) V OMAX) ) 4. Using formula 4), calculate value of the current sense resistor R S n V EFF 4.47Ω 5. Using formula ), calculate value of the maximum peak current I PKMAX) V V CSTH)MAX CSTH)MAX 0.77A R SMIN) 0.99 R S 6. Using formula 11), calculate maximum value of the magnetizing inductance L m L mmax) ΔQ INMAX) 0.99R IN 0.99R S.564µH 110% V CSTH)MAX 110% 9. Using formula 15), calculate value of the resistor D V DDUV) V DDREG) n V VINMIN) V OMIN) ) K OscMAX) INMAX) D I DDQ + Q GATE V + V ) 6.0Ω OMIN) F F SMAX) VOMAX) ) We have assumed Q GATE 15nC and V DDMIN) 8V to account for the forward voltage drop at the bootstrap winding diode.) 10. Using formula 18), calculate the maximum power dissipation W DD in the resistor D W DD V INMAX) V DDREG) n V OMAX) ) K OscMAX) 0.08W D V INMAX) 11. Using formula 30), calculate the resistor R SN. Assume C OSS 33pF IRFUC0, 600V, 1A MOSFET), L LK 0μH 7. Using formula 14), calculate turns ratio primary-to-auxiliary winding of the flyback transformer V INMIN) V INMAX) 6.7 V DDUV) V INMAX) V INMIN) V DDREG) C SN 33pF R SN 1.6 L LK 1.5k Ω C SN 8. Using formulas 1) and 3), calculate values of the resistors, R BIAS R IN 38.9kΩ 1. Using formula 30), calculate the maximum power dissipation W RSN in the resistor R SN W RSN C SN V INMAX) F SMAX) 0.6W R BIAS 5.56kΩ 7 9

10 Pin Description Pin # Function Description 1 VIN This pin is the input voltage feed forward input. Connect a resistor from this pin to the input side of the primary winding of the transformer to program the VIN current. The same resistor is also used for start-up upon initial application of power. VD This pin is the auxiliary winding feedback input. Connect a resistor from this pin to the transformer bootstrap winding. 3 VDD This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to GND. The capacitor must be able to store sufficient energy for starting up the converter. 4 CS This pin is for sensing peak output voltage at an external current sense resistor.. 5 GATE This pin is the output gate driver for an external N-channel power MOSFET. 6 BIAS This pin is used for generating a correction current to account for the.44v offset at VD. Connect a resistor to ground to program. 7 PWMD When this pin is pulled to GND, switching of the is disabled. When the PWM pin is released, or external TTL high level is applied to it, switching will resume. 8 GND This pin is the common return for all the internal circuits. 10

11 8-Lead SOIC Narrow Body) Package Outline LG) 4.90x3.90mm body, 1.75mm height max), 1.7mm pitch D θ1 8 Note 1 Index Area D/ x E1/) E1 E L Gauge Plane 1 L L1 Seating Plane Top View A A A1 e b Seating Plane Side View A A θ View B View B Note 1 h h View A-A Note 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be a molded mark/identifier; an embedded metal marker; or a printed indicator. Dimension mm) The package drawings) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http///packaging.html.) does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the website http//) 01 All rights reserved. Unauthorized use or reproduction is prohibited. Symbol A A1 A b D E E1 e h L L1 L θ θ1 MIN 1.35* * 5.80* 3.80* O 5 O NOM BSC REF BSC MAX * * 6.0* 4.00* O 15 O JEDEC Registration MS-01, Variation AA, Issue E, Sept * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. # DSPD-8SOLGTG, Version I Bordeaux Drive, Sunnyvale, CA Tel