AA4006. Pin Assignments. Description. Features. Applications 2.7W STEREO AUDIO POWER AMPLIFIER WITH 4 SELECTABLE GAIN SETUPS AND INPUT MUX AA4006

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1 .7W STEREO AUDIO POWER AMPLIFIER WITH SELECTABLE GAIN SETUPS AND INPUT MUX Description Pin Assignments The is a Class AB stereo audio power amplifier with headphone driver, which can deliver.7w into 3Ω speakers with 5.0V power supply and THDN less than %. It is designed specially for notebook PC and portable media player applications. (Top View) GND GND The features stereo full differential input or sets of stereo singleended audio input. There are different gain settings at BTL mode 6dB, db, 5.6dB and.6db, changed by setting GAIN0, GAIN pins. At SE mode, the gain is fixed.db. GAIN0 GAIN OUTL LLINEIN RLINEIN SHUTDOWN OUTR RHPIN The can amplify square waveform beep input signal from BEEPIN pin and its' output can always reach BTL terminal, masking all other audio inputs regardless of whether the chip is in shutdown, SE or BTL mode. LHPIN PVDD RIN OUTL VDD PVDD HPLINE OUTR LIN 5 HPSENSE The is available in TSSOP (EDP) package. BYPASS BEEPIN Features Output Power, THDN=%: mw at SE Mode for 3Ω Headphone mw at SE Mode for 6Ω Headphone.5W at BTL Mode for 8Ω Speaker.3W at BTL Mode for Ω Speaker.7W at BTL Mode for 3Ω Speaker Supply Voltage Range:.5V to 5.5V Selectable Internal Fixed Gain Setups Stereo : Input Multiplexer Stereo Full Differential Input PC Beep Input Low Power Consumption at Shutdown Mode 50mA Typical Excellent Click/Pop Noise Suppression Thermal Shutdown Protection GND 3 Applications Notebook PC Portable Media Player TSSOP (EDP) GND of

2 Typical Applications Circuit 0.µF C S µf 7,8,9 0.7µF 5 Left Line IN 0.7µF 6 Left HP IN MUX Gain AMP 0.7µF Left IN AMP Left Out Left Out 9 C OUT µf kω 0.7µF 3 Right Line IN 0.7µF Right HP IN 0.7µF 8 Right IN C B µf MUX BYPASS Gain AMP3 AMP Right Out Right Out HP/LINE HPSENSE C OUT µf R 0kΩ.0kΩ SLEEVE HEADPHONE JACK R 0kΩ C BP 0.7µF SHUTDOWN BEEP IN VREF PC BEEP GAIN0 GAIN 3,,3, U: of

3 Pin Descriptions Pin Number Pin Name Function,, 3, GND Ground reference, it is better to connect with thermal pad GAIN0 Internal gain setup 0, see table below 3 GAIN Internal gain setup, see table below OUTL Left channel positive output 5 LLINEIN Left channel line input 6 LHPIN Left channel headphone input 7, 8 PVDD Power supply for output stage 8 RIN Right channel common input for differential input, AC ground for singleended input 9 OUTL Left channel negative output LIN Left channel common input for differential input, AC ground for singleended input BYPASS Internal reference voltage pin, connect a.0µf ceramic capacitor to GND BEEPIN Beep signal input pin 5 HPSENSE SE, BTL mode switch pin, L BTL mode, H SE mode 6 OUTR Right channel negative output 7 HPLINE Headphone, line input select pin, L line input, H headphone input 9 VDD Power supply for other analog circuit RHPIN Right channel headphone input OUTR Right channel positive output SHUTDOWN Shutdown mode select, L shutdown enable, H shutdown disable, normal work 3 RLINEIN Right channel line input 3 of

4 Table : Gain vs. Gain0, Gain Logic Level GAIN0 GAIN HPSENSE Mode Gain L L L BTL 6dB L H L BTL db H L L BTL 5.6dB H H L BTL.6dB X X H SE.dB Absolute Maximum Ratings (Note ) Symbol Parameter Rating Unit Power Supply Voltage 6.0 V V IN Input Voltage 0.3 to 0.3 V P D Power Dissipation (Note ) Internally Limited θ JA Thermal Resistance 65 C/W T J Operating Junction Temperature 50 C T STG Storage Temperature Range 65 to 50 C T LEAD Lead Temperature (Soldering, sec) 60 C ESD ESD (Human Body Model) 00 V ESD (Machine Model) 0 V Notes:. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.. Chip is soldered to 0mm (mm x 5mm) copper (top side solder mask) of oz. on PCB with 6 x 0.5mm vias. Recommended Operating Conditions Symbol Parameter Min Max Unit Supply Voltage V T A Operating Ambient Temperature 0 85 C of

5 Electrical Characteristics (=5.0V, Gain = BTL SE mode, T A=5 C, f=khz, khz low pass filter, for SE mode, HPSENSE=5.0V, for BTL mode, HPSENSE=0V, unless otherwise specified.) Symbol Parameter Condition Min Typ Max Unit I DD Quiescent Current SE mode, V IN=0, I O= BTL mode, V IN=0, I O=0 6.5 ma I SD Shutdown Current V SHUTDOWN=0V µa HPSENSE, HPLINE.0 V V IH V IL High Logic Level Low Logic Level GAIN0, GAIN 3.0 V SHUTDOWN.0 V HPSENSE, HPLINE 3.0 V GAIN0, GAIN.0 V SHUTDOWN 0.8 V Thermal Shutdown Temperature 65 C Hysteresis Temperature Window 35 C BEEP V BP Input Amplitude.5 V P P G BP Gain C BP=0.7µF, f=khz, D=50% square wave form, V BP=3.3Vpp 0.3 V/V SE Mode THDN=%, =3Ω 90 Output Power THDN=%, =3Ω THDN=%, =6Ω 80 mw THDN=%, =6Ω THDN Total Harmonic Distortion Noise =75mW, =3Ω 0.03 % S/N Signal to Noise Ratio =75mW, =3Ω 95 db X TALK Crosstalk f=khz 90 db PSRR Power Supply Rejection Ratio C B=µF, f=khz, V RIPPLE=0.V RMS 60 db V NO Output Noise f=hz to khz, =3Ω µv RMS BTL Mode Output Offset Voltage V IN=0V, no load ±5 ±5 mv THDN=%, =3Ω. THDN=%, =3Ω.7 Output Power THDN=%, =Ω.8 THDN=%, =Ω.3 W THDN=%, =8Ω. THDN=%, =8Ω.5 5 of

6 Electrical Characteristics (=5.0V, Gain = BTL SE mode, T A=5 C, f=khz, khz low pass filter, for SE mode, HPSENSE=5.0V, for BTL mode, HPSENSE=0V, unless otherwise specified.) (Cont.) Symbol Parameter Condition Min Typ Max Unit THDN Total Harmonic Distortion Noise =W, =Ω 0.08 % S/R Signal to Noise Ratio =W, =Ω 0 db X TALK Crosstalk f=khz 0 db PSRR Power Supply Rejection Ratio C B=µF, f=khz, V RIPPLE=0.V RMS 70 db V NO Output Noise f=hz to khz, =8Ω 8 µv RMS Performance Characteristics Quiescent Current (ma) Quiescent Current vs. Supply Voltage V IN =0V No Load BTL Mode SE Mode Supply Voltage (V) Shutdown CurrentI SD (µa) Shutdown Current vs. Supply Voltage V IN =0 I OUT =0 V SHUTDOWN = Supply Voltage (V) Bypass Voltage vs. Supply Voltage THDN vs. Output Power =5.0V, SE Mode =6Ω, f=khz khz LPF Bypass Voltage (V) THDN (%) Supply Voltage (V) 0.0 m 50m 0m Output Power (W) 00m 6 of

7 Performance Characteristics (Cont.) THDN vs. Output Power THDN vs. Output Power =5.0V, SE Mode =3Ω, f=khz khz LPF BTL Mode, =Ω f=khz, khz LPF THDN (%) THDN (%) =5.0V =5.5V 0.0 m 50m Output Power (W) 0m 0.0 0m m 0m Output Power (W) 3 THDN vs. Output Power THDN vs. Output Power =5.0V, SE Mode =3Ω, 30kHz LPF =5.0V, SE Mode =3Ω, 30kHz LPF C OUT =µf THDN (%) f=khz THDN (%) 0. =75mW 0. f=khz 0.0 PΟ=5mW =50mW 0.0 m f=0hz 0m Output Power (W) THDN vs. Output Power 0m E3 0 k k Frequency (Hz) THDN vs. Output Power k =5.0V, BTL Mode =3Ω, f=khz Gain=6dB, khz LPF =5.0V, BTL Mode =Ω, f=khz Gain=6dB, khz LPF THDN (%) THDN (%) m 0m Output Power (W) 0.0 m 0m Output Power (W) 7 of

8 Performance Characteristics (Cont.) THDN vs. Output Power THDN vs. Output Power =5.0V, BTL Mode =8Ω, f=khz Gain=6dB, khz LPF =5.0V, BTL Mode =Ω, f=khz khz LPF THDN (%) THDN (%) Gain=.6dB Gain=5.6dB Gain=6dB Gain=dB 0.0 m 0m Output Power (W) 0.0 m 0m Output Power (W) THDN vs. Output Power THDN vs. Frequency =5.0V, BTL Mode =Ω, Gain=6dB 30kHz LPF =5.0V, BTL Mode =3Ω, Gain=6dB 30kHz LPF THDN (%) f=k f=k THDN (%) 0. =.75W =0.5W =.0W f=hz 0.0 m 0m Output Power (W) E3 0 k k Frequency (Hz) k THDN vs. Frequency THDN vs. Frequency =5.0V, BTL Mode =Ω, Gain=6dB 30kHz LPF =5.0V, BTL Mode =8Ω, Gain=6dB 30kHz LPF THDN (%) 0. =.5W =.0W THDN (%) 0. =.0W =0.5W 0.0 =0.5W 0.0 =0.5W E3 0 k k k E3 0 k k k Frequency (Hz) Frequency (Hz) 8 of

9 Performance Characteristics (Cont.) THDN vs. Output Power BTL Mode, =Ω f=khz, khz LPF 0 30 =5.0V, SE Mode Cb=.0µF, =3Ω V RIPPLE =0.V RMS Input AC Ground PSRR vs. Frequency THDN (%) 0. =5.0V PSRR (db) =5.5V m 0m Output Power (W) k k Frequency (Hz) k PSRR vs. Frequency THDN vs. Frequency 0 30 =5.0V, BTL Mode Cb=.0µF, =8Ω V RIPPLE =0.V RMS Input AC Ground 0 0 =5.0V, SE Mode =75mW, =3Ω PSRR (db) Crosstalk (db) Left > Right Right > Left 90 0 k k Frequency (Hz) 0 k 0 k k Frequency (Hz) k Crosstalk vs. Frequency Gain vs. Frequency Crosstalk (db) =5.0V BTL Mode =8Ω, =.0W Right > Left Gain (db) 8 6 =5.0V, BTL Mode =8Ω, =.0µF Gain0, Gain=H, H Gain0, Gain=H, L Gain0, Gain=L, H 0 Left > Right 0 k k Frequency (Hz) k 8 6 Gain0, Gain=L, L 0 k k Frequency (Hz) k 9 of

10 Performance Characteristics (Cont.) Gain vs. Frequency THDN vs. Common Mode Input Voltage Gain (db) 6 0 =kω =6Ω =5.0V, SE Mode =.0µF, C OUT =µf THDN (%) =5.0V, BTL Mode Differential Input =8Ω, f=khz P=.0W =3Ω k k Frequency (Hz) k Common Mode Input Voltage (V) THDN vs. Output Voltage Pop Noise at SE Mode =5.0V, SE Mode =kω, C OUT =µf =.0µF, f=khz CH THDN (%) 0. CH CH m Output Voltage (V) 3 (=5V, SE Mode, =3Ω, C b=.0µf, =0.7µF, C OUT=µF, CH=V SHUTDOWN, CH=V BYPASS, CH3=V OUT at ) of

11 Application Information SE/BTL Mode, HPSENSE Pin The can operate under types of output configuration, SE (SingleEnded) mode and BTL (Bridged Tied Load) mode, determined by HPSENSE pin's logic level. (Here is the discussion about left channel only, it can equally apply to right channel.) When HPSENSE pin is held low which sets the chip in BTL mode, both AMP and AMP are turned on. AMP has the same gain with AMP except 80 degree phase shift. Because the DC component (output bias voltage from AMP and AMP, approx. / ) between OUT and OUT is canceled, there is no necessity to use DC block capacitors for speaker load. In BTL mode, output voltage swing across load is about times that in SE mode, so there is about times output power compared to SE mode with same load and input. (See Figure ) If applying high level to HPSENSE pin which sets the chip in SE mode, AMP unit is turned off with high impedance. There is no current loop between OUT and OUT, the speaker is naturally disabled without any hardware change. The output audio signal rides on bias voltage at OUT (output bias voltage from AMP and AMP, approx. / ), so it has to use a capacitor C OUT to block DC bias voltage and couple AC signal to headphone load. It is recommended to connect HPSENSE to the headphone jack switch pin illustrated in Figure. When headphone plug is not inserted, the voltage of HPSENSE pin is determined by voltage divider formed by and R. For given resistors' value in Figure, =kω, R =0kΩ (Assuming =5.0V), DC voltage at HPSENSE node is about 9.5mV. AC signal equals output amplitude of OUT through C OUT, the maximum peakpeak voltage is no greater than, so the positive maximum voltage of HPSENSE node will be no greater than.5v9.5mv=.55v(dc voltage plus AC voltage), which is less than HPSENSE input high level minimum value (.0V). That means the chip works in BTL mode reliably and there is no risk of operation mode switch between SE and BTL. When headphone plug is inserted, as the is disconnected from R, the voltage of HPSENSE pin is pulled up by R to sets the chip in SE mode. HPSENSE pin can also be connected to MCU I/O port directly to switch the operation mode between SE and BTL. 0.7µF 5 Left Line IN 0.7µF 6 Left HP IN MUX Gain 0.7µF Left IN AMP AMP Left Out Left Out 9 C OUT µf kω HP/LINE 7 R 0kΩ HPSENSE 5 GAIN0 GAIN 3 R 0k Ω SLEEVE HEADPHONE JACK Figure. Input MUX and Output Configuration for Left Channel of

12 Application Information (Cont.) C LLIN 0.7µF 5 Left Line IN C LHPIN 0.7µF 6 Left HP IN C LIN 0.7µF MUX Gain AMP Left Out Left Out 9 Left IN AMP HPLINE 7 HPSENSE 5 GAIN0 C RLIN 0.7µF Right Line IN C RHPIN 0.7µF Right HP IN 3 MUX Gain AMP GAIN 3 Right Out 6 C RIN 0.7µF 8 Right IN AMP3 Right Out Figure. SingleEnded Input Input MUX, SingleEnded Input and Differential Input The offers the capability to use individual stereo inputs: headphone input and line input. For a singleended input, the common input terminal pins (LIN, RIN) should be connected to ground through a capacitor, also the size of C LIN (C RIN) has to be the same as C LLIN (C RLIN), C LHPIN (C RHPIN). Line input and headphone input are selected by switching HPLINE pin. When HPLINE is pulled high, the headphone input (LHPIN, RHPIN) is selected. When HPLINE is held low, the line input (LLINEIN, RLINEIN) is selected. If the input signals are differential, only one stereo signal is permitted because share common input terminal pin (LIN, RIN), both headphone input and line input can be formed into differential pair with common input terminal. (See Figure 3) With differential input configuration, the input coupling capacitors of differential pair can be removed if DC bias voltage of input source is within input common mode voltage range, refer to Figure THDN vs. Common Mode Input Voltage in Performance Characteristics. of

13 Application Information (Cont.) C LLIN 0.7µF 5 Left Line IN C LHPIN 0.7µF 6 CLIN 0.7µF MUX Gain AMP Left Out Left Out 9 Left Line IN AMP HPLINE 7 HPSENSE 5 GAIN0 C RLIN 0.7µF 3 Right Line IN C RHPIN 0.7µF MUX Gain C RIN 0.7µF 8 Right Line IN AMP AMP3 GAIN 3 Right Out 6 Right Out A) Using LINEIN C LLIN 0.7µF 5 MUX Left Out C LHPIN 0.7µF 6 Left HP IN C LIN 0.7µF Left HP IN Gain AMP AMP Left Out 9 HPLINE 7 HPSENSE 5 GAIN0 C RLIN 0.7µF 3 C RHPIN 0.7µF Right HP IN MUX Gain C RIN 0.7µF 8 Right HP IN AMP AMP3 GAIN 3 Right Out 6 Right Out B) Using HPIN Figure 3. Differential Input with Input Coupling Capacitors 3 of

14 Application Information (Cont.) Left Line IN 5 MUX Left Out C LHPIN 0.7µF 6 Gain AMP Left Out 9 Left Line IN AMP HPLINE 7 HPSENSE 5 GAIN0 GAIN 3 Right Line IN C RHPIN 0.7µF 3 MUX Gain AMP Right Out 6 Right Line IN 8 AMP3 Right Out A) Using LINEIN C LLIN 0.7µF 5 MUX Left Out Left HP IN 6 Gain AMP Left Out 9 Left HP IN AMP HPLINE 7 HPSENSE 5 GAIN0 C RLIN 0.7µF 3 GAIN 3 Right Out 6 Right HP IN MUX Gain AMP Right HP IN 8 AMP3 Right Out B) Using HPIN Figure. Differential Input without Input Coupling Capacitors of

15 Application Information (Cont.), C OUT, C B and C S (Power Supply) Selection Although there is no necessary to use input coupling capacitors in differential input if DC voltage of input is within commonmode input voltage range. The allows using input capacitors to accommodate different DC level between input source(like Audio DA converter) and bias voltage (about / ), especially in singleended input mode which is popularly used in most applications. Input stage of is illustrated as Figure 5, it is a full differential architecture, which consists of input resistor, and feedback resistor,. In SE mode, passband gain is, R GAIN SE = R FB IN.() In BTL mode, passband gain is, GAIN BTL R R FB = () IN OUT AMP V BIAS AMP OUT External Internal Figure 5. Full Differential Input Stage of The typical input resistance, feedback resistance of at each gain setting are showed in the table below. GAIN0 GAIN HPSENSE GAIN (db) (Ω) (Ω) x x of

16 Application Information (Cont.) Input capacitors and input resistors form a first order High Pass Filter, which determines the lower corner frequency according to the equation below. f CIL πr * C =...(3) IN IN It is a little different from the classic equation according to Figure 6. OUT AMP V BIAS AMP OUT External Internal A) Input Configuration with Input Capacitor OUT AMP V BIAS AMP OUT External Internal B) Classic Input Configuration with Input Capacitor Figure 6. Input Configuration with Input Capacitor, Input resistance varies with gain setting, also the absolute resistance of may drift ±% due to fab process. To ensure the minimum cutoff frequency within the audible range, the input capacitor () has to be greater than 0.33µF. The low ESR ceramic capacitor of 0.7µF is recommended. See Figure 7 for frequency response using 0.7µF. However, using bigger size of will affect pop noise of. If using an external resistor R EXT in series with input capacitor, the closedloop gain and cutoff frequency can be calculated by equations below. 6 of

17 Application Information (Cont.) 8 6 =5.0V, BTL mode =0.7µF, =kω Gain=.6dB Gain=5.6dB Gain (db) 8 6 Gain=dB Gain=6dB 0 k k Frequency (Hz) 30k Figure 7. Frequency Response Using 0.7µF Input Capacitor GAIN BTL = R R FB EXT R IN.() f CIL = π ( R EXT ).(5) R EXT OUT R EXT AMP V BIAS AMP OUT External Internal Figure 8. Using an External Resistor, R EXT in Series with Input Capacitor, Similarly, for output stage in SE mode, output capacitor (C OUT) and headphone load (R HP) also form a first order High Pass Filter, and its lower cutoff frequency is determined by equation 6. f COL =...(6) πrhp * COUT 7 of

18 Application Information (Cont.) C OUT (µf) Headphone Load (Ω) Lower Cutoff Frequency (Hz) The purpose of the bypass capacitor (C B) is to filter noise, reduce total harmonic distortion plus noise, and improve power supply rejection ratio performance. Tantalum or ceramic capacitor of.0µf with low ESR is recommended, and it should be placed as close as possible to the chip in PCB layout. This capacitor affects the pop noise performance furthest by changing the ramp of charge and/or discharge. The below table shows output noise in each gain under the condition of.0µf bypass capacitor. Unit: µvrms. Filter: Hz ~ khz AWeighted Filter SE Mode C OUT=µF, =6Ω 6 C OUT=µF, =3Ω 3 7 Gain0, Gain = 0, =Ω Gain0, Gain = 0, 3 7 Gain0, Gain =, BTL Mode Gain0, Gain =, Gain0, Gain = 0, 0 9 =8Ω Gain0, Gain = 0, 8 Gain0, Gain =, Gain0, Gain =, 5 39 For power supply, it is better to use an individual power source generated from voltage regulator split from video, digital circuit units in system. For power supply bypass capacitor (C S), it is recommended to use one low ESR electrolytic or tantalum capacitor from.7µf to µf in parallel with 0.µF ceramic capacitor which is located close to the chip. Shutdown has a shutdown feature to reduce power consumption during nonuse operation. If apply low level to shutdown pin, output amplifiers, bias circuit will be turned off, the current drawn from is about 0µA. However, the Beep Detect circuitry is always ready to give alert on speaker load once apply any valid signal into BEEPIN pin. The SHUTDOWN pin should be pulled high during normal operation, and it should never be left floating to prevent the unpredictable status of the chip. However, the music signal will be output instantly once the SHUTDOWN pin is applied to logic level from low to high. When the SHUTDOWN pin changes from high to low, output will be present until bias voltage drops to approx 0.V. See Figure 9 for time relationship between shutdown, bias voltage and output. 8 of

19 Application Information (Cont.) Figure 9. Time Chart for V SHUTDOWN, V BIAS and V OUT Optimizing Click/Pop Noise The includes optimized circuits to suppress Click/Pop noise during power up/power down transition. In BTL mode, can reduce most common mode signal also including Click/Pop noise due to symmetrical output. In SE mode, optimized ramp for rise/fall edge of bias can significantly reduce Click/Pop noise generated by output capacitor (C OUT) charge and/or discharge. Smoothing rise/fall edge of DC bias voltage is a quite important method. Another way is to prolong charge/discharge time which can shape power spectrum of output, and this makes some frequencies outside of the human audible range (Hz to khz). So external components (including C B,, C OUT and headphone load) will affect pop noise performance. The recommended components are, C B=.0µF, =0.7µF, C OUT=µF, 3Ω for headphone load. Under given conditions, the maximum peakpeak voltage of pop noise is less than 5mV (See Figure Pop Noise at SE Mode). If using 6Ω headphone, the voltage of pop noise will decrease accordingly. Beep Input Beep input feature is used in computer system for alerting. A beep signal can be sent directly from a computer. If peakpeak voltage of beep signal applied to BEEPIN pin (pin) exceeds a certain voltage (typical / ), the feature will be activated automatically, then will be forced in BTL mode with the fixed gain of 0.3V/V, both LINEIN and HPIN are deselected, the logic level of HPSENSE, HPLINE, GAIN0, GAIN and SHUTDOWN is ignored. Once beep signal is removed from the chip, the will return to the previous operation mode, gain settings. The preferred beep signal is a square wave or pulse train, the preferred input is DCcoupled. If using ACcoupled, assuming beep input capacitor is 0.7µF, the input voltage is 3.3 V PP square wave, the beep signal should have a minimum of cycles. Power Dissipation, Efficiency and Thermal Design Consideration For Class AB amplifiers, equation 7 is the basic equation of efficiency worked in BTL mode, πvp η =..(7) Here V P is output peak voltage across the load. Thermal dissipation becomes major concern when delivering more power into speaker especially in BTL mode. The maximum allowed power dissipation can be calculated by equation below which is determined by thermal resistance of package. P T T JMAX A DMAX =..(8) θ JA 9 of

20 Application Information (Cont.) Here T JMAX is maximum operating junction temperature of 50 C, T A is ambient temperature, θ JA is thermal resistance from junction to ambient. For TSSOP(EDP) package, it is 65 C/W given in datasheet. Assuming T A is 5 C, the maximum allowed power dissipation is about.9w according to equation 8. There is another equation about power dissipation which is determined by power supply voltage and load resistance under a certain application. V * V P DD P P DBTL = * VDD * RL R π L V I DD.(9) The above equation expresses total power dissipation, dominated by dual channels, quiescent current. It is a quadratic equation with the negative coefficient of output voltage variation (V P), there is always a maximum showed as below. V = I..() π DD P DBTLMAX VDD * RL DD If power dissipation calculated by application is larger than the package permitted, it is necessary to use larger copper plane under the chip, or assemble an additional heat sink, or use forcedair cooling to keep ambient temperature around the chip low, or increase load resistance, or decrease power supply voltage. For example, assuming =5.0V, speaker load R SP=.0Ω, stereo in BTL mode, the maximum power dissipation, includes channels, plus quiescent power dissipation, dominated by quiescent current. P DBTLMAX V = π R DD L V DD *I DD * 5 = 5. 0* π * =. 56W That is to say, to make sure can output power into stereo Ω speakers continuously, the maximum ambient temperature should be no more than, T A = T JMAX θ JA * P = 50 65*.56 = 6. C DT /π The maximum power dissipation is achieved only when output power perchannel equals * *R SP. If actual output power is not this data, power dissipation will be less than.56w. When junction temperature exceeds about 65 C, OTSD feature will be enabled, that turns off output amplifiers to prevent damaging the chip. Once junction temperature drops lower than 30 C, the chip will work again automatically. There is an exposed thermal pad on the bottom of the chip to provide the direct thermal path from die to heat sink. It is recommended to use copper on the surface of Printed Circuit Board (PCB) as heat sink. To dig some matrix regular holes under chip, remove mask of this area copper, and make sure to keep them contact well when soldering on PCB are also recommended. (See Figure ) of

21 Application Information (Cont.) Figure. Recommended PCB Layout for Heat Sink Recommended PCB Layout Using wide traces for power supply, BTL outputs to reduce power losses caused by parasitic resistance is recommended. It is also recommended to place bypass capacitor, and power supply decouple capacitor as close as possible to the chip. Figure. Top Route and Copper of

22 Application Information (Cont.) Figure. Bottom Route and Copper Ordering Information X X X Product Name Package Packing E/G G: TSSOP(EDP) TR: Tape & Reel E: RoHS Compliant G: RoHS Compliant and Green Package Temperature Range Part Number Marking ID Lead Free Green Lead Free Green Packing TSSOP(EDP) 0 to 85 C GTRE GTRG G GG Tape & Reel of

23 Package Outline Dimensions (All dimensions in mm(inch).) ( ) Package Type: TSSOP (EDP) 0.650(0.06) 0.90(0.007) 0.300(0.0) 3 6.0(0.) 6.600(0.59).500(0.059)MIN.300(0.69).500(0.77).700(0.6)MIN.0(0.07)MAX (0.0) 0.700(0.08).000(0.039) GAGE PLANE 0.50(0.0) SEATING PLANE 0.000(0.000) 0.50(0.005) 3 of

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