Fault Detection and Diagnosis of Multilevel Inverter Using Neural Network

Transcription

1 Fault Detection and Diagnosis of Multilevel Inverter Using Neural Network Shivam Prakash Gautam 1 Student Member, IEEE Lalit Kumar 2 Member, IEEE 1 shivam.prakash.gautam@gmail.com, 2 lkumar.ele@nitrr.ac.in, 3 sgupta.ele@nitrr.com, 1,2,3 Department of Electrical Engineering, NIT, Raipur, India Shubhrata Gupta 3 Senior Member, IEEE Abstract Multilevel inverter (MLI) has emerged as a key player in medium and high voltage application due to its tremendous popularity in reduced voltage stress across the power switches and low total harmonic distortion in output waveform. MLI requires large amount of power switches to perform conversion as compared to conventional converter. In MLI, as the number of levels increase number of switches also increase, so the probability of fault also goes on increasing with addition of power switches in converter. This paper proposes a modified switch-ladder multilevel inverter topology with fault tolerant capacity. Fault tolerance is achieved by the inner redundancy of the modified circuit and for fault detection neural network has been applied. After locating the faulty switch a suitable reconfiguration of control strategy is performed. The detailed simulation and analysis is done using MATLAB/SIMULINK. Keywords Multilevel inverter; neural network; switch-ladder; redundanc; fault analysis. I. INTRODUCTION First MLI was built in 1975 [1]. MLI provides a way to increase converter operating voltage above voltage limits of classical semiconductors [2]. Since last few decades industries have begun to demand for higher power equipment, which now reaches megawatt level [3]. In MLI we can generate three or more levels [4]. MLI is best suited for medium to high voltage ratings [5]. MLI involves large number of switching devices to perform its conversion. MLI is employed in areas of industrial drives such as pumps, fans, compressor, smart grid etc. [6]. There are many features of MLI some are as follows: generated output is of low distortion, common mode voltage is low, operating frequency is reduced, good power quality, good electromagnetic compatibility, etc. [7-8]. Use of MLI is also extended in field of photovoltaic and wind power conversion [9]. Number of switches increase as number of levels increase to obtain better output. One of the disadvantages of MLI is that it requires large number of semiconductor switches to perform its conversion hence system becomes complex as well as costly. So as the number of switches increase, the probability of fault on inverter also goes on increasing. Thus reduction in switches is required to a greater extent without affecting the number of output levels as well as increasing its fault tolerance. MLI topologies present better fault tolerant capabilities because of their inherent redundant states. Fault tolerance requirements in power converters are necessary [10]. When two level inverters are applied to a safety of critical system, duplex or triplex redundant models are used to handle fault situation [11]. In order to achieve reliability N+M redundancy concepts have been proposed in the past [12],[13]. Moreover, only a limited amount of research has been focused on fault tolerant topologies in literature. In [14] Rodriguez et al. gives operation of cascaded H- bridge (CHB) under fault condition. According to it, under fault condition, angle of phase shifting in carrier signals is modified in accordance with the number of healthy H-bridges to minimize the voltage distortion, as well as reference signal is also modified to obtain better output. In [15] Khomfoi et al. gives fault detection through soft computing techniques. In this artificial neural network (ANN) is used for classification of faults. In [16] Khomfoi et al. gives fault classification and detection is done with the use of artificial intelligence. ANN along with genetic algorithm is applied to speed up the detection and classification process. It requires only six cycles to clear open or short circuit fault. In [17] Lezana et al. presented a method to operate a regenerative CHB MLI under faulty condition. In this it is shown that even under faulty condition inverter can provide the CHB under fault condition is proposed. According to the aforementioned, under faulty condition the maximum output phase voltage of each leg is used thus, line to line voltage is also at its maximum. In [19] Lezana et al. gives fault detection of CHB by use of output voltage frequency analysis, which detects fault in one cycle measurement. Frequency analysis uses high frequency harmonics which avoids invalid detection of faults under transients while keeping the accuracy of the real faults. It uses a threshold value which is able to differentiate between normal transients and real faults. Also, speedy detection is possible because it is based on switching frequency analysis; therefore the slow dynamics of load are not complicated. This strategy also reduces complexity since it requires fewer sensors. In [20] Barriuso et al. gives fault tolerant design of asymmetric CHB. This proposes, a new reconfiguration system based on bidirectional electronic switches which is designed for three phase system. Once the fault is detected the hardware is reconfigured keeping higher power bridges in operation. It is an expensive approach. [21] Maharjan et al. gives fault tolerant operation of battery energy storage system based on multilevel cascaded PWM converter with star configuration. In case of fault it provides continuous operation and maintains state of charge balancing of the remaining healthy battery units. The strategy of fault handling is done by combination of bypassing faulty switch along with executing the neutral shift. In [22] 1 P a g e

2 Parker et al. fault tolerance of generator-converter for direct drive turbine is given. In this work a modular CHB is proposed for direct drive wind turbine generator. In case of fault, the faulty cell is bypassed, whereas the control of the remaining modules are adjusted. Boost rectifier scheme on machine side of power conversion stage is developed for this purpose featuring control of coil current without measuring the electromotive force. DC-link voltage controller is developed which can rapidly raise the dc-link voltages of remaining modules to overcome the loss of module. [23] nominal power. In [18] Lezana et al. extended operation of Sedghi et al. presents that fault detection is done through output voltage histogram and NN. In this work histogram is used for feature extraction and these features have been used as input for NN. In [24] Carnielutti et al. generalized carrier based modulation scheme for CHB operating under faulty condition is proposed. The proposed modulation scheme is same for both symmetrical and asymmetrical MLI. In this, first a set of all converter voltages for linear operation is derived, considering the status of each converter cell. By properly selecting the commonmode voltage the entire converter voltage synthesis capability can be achieved under any fault conditions. This paper first proposes a modified version of switchladder multilevel inverter topology presented in [25-26]. It is simple circuit of symmetrical MLI with less number of switches with input as isolated DC voltages. Fault tolerance is achieved through inner redundancy of the proposed modified circuit. Only open circuit fault is discussed in this paper. For detection of faulty switch, soft computing technique is used. A suitable reconfiguration of control strategy is done for post fault operation. A generalized structure of the modified switch-ladder network is also given. In section II, working principle of proposed topology is given along with its fault tolerance handling capacity is explained. Section III explains the modulation strategy adopted for the proposed topology. In section IV, fault detection and classification using ANN is explained. Section V provides the fault diagnosis result as well as experimental results. Conclusion is given in section VI. II. PROPOSED TOPOLOGY The proposed modified switch-ladder topology for symmetrical multilevel inverter is shown in Fig. 1. This topology gives the maximum output levels with minimum number of switches and is extremely fault tolerant. While examining the modified topology, it is found that in case of fault on certain switch (which is more than one) it can produce the same number of levels in the output as compared with normal operation condition. The detailed examination of the new topology is done and fault on each switch is considered. The reason behind extreme fault tolerance of proposed topology is that the redundant states are increased. Fig. 1 gives the new modified fault tolerant topology. Table I presents the switching table of proposed topology under normal condition. In proposed topology, for any number of levels, at a time only three switches are at ON state and rest others are at OFF state due to which switching losses reduces significantly as compared with conventional inverters. Fault condition on various switches is considered in the following section and detailed analysis is performed. Fig. 1. Proposed modified switch-ladder fault tolerant topology. TABLE I. SWITCHING TABLE FOR PROPOSED TOPOLOGY Output Voltage Switching (1=ON and 0=OFF) V V V V V V V V A. Fault Condition (one fault at a time): Here fault analysis is done for switches S1, S5 and S9 at a time. A. Strategy adopted in case of fault on switch 1: In case of fault occurrence, the faulted switch should be kept opened and reconfiguration of switching strategy should be done in order to get maximum output voltage levels. Fig. 2 shows the circuitry for fault on switch1 and its corresponding switching states is shown in the table 2. As can be seen from table I, switch 1 only operate for voltages 1V, 2V and 4V, hence reconfiguration of switching strategy will be done for only these voltage levels and the rest of the states are kept same. Fig. 2. Fault on switch 1. TABLE II. SWITCHING TABLE IN CASE OF FAULT ON S1 Output Voltage Switching (1=ON and 0=OFF) 1V V V 0 X X x X X X X x As can be seen from table II that 4V cannot be reached hence in order to keep the balance voltage condition -4V is omitted. Seven levels in the output have reached in faulted condition as compared with nine levels in normal condition. 2 P a g e

3 Fault results reduction in two levels in the output as compared to normal condition. B. Fault on Switch 5: Again using the same strategy as in the previous case, switch 5 should be opened. As can be seen from table I, switch 5 only operates for voltages 1V and -2V, hence reconfiguration of switching strategy should be done for only these voltage levels and the rest of the states are kept same. Table III shows the modified switching strategy in case of fault on switch 5. Faulted Switch Obtained Output Levels Under Normal Condition Table V provides the various fault condition on different switches; it can be seen from table 5 that even after the fault occurrence on switches 2, 5 or 8, the same number of output levels as in normal condition will be produced. Now extending the concept of proposed topology for higher number of levels, figure 5 shows the topology for higher number of levels. Fig. 3. Fault on Switch 5 TABLE III. SWITCHING TABLE IN CASE OF FAULT IN SWITCH 5 Output Voltage Switching (1=ON and 0=OFF) 1V V Hence it can be seen from table III even after fault all the levels have been attained by reconfiguration of switching strategy. C. Fault on Switch 9: Switch 9 is opened and reconfiguration of switching strategy is done using table 4. From table I, switch 9 operates in voltage levels of 2V, -2V and -4V, hence in table IV reconfiguration of only these levels are considered. Fig. 5. Generalized modified switch-ladder topology for higher levels. (b) Fig. 4. Fault on Switch 9 TABLE IV. SWITCHING TABLE IN CASE OF FAULT IN SWITCH 9 Output Voltage Switching (1=ON and 0=OFF) 2V V V X X X x X X X X x As can be seen from table IV voltage levels -4V cannot be reached in case of faults in switch 9. Hence, only seven levels in the output have been reached as compared to nine levels in normal condition. Now table V provides the fault condition for each switch and its corresponding output levels. (c) Fig. 6. Output voltage normal case; (b) fault on switch S1; (c) fault on switch S5; (d) fault on switch S9. (d) TABLE V. OBTAINED OUTPUT LEVELS AT VARIOUS FAULT CONDITION FOR FIGURE 1 3 P a g e

4 III. MODULATION TECHNIQUE Multi-carrier pulse width modulation technique is employed with carrier frequency of 100 hertz, whereas reference signal frequency is kept at 50 hertz. In multi-carrier pulse width modulation scheme, carrier signal are compared with reference signal and pulses so obtained are used for switching of devices corresponding to their respective voltage levels. Number of carriers will increase as the number of levels increase and the increment is directly proportional. Therefore for nine level multi-level inverter eight carriers and one reference signal are used. Fig. 6 provides the output voltage waveform of the proposed nine levels inverter. Modulation strategy is shown in fig. 7. C. Feature Extraction: Feed forward layer is used for training purpose since it performs nonlinear mapping of input and output pattern. For diagnosis of fault in switches, output voltage is used. In this paper open circuit fault at each switch is considered. Output voltage harmonics are taken as a feature for classifying the fault. Many techniques are available for obtaining the harmonics from a signal; this paper uses fast Fourier transform. Up to tenth harmonics are calculated for normal as well as nine fault cases. Harmonic spectrum of normal as well as few fault cases are shown in below fig. 9. (b) Fig. 7. Modulation strategy (c) (d) IV. FAULT DIAGNOSIS A. Neural Network: Neural network are computational models inspired by animal s central nervous system (i.e. brain) which is capable of machine learning as well as pattern recognition. Basic structure of neural network is given in figure 8. Fig. 9. Fast Fourier transform of normal case; (b) S1 fault; (c) S5 fault; (d) S9 fault. Fault features extracted from output voltage are used as input data for neural network which are used to diagnose 10 modes represented in table VI. TABLE VI. FAULT MODES AND OUTPUT OF NEURAL NETWORK Fig. 8. Architecture of Neural Network Neural networks are system of interconnected neurons which can compute values from input. Interconnection between neurons in different layers of each system is known as network. Basic neural network has following parameters: Interconnection between neurons. (b) Learning process for updating weights of interconnection. (c) Transfer function that converts a neuron weighted input to its output. B. Mathematical Formulation of Neural Network: a=f(wp+b) where p=input; w=weight; b=bias; f=transfer function and a=output. Fault modes (open circuit) Output classes Fault free S S S S S S S S S D. Training Data: Each network is trained by one set of normal data and nine set of faulty data. Thus size of matrix will be (11x10). For training purpose levenberg-marquadt (trainlm) is used. Error is calculated by mean square error (mse). Training data are obtained from simulation result by varying modulation index from 0.6 to 1 with a step size of 0.1. Testing data are obtained by varying modulation index from 0.65 to 0.95 with a step size of 0.1. E. Scaling Process: Mapminmax processes the matrices by normalizing the minimum and maximum value of each row to [Ymin, Ymax]. Before training it is often useful to scale the input and target so that they always fall within a specified range. The function mapminmax scales input and target so thet they fall in range of [-1, 1]. If mapminmax is used to 4 P a g e

5 preprocess the training set data, then whenever trained network is used with new input they should be preprocessed with minimum and maximum that was computed for training set. V. DISCUSSION In this section a comparison is drawn between 9-level proposed topology and conventional CHB. As can be seen from Table VII, the proposed topology requires less number of switches, diodes and driver circuits as compare to conventional CHB. Moreover, in case of fault on certain switches (i.e. on S2, S5 and S8) no levels or output power is lost, which is major advantage of proposed topology in comparison with CHB. TABLE VII. COMPARISON TABLE Devices MLI Type CHB Proposed Switches Diodes Driver Circuits 16 9 DC Sources 4 4 VI. SIMULATION AND DIAGNOSIS RESULTS After proper training and testing the data, different parameters like confusion matrix, validation plot, performance plot and regression plot are computed which are shown in fig. 10. Confusion matrix is determined by predicted value and obtained value. The diagonal cells in table show the number of cases that were correctly classified and other elements in table shows the misclassified cases. Element of last row and last column shows the total cases of perfectly classified and total percentage of misclassified cases. Fig. 10.(b) shows the validation of trained network. Fig. 10.(c) shows the performance of the network while training process. Fig. 11 gives the experimental output voltage waveform of proposed topology and it corresponding THD respectively. (b) (c) (d) Fig. 10. Diagnosis result confusion matrix; (b) validation plot; performance plot; (d) regression plot. 5 P a g e

6 (b) Fig. 11. Experimental Output Voltage waveform of proposed topology; (b) Experimental THD obtained for 9-level. VII. CONCLUSION In this paper a modified switch-ladder MLI topology with fault tolerance capability is presented. The proposed topology reduces the total number of switches as compared to conventional H-bridge MLI. Fault tolerance is achieved by inner redundancy of the modified proposed topology. In case of fault, with reconfiguration of switching strategy fault tolerance can be achieved. For detection and classification of fault a soft computing technique is proposed. Input data of neural network is scaled by mapminmax technique which improves the classification to 100%. FFT is used to transform the output voltage signal since it takes less time. Various parameters of classification is presented in the paper. The present paper deals with the operation of MLI from modulation index 0.6 to 1. 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