NEXIP HIGH-END COMPUTER VISION ALGORITHMS IMAGE PROCESSING & ANALYSIS GPU-FPGA 2016 Catalog

Transcription

1 NEXIP HIGH-END COMPUTER VISION ALGORITHMS IMAGE PROCESSING & ANALYSIS GPU-FPGA 2016 Catalog

2 NEXIP HIGH-END COMPUTER VISION ALGORITHMS IMAGE PROCESSING & ANALYSIS 2016 Catalog powered by / 002 NEXIP contact@nexvision.fr (+33) MARSEILLE - FRANCE

3 SUMMARY ABOUT NEXVISION ABOUT THE NEXIP LIBRARY IMAGE CAPTURE algorithms IMAGE PROCESSING algorithms Optical Pre-processing Enhancement IMAGE ANALYSIS algorithms VIDEO OUTPUT algorithms DATA LINK algorithms MISCELLANEOUS algorithms NEXIP 003 /

4 ABOUT NEXVISION NEXVISION designs and manufactures advanced optronics for innovative vision systems with a rare level of expertise in the world. We develop whole multispectral systems, from Hardware to Software, including cutting-edge image processing and analysis algorithms. SECUR Nexvision masters the entire vision system architecture : Image sensors integration in each spectral band (UV, visible, night, SWIR, LWIR, Thermal, Terahertz) HPC embedded electronic design (CPU/GPU/CUDA/FPGA ) Image processing & analysis software Video streaming, video over IP & high speed real time transmission. C Thanks to our powerful electronic modular architecture, we can quickly design any complex vision system, so our customers usually save 30% to 50% in development time. INDUSTR We design complex optronics for several markets. / 004 NEXIP

5 ITY / DEFENSE / AEROSPACE SMART HOME / SMART CITIES INEMA / MEDIA IAL INSPECTION NEXIP 005 /

6 ABOUT NEXIP NEXIP is our IP library running on FPGA and GPU. Our algorithms are actually used in several optronics for differents markets (night vision system for helicopter pilot s helmet, digital microscope, videosurveillance system in the A380...). Our portfolio of imaging and vision solutions is constantly expanded and compatible with the latest OEM technologies (Xilinx Kintex 7 & Ultrascale FPGA, nvidia Tegra K1/X1 ). / 006 NEXIP

7 Our complete library at a glance : ANALYSIS RESULTS Type : Helicopter Color : Yellow Speed : x pixels/s... IMAGE CAPTURE OPTICAL PRE PROCESSING ENHANCEMENT ANALYSIS MULTISPECTRAL IMAGE SENSORS > UV > Visible > Night vision > SWIR > LWIR / Thermal > TeraHertz OPTICAL ENHANCEMENT & CORRECTIONS > Super resolution > Aberration corrections > Chromatic aberrations > Relative illumination > Distorsion correction > Fisheye correction DECONVOLUTION > Image reconstitution > Recursive algorithms > Denoising > Myopic deconvolution > Lens defocused > Multi channels deconvolution STABILIZATION > Close control loop > Piezo actuator > Motion compensation > Viewer pointed IMAGE SENSOR PRE PROCESSING > CFA Bayer to RGB > Auto exposure > Multi resolution > Color matrix correction > Auto white balance > Gamma & YUV/HSI color conversion > Dead pixel correction > Non uniformity correction (FPN) > DSNU & PRNU > Anti flickering > Lab color space conversion > 2D Image scaling > 3D lookup table color correction > ACES color space management DYNAMIC RANGE : HDR & NOISE FILTERING > High Dynamic Range > Dynamic local tone mapping > 3D noise filter > Contrasts & edges enhancement > Spatial filters VIBRATION CORRECTION DETECTION / RECOGNITION Methods > Feature extraction > Pattern matching > Texture recognition > Optical Character Recognition > Smart line detection (rail, lane, path, horizon) > Multispectral band object recognition > Content based image retrieval Applications > Suspicious stationary object detection > Motion detection > Number plate recognition > Traffic accident detection > Streetcar line detection > Fire detection > Pedestrian counting > Human body detection > Gesture recognition TRACKING > Online tracking > Specialized trackers > Autonomous tracking initialization MACHINE LEARNING > Shallow learning > Deep learning > Neural networks ENVIRONMENT MEASUREMENT > Augmented reality > SLAM > 3D scene reconstruction > Localisation / positioning > Advanced Driver Assistance System > Ground speed estimate > Unified scene alignment > Depth map > Sensors fusion > Barcode / QR Code reading > 1D, 2D, 3D measurement DATA LINK VIDEO OUTPUT I/O > PCIe (FPGA Tegra DMA) > USB 2.0, 3.0 & 3.1 > NVMe / SSD > Fiber-optic interconnect I/O > Composite > HDMI > SDI (3G-HD) > CoaXPress MISCELLANEOUS IP > Master AXI Lite Intf > AXI Lite Slave Intf > I2C driver > SPI driver > Flash SPI > PWM DISPLAY > Microoled > LCD NEXIP 007 /

8 IMAGE CAPTURE algorithms

9 MULTISPECTRAL IMAGE SENSORS > > UV > > VISIBLE > > NIGHT VISION > > SWIR > > LWIR / THERMAL > > TERAHERTZ NEXIP 009 /

10 Visible Python driver This IP controls OnSemi Python video sensor and delivers video frames based on data received from the sensor. Support 0.3, 0.5 and 1.3 Megapixels sensor s version Up to 815 FPS 8 Bit or 10 Bit output mode LVDS data and control links calibration Sensor configuration (through an SPI connection) 3 Exposure control modes Sensor s temperature reading Configurable frame size High frame rate video applications XILINX ARTIX 7 SERIES Generic Parameter Device Resources Performance PIXEL WIDTH SENSOR VERSION Luts Flip-Flops Bram DSP48 Fmax Mpx Serial Clock 360 MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File Provided XDC Design Entry Suite Isim Vivado / 010 NEXIP

11 Night vision Kameleon/Lynx driver This IP interfaces with Photonis Kameleon (color) or Lynx (monochrome) video sensor. It processes data received from the sensor and delivers video frames. It enables sensor control and configuration as well. Mode 60 FPS and 100 FPS supported LVDS data and control links calibration Image Flip on X and/or Y axes Sensor configuration (through an AXI-Lite bus that can be connected to SPI Master) SDR or DDR sample mode Night vision video applications XILINX ARTIX 7 SERIES Generic Parameter Device Resources Performance FPS MODE Luts Flip-Flops Bram DSP48 Fmax 60 FPS x36K MHz Output Pixel Clock 100 FPS x36K MHz Output Pixel Clock / ABOUT THE KAMELEON SENSOR Supported Device Family Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File Provided XDC Photonis Kameleon sensor NATO night level : 3 Color 1,3MpX Design Entry Suite Isim Vivado NEXIP 011 /

12 Visible CMV driver This IP interfaces with CMOSIS CMV video sensor. It processes data received from the sensor and delivers video frames. It enables sensor control and configuration as well. Support all CMOSIS CMV devices. Support external exposure control. Support 10 bits per pixel mode. Support X and/or Y axes flipping. Support DDR sample mode. Sensor configuration through an AXI-Lite bus which can be connected to AXI-Lite Master. LVDS data and control links calibration. Configurable number of LVDS data outputs Configurable number of pixels per clock. Can take into account the vibrations of the system for exposure management. Provide a Frame, Line and Pixel to downstream IP. Embedded Systems Vision enhancement, automotive or airborne Film, photographic, graphic design, printing industries XILINX ARTIX 7 : XC7A200TFBG676 Generic Parameter Device Resources Performance PIXEL BY CLOCK LVDS NUMBER Luts Flip-Flops Bram DSP48 Frequency x18K 0 40 MHz SDR Input Sensor 200 MHz DDR Output Sensor 160 MHz SDR Output Pixel / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series & Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Isim / QuestaSim Vivado / 012 NEXIP

13 Aptina AR1011HS driver This IP interfaces with Aptina AR1011HS video sensor. It processes data received from the sensor and delivers video frames. It enables as well sensor control and configuration. Support 12 bits per pixel. Manual exposure mode supported. Configurable number of pixels per clock. Sensor configuration through an I2C interface. Sensor registers available in Read/Write mode through register interface. LVDS data and control links calibration: Eye detection, Word alignment. Support DDR sample mode for LVDS inputs. Can control the LED light with regards to integration time. Provide a Nexvision Video Interface based on sync signals (Frame, Line and Pixel data) to downstream IP. Embedded Systems Vision enhancement, automotive or airborne Film, photographic, graphic design, printing industries XILINX KINTEX 7 : XC7K70TFBG484-2 Generic Parameter Device Resources Performance PIXEL BY CLOCK LVDS NU- MBER Luts Flip-Flops Bram DSP48 IDELAY LVDS Frequency Pixel Frequency MHz 144 MHz Supported Device Family All Xilinx 7 series & Ultrascale Documentation Design Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Vivado NEXIP 013 /

14 On Semiconductor AR1411HS driver This IP interfaces with On Semiconductor AR1411HS video sensor. It processes data received from the sensor and delivers video frames. It enables as well sensor control and configuration. Support 12 bits per pixel. Manual and Automatic exposure modes supported. Configurable number of pixels per clock. Sensor configuration through an I2C interface. Sensor registers available in Read/Write mode through AXIlite or register interface. LVDS data and control links calibration: Eye detection, Word alignment. Support DDR sample mode for LVDS inputs. Can take into account vibrations of the system for exposure management. Provide a Nexvision Video Interface based on sync signals (Frame, Line and Pixel data) to downstream IP. Embedded Systems Vision enhancement, automotive or airborne Film, photographic, graphic design, printing industries XILINX ARTIX 7 : XC7A200TFBG676 Generic Parameter Device Resources Performance PIXEL BY CLOCK LVDS NUMBER Luts Flip-Flops Bram DSP48 Frequency MHz SDR Input Sensor MHz DDR Output Sensor 200 MHz SDR Output Pixel / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series & Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Isim / QuestaSim Vivado / 014 NEXIP

15 NEXIP 015 /

16 IMAGE PROCESSING OPTICAL

17 OPTICAL ENHANCEMENT & CORRECTIONS > > SUPER RESOLUTION > > ABERRATION CORRECTIONS > > CHROMATIC ABERRATIONS > > RELATIVE ILLUMINATION > > DISTORSION CORRECTION > > FISHEYE CORRECTION DECONVOLUTION > > IMAGE RECONSTITUTION > > RECURSIVE ALGORITHMS > > DENOISING > > MYOPIC DECONVOLUTION > > LENS DEFOCUSED > > MULTI CHANNELS DECONVOLUTION STABILIZATION > > CLOSE CONTROL LOOP > > PIEZO ACTUATOR > > MOTION COMPENSATION > > VIEWER POINTED AUTOFOCUS NEXIP 017 /

18 Pixel Sub Sampling 3 This IP algorithm shifts frame of 1/3 of a pixel during a sequence of 36 frames to perform a 9-times up sampling of each pixel. The goal is to extract a quality enhanced RGB image directly from RAW data after having merged 9 images with external software. 4 Raw (10 bits) pixels by clock. A piezo actuator to shift image of 1/3 of pixel horizontally or vertically. The colored sensor is organized with a bayer G1-R-G2-B pattern. No debayering algorithm needed. Industrial inspection/machine Vision Quality Assurance Microscopy Embedded Systems / BLOCK DIAGRAM / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Luts Flip- Flops Performance Bram DSP48 Fmax MHz Supported Device Family Xilinx 7 series Software provided in C# Documentation Design Specification Design Files Example Design Test Bench Model Constraints File UCF Design Entry ISE 14.6 Isim ISE / 018 NEXIP

19 Color co-site Sub Sampling The algorithm captures 4 frames which are shifted by 1 pixel thanks to an actuator. The objective is to extract RGB directly from RAW data instead of using a debayer. 4 Raw (10 bits) pixels by clock. A piezo actuator to shift image of one pixel horizontally or vertically. The colored sensor is organized with a bayer G1-R-G2-B pattern. No debayering algorithm needed. Industrial inspection/machine Vision Quality Assurance Microscopy Embedded Systems / RESOURCES BLOCK DIAGRAM & PERFORMANCE / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Luts Flip- Flops Performance Bram DSP48 Fmax MHz Supported Device Family Xilinx 7 series Documentation Design Specification Design Files Example Design Test Bench Model Design Entry ISE 14.6 Isim ISE NEXIP 019 /

20 Image Stabilization The image stabilization module detects a possible motion vector in the video sequence and compensates it in order to get a stable image. It estimates motion vectors between every two consecutive frames then generates smoothing motion vectors needed for compensation and warps the frames creating a more visual stable image sequence. Based on Bit Plane Matching with Gray Code. 4 x RGB (10 bits) pixels by clock. Compensation of up to [-128: 127] cumulated horizontal and vertical translation based on an 80x80 reference area. Reference area can be adjusted by register. Real time stabilization to compensate translation motion Industrial inspection/machine Vision Quality Assurance Microscopy Medical Technology Embedded Systems / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Performance Luts Flip- Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Files Example Design Test Bench Model Constraints File Design Specification UCF Design Entry ISE 14.6 Isim ISE / 020 NEXIP

21 Focus Map Focus map IP divides an image in a given number of areas. The module treats the current image finding the level of information for each area and for each vertical position of the optical engine. With this module, user knows the best vertical position for each area. 4 x RGB (10 bits) pixels by clock. Based on the square of a gradient compared to a threshold, to calculate the difference between a pixel and its neighbors. Industrial inspection/machine Vision Quality Assurance Microscopy Embedded Systems / BLOCK DIAGRAM / RESOURCES & PERFORMANCE Supported Device Family Xilinx 7 series Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Luts Flip- Flops Performance Bram DSP48 Fmax MHz Documentation Design Files Example Design Test Bench Model Constraints File Design Specification UCF Design Entry ISE 14.6 Isim ISE NEXIP 021 /

22 Focus Score This IP calculates the focus value of an incoming frame. It can be used in conjunction of an autofocus algorithm to change the lens position in order to deliver the sharpest image possible from a system. 4 x RGB (30 bits) pixels by clock. Based on the square of a gradient compared to a threshold, to calculate the difference between a pixel and its neighbors. Industrial inspection/machine Vision Quality Assurance Microscopy Embedded Systems / BLOCK DIAGRAM / RESOURCES & PERFORMANCE Supported Device Family Xilinx 7 series Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Luts Flip- Flops Performance Bram DSP48 Fmax MHz Documentation Design Files Example Design Test Bench Model Constraints File Design Specification UCF Design Entry ISE 14.6 Isim ISE / 022 NEXIP

23 NEXIP 023 /

24 IMAGE PROCESSING PRE PROCESSING

25 IMAGE SENSOR PRE PROCESSING > > CFA BAYER TO RGB > > AUTO EXPOSURE > > MULTI RESOLUTION > > COLOR MATRIC CORRECTION > > AUTO WHITE BALANCE > > GAMMA & YUV/HSI COLOR CONVERSION > > DEAD PIXEL CORRECTION > > IR SENSORS NON UNIFORMITY CORRECTION > > DSNU 1& PRNU > > ANTI FLICKERING > > LAB COLOR SPACE CONVERSION > > 2D IMAGE SCALING > > 3D LOOKUP TABLE COLOR CORRECTION > > ACES COLOR SPACE MANAGEMENT NEXIP 025 /

26 CFA Bayer to RGB Demosaicing IP delivers a generic algorithm of CFA Bayer pattern to RGB. Its goal is to be used with all Image sensors implementing a basic Bayer pattern. It is based on a linear Interpolation method using 5x5 filters. Multi-pixels by clock Power Management: Sleep Mode Generic Interface Size of a pixel (PIX_SIZE): 8 to 12 bit Nb Pixel by clock (PIX_BY_CLK): 1 to 16 Size of the Image PIX_ROW x PIX_COLUMN ( nb of ROW and nb of column) Real-Time adaptation of the CFA (Color Frame management) All vision systems with image sensors (Bayer pattern) / RESOURCES & PERFORMANCE Device XILINX ARTIX 7 (XC7A200TFBG484-3) Generic Parameter Device Resources Performance Number pixel by clock Pix column Size of a pixel Luts Flip-Flops Bram DSP48 Fmax MHz MHz MHz MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Reference Model Constraints File Matlab XDC / 026 NEXIP Design Entry Suite Isim, QuestaSim, Matlab Vivado

27 Two by two decimation CFA Bayer to RGB Demosaicing IP delivers a generic algorithm of CFA Bayer pattern to RGB. Its goal is to be used with all Image sensors implementing a basic Bayer pattern. It is based on two by two decimation algorithm. Multi-pixels by clock Power Management: Sleep Mode Generic Interface Size of a pixel (PIX_SIZE): 8 to 12 bit Nb Pixel by clock (PIX_BY_CLK): 1 to 16 Image width Real-Time adaptation of the CFA (Color Filter Array) All vision systems with image sensors (Bayer pattern) / RESOURCES & PERFORMANCE Device XILINX ARTIX 7 (XC7A200TFBG484-3) Generic Parameter Device Resources Performance Number pixel by clock Pix column Size of a pixel Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Reference Model Constraints File Matlab XDC Design Entry Suite Isim, QuestaSim, Matlab Vivado NEXIP 027 /

28 Nearest Neighbour CFA Kameleon to RGB Demosaicing IP delivers an algorithm of CFA Kameleon from Photonis night sensor to RGBW. It is based on nearest neighbour algorithm. Multi-pixels by clock Support 10 bits per pixel Power Management: Sleep Mode Generic Interface Nb Pixel by clock (PIX_BY_CLK): 1 to 16 Image width Real-Time adaptation of the CFA (Color Filter Array) of Photonis night sensor: Kameleon All vision systems using a Kameleon CFA / RESOURCES & PERFORMANCE Device XILINX ARTIX 7 (XC7A200TFBG484-3) Generic Parameter Device Resources Performance Number pixel by clock Image width Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 7 & Ultrascale series Documentation Design Files Example Design Test Bench Reference Model Constraints File Design Specification XDC Design Entry Suite Vivado / 028 NEXIP

29 Auto Exposure Auto Exposure IP is a fast adaptive IP that answers need of controlling exposition of a sensor in an unstable illumination conditions scene. It calculates luminance average of a picture and adjusts sensor s exposure time to match desired luminance target. As this IP is not sensor dependant, it can be used indifferently with night or day sensor. Multi-pixels by clock Power Management: Sleep Mode Generic Interface o Size of a pixel (PIX_SIZE): 8 to 12 bit o Nb Pixel by clock (PIX_BY_CLK): 1 to 16 o Size of a picture (PIX_ROW * PIX_COLUMN) : 1 to 20 Mpx o Frequency of the update of exposure time 2 modes Automatic and Manual Real-Time adaptation of target of luminance desired Real-Time adaptation of the Max and Min of exposure time Real-Time adaptation of the value of the correction time to added to exposure time Industrial inspection/machine Vision Quality Assurance Microscopy Medical Technology Embedded Systems Homeland Security and border surveillance Vison enhancement (automotive or airbone) / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7K70T-2FBG484) Generic Parameter Device Resources Performance Number pixel by clock Size of a pixel Pix column Pix row Luts Flip-Flops Bram DSP48 Fmax MHz MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series & Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Isim, ModelSim Vivado NEXIP 029 /

30 RGB to YCbCr This IP shifts incoming frames from RGB color space to YCbCr color space. Power Management : Sleep Mode Generic Interface o Size of color component: 8 to 12 bit o Number of pixel by clock: 1 to 16 All vision systems / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7K70T-2FBG484) Generic Parameter Device Resources Performance Number pixel by clock Size of a pixel Luts Flip-Flops Bram DSP48 Fmax 8 3x12 bits x MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 6, 7 & Ultrascale series Documentation Design Files Example Design Test Bench Model Constraints File Design Specification Design Entry ISE / Vivado ISE & Vivado / 030 NEXIP

31 RGB to YUV444 This IP shifts incoming frames from RGB color space to YUV444 color space. Power Management : Sleep Mode Generic Interface o Size of color component: 8 to 12 bit o Number of pixel by clock: 1 to 16 All vision systems / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7K70T-2FBG484) Generic Parameter Device Resources Performance Number pixel by clock Size of a pixel Luts Flip-Flops Bram DSP48 Fmax 8 3x12 bits x MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 6, 7 & Ultrascale series Documentation Design Files Example Design Test Bench Model Constraints File Design Specification Design Entry ISE / Vivado ISE & Vivado NEXIP 031 /

32 Crop Crop IP allows a system to remove of the outer parts of an image to improve framing, extract or focus on a point of interest of the scene or change aspect ratio of any pictures from any sensors. Runs on a Frame, Line and Pixel input system. Provides processed Frame, Line and Pixel to downstream IP. Provides processed new Color Filter Array to downstream IP. Y_CROP_SIZE can be any number less or equal to the frame row number. X_CROP_SIZE can be any multiple number of pixel by clock. Medical Technology Embedded Systems Vision enhancement, automotive or airborne Film, photographic, graphic design, printing industries / RESOURCES & PERFORMANCE Device XILINX ARTIX7 (XC7A200TFBG676) Generic Parameter Device Resources Frequency (MHz) PIXEL BY LINE PIXEL BY CLOCK X CROP SIZE Y CROP SIZE Luts Flip-Flops Bram DSP48 System MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series & Ultrascale Documentation Design Specification Validation specification Implementation specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Isim / QuestaSim Vivado / 032 NEXIP

33 Dead pixel correction Dead pixels are a common issue in vision systems and appear randomly on sensor images. This phenomenon is seen on any sensors even brand new ones. In order to solve this problem, Nexvision has designed the Dead pixel correction IP able to replace every single dead pixel by its closest neighbor. Up to 200 MHz system clock Multi-pixels by clock Low power management with global clock enable control. Two dead pixel detection sources: o External detection along with video bus o Detection generation from a dead pixel table, available only for 1 pix/clk Works with Monochrome or Bayer pattern pixel organization All vision systems / RESOURCES & PERFORMANCE Device XILINX ARTIX7 (XC7A200TFBG484-3) Generic Parameter Device Resources PIXEL SIZE PIXEL BY CLOCK DETECTION SENSOR Nb DEAD PIXEL Luts Slices Bram DSP Internal 20 Mpx External 20 Mpx External 20 Mpx / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series & Ultrascale Documentation Design Specification Validation specification Implementation specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Vivado Isim or ModelSim Vivado NEXIP 033 /

34 Light Ring best Shot The goal of this IP is to capture a series of 8 frames with different LED illumination configurations defined by registers. It enables to see an object with different light expositions while waiting for a proper exposure of each frame. 4 x (RGB 10 bits) pixels by clock. Controls 8 LEDs around the sensor. Industrial inspection/machine Vision Quality Assurance Microscopy Embedded Systems / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Performance Luts Flip- Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Files Example Design Test Bench Model Constraints File Design Specification UCF Design Entry ISE 14.6 Isim ISE / 034 NEXIP

35 Color matrix correction In camera, incoming light is split by filters into the three RGB primary colors. As filters haven t the same response curve, RGB image from sensor has unadjusted colors. This IP corrects RGB colors delivered by the sensor. RGB image Real time matrix update Matrix 3x3 and offset Generic Interface Size of a pixel: 8 to 12 bitsv Number of pixel by clock: 1 to 16 / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7K70T-2FBG484) Generic Parameter Device Resources Performance Number pixel by clock Size of a pixel Luts Flip-Flops Bram DSP48 Fmax 8 3x12 bits x MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 6, 7 & Ultrascale series Documentation Design Files Example Design Test Bench Model Constraints File Design Specification Design Entry Suite ISE & Vivado NEXIP 035 /

36 Demosaicing-Linear interpolation The NexVision IP Demosaicing is a generic algorithm of CFA Bayer pattern to RGB. The aim of this IP is to be used with all Image sensors (with basic Bayer pattern). It is based on a linear Interpolation method using 5x5 filters. Multi-pixels by clock Power Management: Sleep Mode Generic Interface o Size of a pixel (PIX_SIZE): 8 to 12 bit o Nb Pixel by clock (PIX_BY_CLK): 1 to 16 o Size of the Image PIX_ROW x PIX_COLUMN ( nb of ROW and nb of column) Real-Time adaptation of the CFA (Color Frame management) / RESOURCES & PERFORMANCE Device ARTIX 7 XC7A200TFBG484-3 Generic Parameter Device Resources Performance Number pixel by clock Size of a pixel Pix column Luts Flip-Flops Bram DSP48 Fmax MHz MHz MHz MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Reference Model Constraints File Matlab XDC Design Entry Suite Isim, QuestaSim, Matlab Vivado / 036 NEXIP

37 FPN : Fixed Pattern Noise 2 Points correction DSNU & PRNU Nexvision FPN 2 points correction IP is made to compensate fixed pattern noise issues from an image driver. Corrective algorithm used is based on a coefficient table dependant on sensor s physical characteristics. Various input parameters award great flexibility of use for all type of image sensors. Global Sleeping Mode (option) Power management: automatic idle during frame blanking Generic Interface o Size of a pixel (PIX_SIZE) o Nb pixel by clock (PIX_BY_CLK): o Size for coefficient values o Memory management for reading coefficient values Algorithm built on gain and offset approximation Correction results with fractional approximation Real-Time update of coefficient table Independent memory management for reading input calibration values Industrial inspection/machine Vision Quality Assurance Microscopy Medical Technology Embedded Systems Homeland Security and border surveillance Vison enhancement (automotive or airbone) / RESOURCES & PERFORMANCE Device ARTIX 7 XC7A200TFBG484-3 Generic Parameter Device Resources Number pixel by clock Size of a pixel FPN_A_Size / FPN_B_Size Luts Slice registers Bram DSP48 BUFHCE (*) / BLOCK DIAGRAM Supported Device Family Xilinx 7 series & Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File Not Provided Matlab XDC (*) only if optional sleeping mode is activated Design Entry Suite Isim Vivado NEXIP 037 /

38 IMAGE PROCESSING ENHANCEMENT

39 DYNAMIC RANGE : HDR & NOISE FILTERING > > HDR > > DYNAMIC LOCAL TONE MAPPING > > 3D NOISE FILTER > > CONTRASTS & EDGES ENHANCEMENT > > SPATIAL FILTERS VIBRATION CORRECTION NEXIP 039 /

40 High dynamic range and global tone mapping (16 bits resolution based) High-dynamic-range imaging is a set of techniques used to reproduce a greater dynamic range of luminosity in a picture. HDR images represent more accurately the range of intensity levels found in real scenes. Non-HDR cameras take pictures with a limited exposure range, resulting in the loss of detail in bright or dark areas. HDR compensates for this loss of detail by capturing multiple pictures at different exposure levels and combining them in order to deliver a broader tonal range picture. This IP, therefore, does merging of several exposed pictures and applies a global tone mapping algorithm on the resulting picture prior to deliver it. 4 RGB888 pixels by clock Merge 3 images to 1 stop modes: 1, 2 and 3 stops Real time merging (16bits resolution based) Real time global tone mapping / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Performance Luts Flip- Flops Bram DSP48 DDR Bandwidth Fmax Gbps 200 MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Files Example Design Test Bench Model Constraints File Design Specification Design Entry ISE 14.6 ISE / 040 NEXIP

41 Sharpness Acutance Enhancement Nexvision Sharpness IP is logic IP for enhancing detail and spatial precision in images. Implemented algorithm, aiming acutance enhancement, grants both spatial de-noising and detail enhancement to the output image. This IP is independent from input image color space since it takes into account the presence or not of a luminance component in at its inputs. Multi-pixels by clock Global Sleeping Mode (option) Power management: automatic idle during frame blanking Generic Interface : o Size of a pixel (PIX_SIZE) o Nb Pixel by clock (PIX_BY_CLK) o Presence of input luminance component o Frequency of the update of exposure time o Real time LUT values update Color space independant Border treatment Industrial inspection/machine Vision Quality Assurance Microscopy Medical Technology Embedded Systems Homeland Security and border surveillance / RESOURCES & PERFORMANCE Device ARTIX 7 XC7A200TFBG484-3 Generic Parameter Device Resources Number pixel by clock Size of a pixel Pix column Luts Slice registers Bram DSP48 BUFHCE (*) / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Vivado (*) only if optional sleeping mode is activated Isim Vivado NEXIP 041 /

42 IMAGE ANALYSIS

43 DETECTION, RECOGNITION & TRACKING > > FEATURE POINT EXTRACTION > > PATTERN MATCHING > > LINES DETECTION > > SUSPICIOUS STATIONARY OBJECT DETECTION > > PEDESTRIAN COUNTING > > GESTURE RECOGNITION > > QUERY-BY-CONTENT > > MULTISPECTRAL BAND OBJECT RECOGNITION > > HUMAN BODY DETECTION > > TEXTURE RECOGNITION > > TRAFFIC ACCIDENT DETECTION > > FIRE DETECTION > > COLOR ANALYSIS NEXIP 043 /

44 BICTS : Binary Image Classification Training System Nexvision Binary Image Classification Training System (BICTS) gives to Computer Vision Developers the ability to setup binary classification trainings very easily, without having to deal with cumbersome intermediary tasks. Download your dataset, let yourself be guided by BICTS while setting up the training, and enjoy your freshly new built classification model. SVM Training with HOG features. Negatives auto-cropping. Data preprocessing. Boosted training with Multi-Process Mode. Guided configuration setup. Dynamic out-of-memory prevention system. Post-Recommandations on Model usage. Very well-tested on pedestrian INRIA Dataset. / PIPELINE / 044 NEXIP

45 Pedestrian Detection The pedestrian Detection module detects walking pedestrians within various and changing environments in real time. Powered with Machine Learning and Computer Vision Algorithms, it shall give you solid & relevant detections. Real time detection on embedded devices. Compatible with all NVIDIA CUDA-enabled devices including with Tegra K1/X1 processors. Ability to train you own detector from a dataset. Provide APIs allowing the user to have control over robustness and/or speed. Subway Surveillance Driving Assistance Embedded Systems / RESOURCES & PERFORMANCE Device : Embedded NVIDIA Tegra K1 (A15 + GK20A) Device Resources Performance Architecture Compute Capability CUDA Cores GPU Clock L2 Cache Memory Bandwidth Fmax Kepler MHz 128 KB 14 Gb/s 20 Hz on 640x480 Images Device : NVIDIA Quadro K620 Device Resources Performance Architecture Compute Capability CUDA Cores GPU Clock L2 Cache Memory Bandwidth Fmax Maxwell MHz 2048 KB 28 Gb/s 100 Hz on 640x480 Images Supported Device Family NVIDIA CUDA-enabled Devices Documentation Technical report version 0.8 Host language Device language C/C++ CUDA NEXIP 045 /

46 Line Tracking Versatile Line Tracker for Transportation Vehicles Designed specifically for transportation vehicles, this module dynamically adapts itself to the surrounding environment. Whether the vehicle moves across rails or highways, the driver shall be shown relevant & robust tracks. In addition to that, it provides lane departure warnings. Real-time Processing on embedded platforms. Versatility: Application to automotive, tramways, trains and so on Flexibility: Provides APIs allowing user to have control over robustness and/or speed. Lane Departure Warnings. Leverages CUDA / GPGPU Technology. / PERFORMANCE (IN FRAME / SECONDS) TEGRA K1 / X1 (Embedded) WORKSTATION (Intel i7, Quadro K620) Up to 30 Up to 150 / SCREENSHOTS / 046 NEXIP

47 T-DAPS Tramway Driver Assistance for Pedestrian s Safety T-DAPS system is a module built especially for the Tramway vehicle market. Powered with advanced machine learning & Computer Vision Algorithms, it has been designed from our handcrafted proprietary sub-modules (i.e Pedestrian Detection IP & Line Tracking IP). This environment-aware driver companion will make tramways definitely safer for nearby pedestrians. Real time Processing on Embedded platforms. Simultaneous Rail detection and Pedestrian detection. Support for Multi-GPU hardware. Support for CPU Multithreading. Leverages CUDA / GPGPU Technology. Flexibility: Provides APIs allowing user to have control over robustness and/or speed. / PERFORMANCE (IN FRAME / SECONDS) TEGRA K1 / X1 (Embedded) WORKSTATION (Intel i7, Quadro K620) Up to 30 Up to 100 / SCREENSHOTS NEXIP 047 /

48 Target Tracker Non-predefined target robust tracking algorithm This algorithm is a detector based tracker, focusing on features in the image. It is initialized at runtime on the desired target, then the tracker builds and updates its object model to capture the target position in the video sequence. It takes into account the object deformation without forgetting its initial shape. It is thus robust to object deformation, rotations, occlusions and exit of camera view. Online tracker (target defined at runtime) Upgradable target model Robustness to : occlusions, object deformation and exit of camera view / OBJECTIVES Tracker s main performance is robustness. It is made to match state of the art tracking performance compared to competing products and even outperforming them in real usage case. It can be used in assistance system (ADAS, APAS) to stabilize an automatic driver controller. / SPECIFICS Cross platform C++ Customer customization required 25 FPS on NVTK1 platform / SCREENSHOTS This tracker is initialized on an unknown target and captures the target position in the video sequence. / 048 NEXIP

49 NEXIP 049 /

50 VIDEO OUTPUT

51 DISPLAY > > MICROOLED > > LCD I/O > > COMPOSITE > > HDMI > > SDI (3G-HD) > > CoaXPress NEXIP 051 /

52 SDI HD-3G 3G or HD SDI Speed configurability All in one system (SDI, control, GTX) Parallel TX and RX communications AXI interface for adaptability and controllability Optimized interface in terms of number of signals Video transmission / reception over SDI link / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Performance Luts Based on 3G SDI IP of Xilinx, this IP includes GTX modules and an AXI lite interface module to ease configuration and control. The IP provides independent TX and RX communications channels, YUV bits. As GTX Module is already included, it enables final user to not bother about high speed interface configuration. Flip- Flops Bram DSP48 Fmax ,5 MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File /Verilog Mixed Provided XDC Design Entry Vivado Isim Vivado / 052 NEXIP

53 CoaXPress TX This module is a CoaXPress transmitter. It handles low-level link CoaXPress protocol functionality to enable a device to connect to image receivers like frame-grabbers. It enables to send and receive low-level CoaXPress messages and to send image stream data. Inputs of up to 4 parallel data streams of 8/10/12/14/16 bits. Provides an AXI interface for control. Deals with GPIO and trigger packets. The serial receiver of this IP uses a low-speed link. The serial transmitter has to be connected to a transceiver to achieve up to 3.125GBps of bandwidth. Industrial inspection/machine Vision Quality Assurance Microscopy Embedded Systems Data transmission / BLOCK DIAGRAM / RESOURCES & PERFORMANCE Supported Device Family Xilinx 7 series Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Performance Documentation Design Specification Luts Flip- Flops Bram DSP48 Fmax MHz Design Files Example Design Test Bench Model Constraints File /Verilog XDC Design Entry Vivado Isim Vivado NEXIP 053 /

54 CoaXPress RX This module is a CoaXPress receiver. It handles low-level link CoaXPress protocol functionality for a host to connect to image sources such as cameras. It allows user to send and receive low-level CoaXPress messages and receive image stream. Output of 4 parallels data stream of 8/10/12/14/16 bits. Provides an AXI interface for control. Deals with GPIO and trigger packets. The serial transmitter of this IP uses a low-speed link. The serial receiver has to be connected to a transceiver to achieve up to 3.125GBps of bandwidth. Industrial inspection/machine Vision Quality Assurance Microscopy Embedded Systems Data transmission / BLOCK DIAGRAM / RESOURCES & PERFORMANCE Supported Device Family Xilinx 7 series Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Luts Flip- Flops Performance Bram DSP48 Fmax MHz Documentation Design Files Example Design Test Bench Model Constraints File Design Specification /Verilog XDC Design Entry Vivado Isim Vivado / 054 NEXIP

55 NEXIP 055 /

56 DATA LINK

57 DATA LINK > > PCIe > > USB 2.0, 3.0 et 3.1 (FX3) > > NVMe / SSD > > Fiber-optic interconnect NEXIP 057 /

58 USB3 : Cypress FX3 Interface This IP provides an interface to Cypress EZ-USB FX3 component. It provides, through the GPIF2 interface, read/write accesses to single registers, for system control, and to pipes interfaces, for large data transfers. Supports FX3 32bits or 16 bits data interface. Supports 3 different input pipes and 2 output pipes for data flow. Provides 4 output registers and 10 input registers for general purposes control Pipe buffer size configurable default to 4KB. Output clock configurable for optimized interface timings. high speed data transfer over USB3 / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Generic Parameter Device Resources Performance Data bus size Clock inversion Endpoint buffer size Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Verilog Provided Constraints File Design Entry Vivado Isim Vivado / 058 NEXIP

59 NEXIP 059 /

60 MISCELLANEOUS

61 MISCELLANEOUS > > Memory test > > Master AXI Lite Intf > > AXI Master Interface > > Axi Lite Slave Intf > > Flash SPI Controller > > I2C driver MOTOR CONTROL > > SSI-6 > > PID Controller > > PWM > > Sensored Brushless motor control NEXIP 061 /

62 Memory Test Memory test IP intends to be connected to Xilinx MIG memory controller IP. It runs intensive test to memory devices check their integrity. Error status reports failed tests, data bits where an error has been detected and memory addresses where errors happened. 6 different tests : Walking 1 s, Walking 0 s, March C-, Checkerboard, Walking Address, and Mask test MIG AXI4 Interface or User Interface supported 2:1 and 4:1 PHY to controller clock frequency ratio supported Configurable through an AXI-Lite Interface Auto-test mode: Start a full test when system starts Error status outputs Memory Test IP can be used for Built-In Self Tests and hardware debug. / RESOURCES & PERFORMANCE Device XILINX ARTIX 7 series Generic Parameter Device Resources Performance AXI4 INTF ACTIVE APP DATA WIDTH BRAM ADDR WIDTH Luts Flip-Flops Bram DSP48 Fmax NO 256 bits 10 bits x36K MHz YES 256 bits 10 bits x36K MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File Provided XDC Design Entry Suite Isim Vivado / 062 NEXIP

63 Master AXI4 Lite Master AXI4 Lite IP enables through its generic interface an upstream master which is not AXI4 Lite compliant to communicate with a Slave that has an AXI4 Lite interface and thus initiate Read and Write requests. 32 or 64 bits data bus. Internal Clock Domain Crossing management. Transaction s ID provided (optional). End of transaction Acknowledgment signals provided to Upstream master. Medical technology Embedded systems Vision enhancement (automotive or airborne) / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325TFFG900-2) Generic Parameter Device Resources Performance Addr_width data_width Resp_width Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series, zynq, Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File /Verilog XDC Design Entry Suite Isim Vivado NEXIP 063 /

64 AXI4 Master Interface AXI4 Master IP enables, through its generic interface, an upstream non AXI4 compliant master to communicate with a slave that has an AXI4 interface and thus initiate Read and Write bursts. Independent clock support AXI4 Compliant 32 to 1024 bits data bus Customizable AXI ID width FIFO for improved read burst performance Every system implementing an AXI4 communication bus that needs to interface with a non AXI4 compliant master. / RESOURCES & PERFORMANCE Device Generic Parameter Device Resources Performance Addr_width data_width ID_width Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series, zynq, Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Xsim, QuestaSim Vivado / 064 NEXIP

65 AXI Lite Slave The IP provides a seamless interface between an AXI Lite bus system and an IP which is not natively AXI Lite compliant. It deals with clock domain crossing from AXI domain to Slave domain. Handles R/W registers and RO registers interface from AXI side. Number of registers configurable Provides lock mechanism for exclusive accesses Power aware with intensive automatic clock gating Every system implementing an AXI lite communication bus that needs to interface with a non AXI Lite compliant slave / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325TFFG900-2) Generic Parameter Device Resources Performance R/W RO Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Vivado Isim Vivado NEXIP 065 /

66 I2C Driver I2C Driver IP delivers a generic interface for an I2C slave module. Its purpose is to provide a communication channel to an I2C module whatever the Master is. For Instance, in the Block diagram below, it interfaces an AXI4 lite Master to an I2C slave module. AXI slave and AXI Master IPs can be provided aside. Multi I2C Slave START and STOP generation Repeated START generation Acknowledge bit generation/detection 7 bits or 10 bits addressing Transmission and reception FIFO size configurable ( by default 2048 bytes deep) Reset the communication. / RESOURCES & PERFORMANCE Device XILINX KINTEX 7 (XC7-K325T-1FFG676) Device Resources Performance Luts Flip- Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model /Verilog Verilog Design Entry Suite Isim Vivado / 066 NEXIP

67 Flash SPI Controller Flash SPI Controller IP allows an upstream master which is not SPI compliant to communicate with one or several Flash SPI memory, initiating requests with this/these Slave(s) and thus read or store data from/to them. Support 7 Series and Ultrascale families. SPI Single supported, Dual and Quad not supported. Up to 256 Memory slaves. SPI mode 0, 3 supported (mode 1, 2 are optional). Memory Calibration, Page Program, Fast Read, Sector and Bulk Erase user commands available. 3 Bytes addressing mode + extender. SPI clock dynamically controlled. Memory automatic calibration done for Fast Read. Possibility to stop a burst operation: Several Page Program, Fast Read or Sector Erase operations. Error flags available for Slave Select, Bulk Erase, Sector Erase, Page Program and Calibration operations. FSM state and address are available for debug. Tested on N25Q512, N25Q256 and M25P80 memories. Medical Technology Embedded Systems Vision enhancement (automotive or airborne) / RESOURCES & PERFORMANCE Device XILINX ULTRASCALE XCKU040 Generic Parameter Device Resources Frequency (MHz) Device_family StartupEx Memory number Luts Flip-Flops Bram DSP48 System SPI ULTRASCALE TRUE / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Ultrascale Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model /Verilog Design Entry Suite Isim, ModelSim Vivado NEXIP 067 /

68 PID Controller This IP is a PID controller use for any regulation. Data_width range from 1 to 64 bits. Coefficients Kp, Ki and Kd. Output limit control thanks to MAX_LIMIT and MIN_LIMIT parameters Electric Motor position or speed regulation Electric Current regulation / RESOURCES & PERFORMANCE Device Generic Parameter Device Resources Performance Data width Max limit Min limit Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Isim Vivado / 068 NEXIP

69 SSI-6 Interface This IP receives data from an external component compatible with SSI-6 protocol and CRC-8 (used to control validity of data received). SSI-6 interface : 22 data bits, 2 status bits, 8 CRC bits. CRC-8 polynomial 0x97, initial data 0x00, no final XOR. Motor control with a Zettlex encoder / RESOURCES & PERFORMANCE Device XILINX ULTRASCALE XCKU040 Generic Parameter Device Resources Performance Freq system Freq SSI Data out width Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Isim Vivado NEXIP 069 /

70 PWM Electric Motor Driver This IP convert a speed setpoint into 6 PWM signals to manage a 3-phases brushless AC motor using a 6-phases driver. PWM frequency = Sys_freq/2000 Control of torque Dead-time switch parameters Pre-charged sinus LUT for PWM generation Electric Motor control with a PI regulation or just a speed setpoint. / RESOURCES & PERFORMANCE Device Generic Parameter Device Resources Performance PWM Speed width Nb Clock Dead time Luts Flip-Flops Bram DSP48 Fmax MHz / BLOCK DIAGRAM Supported Device Family All Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Isim Vivado / 070 NEXIP

71 Sensor brushless motor control This IP allows to control speed or position of a brushless AC motor with sensor. The precision of the control depends on the precision of the encoder. A track mode can be set to keep heading for a define direction thanks to a gyroscope. High precision control IHM to set some parameters via UART Configurable input width I2C interface for the gyroscope or IMU Motor position or speed regulation Stabilization Tracking / RESOURCES & PERFORMANCE Device Generic Parameter Device Resources Performance Theta width UART Baud rate Sys_clk IMU Freq Luts Flip-Flops Bram DSP48 Fmax MHz MHz / BLOCK DIAGRAM Supported Device Family Xilinx 7 series Documentation Design Specification Validation Specification Implementation Specification Design Files Example Design Test Bench Model Constraints File XDC Design Entry Suite Isim Vivado NEXIP 071 /

72 NEXVISION in the world HEADQUARTER NEXVISION SAS Parc Swen Sud, Bât. D2 Hall D4 1 bd de l océan - Impasse Paradou MARSEILLE FRANCE Tel : (+33) contact@nexvision.fr / 072 NEXIP

73 MAIN CUSTOMERS SECURITY / DEFENSE : AEROSPACE : INDUSTRY : CINEMA / MEDIA / SPORT : TRANSPORT : NEXIP 073 /

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