Reconfigurable Optical Interconnections for Parallel Computing

Transcription

1 Reconfigurable Optical Interconnections for Parallel Computing NEIL MCARDLE, MAKOTO NARUSE, HARUYOSHI TOYODA, YUJI KOBAYASHI, AND MASATOSHI ISHIKAWA Invited Paper We describe our research on optically interconnected optoelectronic parallel computing systems. Our architecture is based on a multilayer pipeline of two-dimensional optoelectronic device arrays in which each pixel is composed of an optical input channel, a general-purpose programmable processor, local memory, and a surface-emitting laser diode as an optical output channel. Free-space optics provides parallel, global communication between layers in the pipeline via optical paths that are dynamically reconfigurable. Design and initial realization of a system are described. Keywords Optical computer architectures, optical interconnections, optoelectronic VLSI, parallel optoelectronic computing, smart pixels, spatial light modulators, surface-emitting lasers. I. INTRODUCTION To overcome some of the limitations of conventional interconnection technologies, optically interconnected electronics has been proposed as a solution. Since the predicted number of required input/ouput connections will approach 5000 and off-chip clock rates will reach 2 3 GHz by the year 2009 [1], current interconnection technologies will have severe difficulties in satisfying these requirements. Research in this field has concentrated on retaining silicon VLSI devices as the dominant data-processing technology and, by integrating suitable optoelectronic interface devices such as laser diodes and photodetectors, providing optical communication paths between processors. This approach provides several advantages. First, the limitation on pin I/O density due to pins being placed only around the edge of the die can be overcome by Manuscript received July 22, 1999; revised February 22, N. McArdle, M. Naruse, and M. Ishikawa are with the Department of Mathematical Engineering and Information Physics, Graduate School of Engineering, University of Tokyo, Tokyo Japan ( neil@k2.t.utokyo.ac.jp; naruse@k2.t.u-tokyo.ac.jp; ishikawa@k2.t.u-tokyo.ac.jp). H. Toyoda and Y. Kobayashi are with the Central Research Laboratory, Hamamatsu Photonics K. K., Shizuoka-ken Japan (toyoda@crl.hpk.co.jp; kobayasi@crl.hpk.co.jp). Publisher Item Identifier S (00) providing a two-dimensional array of optoelectronic I/O devices over the surface of the electronic processor. Research in this field has demonstrated thousands of optoelectronic I/O channels [2]. Second, not only does this approach utilize the high bandwidth of optical communication paths, but the links do not suffer from the high-frequency losses, crosstalk, and electromagnetic interference exhibited by conventional connections [3]. Third, and most interestingly from an architectural point of view, the optical communication paths can be easily routed, combined, split, and reconfigured by suitable optical devices and components such as lenses, beam splitters, holographic elements, fiber bundles, and microoptic components. Using the optical domain for connections allows the straightforward implementation of nonlocal topologies. Classes of applications that are ideally suited to such architectures include calculations where the data communication among processors or processing nodes is inherently nonlocal, such as sorting, fast Fourier transforms (FFT s), signal processing, matrix computations, and high-level image processing. Nonlocal communication pathways among distant processing nodes are difficult and expensive (in terms of silicon real estate) to implement in a dense two-dimensional (2-D) plane (such as a silicon chip or circuit board) by conventional interconnection and large-scale integration technologies because the area required by the connection paths becomes large. By extending the interconnection paths into the third dimension by, for example, surface-emitting optical source and detector arrays, free-space optical beams can provide global interconnection pathways among distant (nonlocal) processing nodes. Several special-purpose demonstration machines have been constructed to implement some of these algorithms [4] [6]. In contrast, our systems are based on general-purpose optoelectronic processors capable of performing many of these tasks. An experimental scaled-up image processor known /00$ IEEE PROCEEDINGS OF THE IEEE, VOL. 88, NO. 6, JUNE

2 as SPE-4k was constructed in our laboratory [7], [8]. It contained programmable processing elements (PE s) between an optical input layer composed of discrete phototransitors and an optical output layer composed of discrete light-emitting diodes (LED s). The system was configured as a single-instruction multiple data-stream (SIMD) optoelectronic parallel processor, and several fast, parallel image-processing algorithms were developed and demonstrated. By replacing the discrete phototransistors with an integrated array of 8 8 photodetectors (PD s) and amplifiers, and the LED s by an 8 8 vertical-cavity surface-emitting laser (VCSEL) array, a more compact system called SPE-II was developed [9]. SPE-II was configured as a single layer of a pipeline arranged in a feedback loop: the outputs from the VCSEL array were imaged back onto the input PD array via a reconfigurable interconnection unit (a spatial light modulator). General algorithms such as vector-matrix multiplication were demonstrated to take advantage of the optical reconfigurability. In SPE-II, off-the-shelf imaging lenses and optomechanics were used, resulting in a large system (around 2 1m ). Toward our goal of constructing a very compact, fully integrated system, many of these components were replaced by custom designed optomechanics and microoptic components, resulting in a compact, partially integrated demonstrator called Optoelectronic Computer Using Laser Arrays with Reconfiguration I (OCULAR-I) [10]. OCULAR-I allowed us to investigate and develop many aspects of the experimental system including the design, modeling, and construction of a compact, high-resolution imaging system [11], the construction and evaluation of a custom optomechanical system, testing and characterization of 2-D VCSEL arrays, the construction of a compact interconnection module coupling an optically addressed spatial light modulator (SLM) with a mini-crt device [9], and the development of algorithmic and system modeling work [9], [16]. Due to limited device availability, OCULAR-I was also a single-layer feedback-type configuration, like SPE-II. By extending this architecture, and by utilizing the results of the OCULAR-I system to improve the design and integration aspects, we have designed and are presently constructing a fully pipelined parallel optoelectronic computer known as OCULAR-II, which contains multiple layers. A more detailed account of the historical development of the architecture, technology, and devices has been previously reported [12]. In this paper, we describe the architecture of our OC- ULAR-II system, details of the system components, and the progress made toward its realization. We conclude with a discussion of present and future developments. II. SYSTEM ARCHITECTURE Although integrated optical devices such as VCSEL arrays, PD arrays, and optoelectronic integrated circuits (OEIC s) can have high two-dimensional parallelism for pattern information processing, their capabilities are not fully utilized in conventional parallel processing systems. For example, in high-speed image-processing systems based on conventional cameras, there is a serious bottleneck that arises because the two-dimensional image falling on the camera is converted to a serial signal stream, which is transferred to the processing unit. This type of system has a limited frame rate (for example, corresponding to a video frame time of about 16.7 ms), especially if a large number of pixels are used. Instead, a local processing element can be placed at each sensor in the camera (or photodetector array), thus removing the need for the parallel-to-serial conversion and/or scanning techniques. Our research is motivated by the removal of this bottleneck by integrating processing and optical I/O elements using technologies such as those described above. Thus we can achieve high-speed image processing with frame rates on the order of several hundred thousand kilohertz (a frame time of a few microseconds), which is especially useful for applications such as high-speed target tracking and robotic vision. We use an integrated array of programmable PE s and photodetectors as a smart sensing element. By stacking many of these arrays in a pipelined system, with free-space optical interconnections between them, we can utilize the global connectivity of the optics and the processing functionality of electronics to build a general-purpose machine for various applications. The architecture that we use is based on the pipelined configuration shown in Fig. 1. Here we define a pipeline to consist of several identical layers arranged in a stack, where each layer consists of an optical input array, a processing array, and an optical output array. Between each of the layers there is a free-space optical interconnection system. In each layer of this pipeline, there is a two-dimensional array of PE s on a chip. Each PE contains some processing circuitry, registers, and local memory. The PE s communicate with their four nearest neighboring elements via electrical connections. Also integrated at each PE chip there is a photodetector for optical input and an optical output device such as a modulator, LED, or surface-emitting laser diode. In our demonstrator systems, we use VCSEL arrays. The VCSEL s generate the optical communication paths between layers in the pipeline. Suitable optics, microoptics, and holograms can be used to route the light beams to their destination PE in the next layer. In contrast to conventional electronic parallel processing systems there are three main differences: 1) the input and output (images or two-dimensional representation of general data) are supplied to the processors in parallel; 2) the connections between nonlocal processors are by optical paths; and 3) the interconnection topology is reconfigurable, that is, the light beams can be dynamically redirected. The benefits of the first two points include high connection density and global connectivity. Although low-level image-processing tasks generally use neighborhood connections, some high-level tasks such as moment extraction and feature extraction can benefit from global interconnection paths. Globally optically interconnected parallel processing systems are also well suited for computationally intensive applications where the nature of data flow is inherently nonlocal, such as sorting, FFT s, and signal processing. 830 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 6, JUNE 2000

3 Fig. 1. Pipelined optically interconnected architecture. Fig. 2. Schematic diagram showing implementation of OCULAR-II. The third point allows the machine to use an interconnection topology that is best suited to the data-flow structure of the algorithm being performed and is not fixed as in conventional parallel processors. This ability has the potential to provide improvements in the performance of many algorithms. We can achieve high flexibility of operation due to the programmability of the PE s and the reconfigurability of the optical interconnections. We can therefore implement a variety of operations on our system: image processing, arithmetic, matrix operations, sorting, and signal processing. This is in contrast to other special-purpose optoelectronic computing machines that have been reported, such as FFT processors [4] and sorters [5]. In order to realize high computing performance beyond the limitation of one processing module (one layer in the pipelined system of Fig. 1), optical interconnections play an important role for realizing dense connections in parallel between pipelined layers of PE s. These optical connection paths can provide global connectivity between PE s, which otherwise would require many iterations of the neighborhood electrical connections. Kirk et al.designed a reconfigurable optical interconnection and showed basic experimental results [13] using a phase-modulating parallel aligned spatial light modulator (PAL-SLM), which can display computer generated holograms (CGH s). Using such a device in our system, by changing the phase pattern that is displayed on the PAL-SLM, we can dynamically alter the interconnection paths between the PE s. Based on this system (described in the following section), the topology of our architecture is dynamically programmable. As an intermediate goal of realizing the fully integrated pipelined system shown in Fig. 1, we have designed OC- ULAR-II, which is a two-layer pipelined prototype in which the PD array, PE array, and VCSEL array are discrete units connected via modular, compactly stacked, custom-designed boards integrating optoelectronic devices, drivers, amplifiers, and interface circuitry. Fig. 2 shows a schematic diagram of the system. There are two processing layers in the diagram, each composed of a PD module for optical input, a laser diode (LD) module for optical output, and a PE module containing an array of electronic processing ele- Fig. 3. (a) Photograph of PD, PE, and LD modules coupled together, (b) schematic figure showing the connection, and (c) photograph of LD and PD modules connected to optical interconnection unit. ments. The system has 8 8 channels connected in a fully parallel fashion, i.e., the output from each PD is directly connected to a corresponding PE, which in turn outputs to a corresponding LD. The whole array is controlled in an SIMD fashion. Each PE module is connected to a control computer from which instructions are downloaded. The outputs from the left layer (Layer 1) are conveyed to the inputs of the right layer (Layer 2) via an optical interconnection unit. Fig. 3(a) shows the LD, PE, and PD modules connected together, and Fig 3(b) shows the connection method. The modules are described in the following sections. III. OPTOELECTRONIC MODULES In OCULAR-II, we have integrated an 8 8 array of PE s into a single custom-designed field-programmable gate array MCARDLE et al.: RECONFIGURABLE OPTICAL INTERCONNECTIONS 831

4 Table 1 Specifications of OCULAR-II Fig. 4. Internal architecture of each processing element. (FPGA) chip. The module is configured as a general-purpose 8 8 SIMD array. Each processing element in the PE module has the internal architecture shown in Fig. 4. Each PE contains an arithmetic logic unit (ALU) and local memory and can perform bit-serial arithmetic and logical operations. It has connections to neighboring PE s as well as input and output for the optoelectronic interface. Specifications are shown in Table 1. The internal operation of the PE is described in more detail elsewhere [14]. There are some tradeoffs involved in the design of the PE s. In order for our system to perform a variety of algorithms and applications, our architecture calls for a general-purpose, programmable PE requiring more transistors and therefore a larger area than a special-purpose, nonprogrammable PE. This limits the number of PE s that can be integrated into a single chip. However, for vision and image-processing applications, a large number of pixels are required, ideally approaching or Given the cost and the chip-size limitations of silicon VLSI fabrication, we must design our PE s to be as compact as possible while remaining programmable. The optical input is provided from an 8 8 PIN photodetector array and amplifier array. These devices provide 64 direct outputs for interfacing to the inputs of the 64 PE s. Some specifications are given in Table 1. We use a custom-designed 8 8 silicon PIN photodetector array with a device pitch of 250 m. In one version of the PD module, the amplifier array consists of a 64-channel bipolar transimpedance amplifier array configured as four separate 16-channel chips. These four chips are arranged around the PD chip in the same package and are wire bonded to the PD chip. In another version of the PD module, the amplifier array consists of a 64-channel CMOS transimpedance amplifier array with integrated comparators to give digital output levels. The characteristics of both these versions are presently being evaluated for use in OCULAR-II. As the optical output device, we used an 8 8 array of VCSEL s developed by MODE Corp. The specifications are shown in Table 1. The VCSEL array is mounted on a customdesigned board and is connected to 64 drivers, configured as four 16-channel driver IC s. The output of the VCSEL s is controlled by the PE module or can be externally driven. The specifications of the VCSEL s are given in Table 1. IV. OPTICAL INTERCONNECTION UNIT The optical system consists of a 4f imaging system in a reflection configuration, as shown in Fig. 2. A PAL-SLM is placed at the Fourier plane and displays CGH s for changing the interconnection topology. The PAL-SLM is addressed by a compact liquid crystal television (LCTV) panel that is illuminated by a visible laser diode. To make the system as compact as possible, the optical path is folded several times 832 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 6, JUNE 2000

5 Fig. 5. (a) Schematic diagram of optical interconnection unit and (b) photograph of the interconnection unit. Fig. 6. (a) Photograph of the zooming FT lens and (b) ray traces at three zoom positions. The length of the lens is nominally cm. by mirrors and a prism. A schematic view of the module is shown in Fig. 5(a), and a photograph is shown in Fig. 5(b) [15]. The optical system and the SLM system are described in more detail below. A. Optical System In OCULAR-II, we use a custom-designed, four-element, zooming Fourier transform (FT) lens. This lens is used to construct a 4f imaging system arranged in a reflection configuration, as shown in Fig. 5(a). The dimensions of the optical interconnection unit are mm, and its weight is 2.16 kg. The PD and LD module are slightly smaller, as shown in Fig. 3(c). Referring to Fig. 5(a), light from the VCSEL array is incident on a prism, the optical axis is folded by two mirrors, and the light is incident on the FT lens. The lens collimates the VCSEL beams, and the collimated light is incident upon a PAL-SLM, which is placed at the Fourier plane of the FT lens. The light is phase-modulated according to the CGH pattern displayed on the LCTV (described below), is reflected, and passes again through the FT lens. The output light is directed toward the PD array by the mirrors and the prism. An aperture-division technique is used to separate the input and output light, so that the output light travels along a different path from the input light and is deflected by the prism toward the PD array. In this way, the VCSEL module, the optical interconnection unit, and the PD module can be stacked together very compactly. The lens is shown in Fig. 6(a), and some ray traces at three different zoom positions are shown in Fig. 6(b). The focal length of the lens is adjustable from 360 to 440 mm, which allows the magnification to be slightly adjusted in order to easily align the output light spots into the photodetector windows. Some specifications of the lens are shown in Table 1. At the zoom positions mm, mm, and mm, the number is 14.4, 16.0, and 17.6, respectively. The entrance pupil diameter at all positions is 25 mm. Fig. 7 shows an image of the VCSEL array (the letters T and U ) after passing through the optical interconnection unit. Some initial characterization of the optical system indicates that the lens aperture and number are not ideally matched with the output beams from the VCSEL array. The MODE Corp. VCSEL s work in multimode operation, and we have measured the divergence angle to be about 10 (full angle). For these reasons, a large proportion of the beam is not collected by the FT lens. On the return path (after reflection at the SLM no phase pattern displayed), the light throughput efficiency at the PD plane was measured to be 60%. The total throughput efficiency from the VCSEL plane to the PD plane was measured to be only 3.6%. That is, for a VCSEL output power of approximately 1.95 mw, we measured a power of mw at the PD plane. This power is insufficient to operate the PD module. Although a detailed analysis and identification of the sources of loss in the system has not been completed, most of the loss is due to the zooming FT lens and the mismatch in numerical apertures between the FT lens and the VCSEL s. There are some options to overcome this problem in future. For example, although the zooming FT lens was chosen to allow adjust- MCARDLE et al.: RECONFIGURABLE OPTICAL INTERCONNECTIONS 833

6 Fig. 8. Phase modulation characteristic of the PAL-SLM coupled to an LCTV. Fig. 7. Image of the VCSEL array after passing through the optical interconnection unit. ment of the magnification for ease of registration of the spot array with the PD array, a simpler lens with a higher numerical aperture could be used if the mechanical tolerances of the system are stricter. Another approach would be to attach a microlens array to the LD module so that a larger proportion of the light from the VCSEL s is collected. However, this approach would also require stringent alignment requirements and may introduce diffraction losses. Another approach would be to use a VCSEL array with a smaller divergence angle, and we are currently investigating such a VCSEL array in an alternative LD module. B. SLM System The optical interconnection unit uses a phase-modulating SLM. The necessary phase patterns to perform the desired interconnection topology can be displayed on the SLM. The SLM is an optically addressed parallel aligned liquid crystal spatial light modulator (PAL-SLM, Hamamatsu Photonics X5641). It uses an amorphous silicon ( -Si) layer as an optical addressing material and a parallel aligned nematic liquid crystal layer as a light modulation material [9]. All characteristics, such as matching the mirror reflectivity to the VCSEL wavelength and adjusting the liquid crystal and amorphous silicon thicknesses, were optimized for use in OCULAR-II. The addressing and modulation layers do not have pixellated structures. In electrically addressed SLM s such as liquid crystal displays, a grating-like structure associated with the addressing line matrix causes diffraction of light into higher orders and a reduction in the active area (aperture ratio). This causes efficiency problems on the reconstructed image of a CGH. On the other hand, in an unpixellated device, there is no diffraction of light into higher orders and no reduction in the active area, and the PAL-SLM performs phase-only modulation with a high diffraction efficiency of more than 30%. In order to control the SLM by a computer, it is coupled to a 1.3-in XGA LCTV panel (Sony LCX023BL) having pixels with a 26- m pitch horizontally and vertically. The LCTV panel was coupled to the PAL-SLM by using an array of gradient-index rod lenses, a SELFOC lens array (SLA manufactured by Nippon Sheet Glass). The SLA is mm, with an imaging distance (distance from object to image plane) of 32.0 mm. Although the SLA has a relatively low resolution [about 10 lp/mm at 50% modulation transfer function (MTF)], the extremely short imaging distance allowed us to construct a very compact interconnection unit, which was controllable by a computer but did not suffer from the drawbacks of a pixellated electrically addressed SLM. The PAL-SLM in this configuration is capable of multilevel phase-only modulation. Some measured phase modulation characteristics are shown in Fig. 8. Although a phase modulation of 3 or more is available, the CGH patterns used for testing were binary phase CGH patterns, and therefore the phase modulation used was radians. The performance of the SLM system was evaluated by using a CGH, which has the function of performing a multicast (fanout or broadcast) operation, both 1 to 2 multicast and 1 to 4 multicast. The results are shown in Fig. 9(a) and (b), respectively. Since these are binary, space-invariant interconnection patterns, the output patterns exhibit rotational symmetry about the central zero-order spot. The presence of a significant zero-order spot in these pictures indicates that the applied phase modulation was not exactly radians. Since only one of the diffraction orders would be used to interconnect to the PD module, the central zero-order spot does not fall on the PD array. However, to improve efficiency, the central spot should be reduced as much as possible. This could be done by improving and more carefully controlling the coupling between the LCTV and the PAL-SLM. The low frame rate of the PAL-SLM is currently a major drawback for high-speed optoelectronic computing. However, the frame rate of the interconnection module need not necessarily be as high as that of the processing elements. For 834 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 6, JUNE 2000

7 Fig. 9. Binary CGH phase patterns displayed on the SLM together with the output spots in the PD plane. (a) shows a multicast 1 to 2 operation and (b) shows a multicast 1 to 4 operation. example, possible applications include an application that requires the interconnection topology to be configured just once before processing begins; an application in which the topology must be reconfigured, for example, every few thousand clock cycles or every few hundred clock cycles; and at the other end of the scale, an application in which the topology must be reconfigured at the same rate as the processor clock. Our present interconnection module devices limit our applications to the former, although we are currently investigating faster interconnection devices for future systems. Since the interconnection module must be addressed by a two-dimensional pattern (a CGH phase pattern, for example), there is also a communication bottleneck if many patterns must be transmitted to the SLM at high frame rates, ultimately at the processor clock rate. However, some of our previous studies have shown that only a relatively small number of interconnection patterns are required for any given algorithm, for example, a few different spatial shift and broadcast (fanout) connections [11]. In that case, it would be relatively easy to construct a high-speed frame memory for storing a variety of precalculated CGH patterns, which could be quickly dumped to the SLM and switched at high frame rates (with parallel addressing if necessary). C. Optomechanics One of the important issues is the miniaturization of the dimensions of optical interconnection systems so as to meet the requirement of available space in particular applications. For example, an optical interconnection system may need to be small enough to be inserted into an information processing system or a communication system. In our applications, the optical systems that connect PE planes via the SLM should be designed and built as powerful and compact plug-in modules in order to easily extend the system architecture. The custom designed optomechanical system should satisfy certain requirements: it should be compact, mechanically and thermally stable, reliable, easy to fabricate (to reduce costs), easy to align, and modular in design to allow easy construction of the pipelined/hierarchical architectures. Commercially available optomechanical positioning and mounting systems do not satisfy all of these requirements; therefore we developed a custom system. A photograph of this system is shown in Fig. 5(b). By folding the optical path, and by using microoptical components, such as the SLA, the optical interconnection unit is compact. Fig. 3(c) shows a photograph of the interconnection unit with the LD module and the PD module attached at the left and right, respectively. Alignment is achieved by adjusting the mirrors in the optical interconnection unit, the focal length of the zooming FT lens, and the tilt of the LD and PD modules, which are attached to the optical interconnection unit by tilting stages. It is difficult to quantify the alignment issues. Although the system provides some mechanisms to relax the difficulties, such as the adjustable magnification of the FT lens, the relatively large PD windows, and the addition of observation ports at the PD plane, it is still a difficult task to align such a complex system. The system is designed to be modular so that many layers of these modules can be stacked together to construct an extended pipeline. V. APPLICATIONS AND ALGORITHMS Using the reconfigurable optical interconnections, the topology of the system can be programmed to suit the structure of the problem being solved. By utilizing the ability to perform connections beyond the neighborhood of a PE, our system can efficiently implement operations, which are inherently globally connected. These include matrix operations, sorting, signal processing, and fast Fourier transforms. We can achieve the necessary global connections in the optical domain (which can be either reconfigurable or fixed). We are developing a framework by which an arbitrary application can be embedded into an optically connected hierarchical architecture of the type shown in Fig. 1. Analyzing such systems from an algorithmic viewpoint, we evaluate some basic tendencies considering both the performance of optical interconnections and the calculation time for an application [16]. By using the reconfigurable interconnection unit, various functions can be performed, such as a one to many interconnection (broadcast) and a spatial shift interconnection (summation). Some previous research [16] has shown that we can still achieve performance benefits with low-level broadcast and summation operations, that is, fanning out to just a few pixels and shifting by just a few pixels (for example, two, four, or eight). This reduces the complexity required in the CGH s, the resolution required of the SLM, and the performance requirements of the imaging system. Typical algorithms such as matrix-vector multiplication, dynamic programming, and sorting can be implemented by successive application of these broadcast and summation operations. Further investigations in this field are underway. VI. FUTURE WORK Many developments are currently under way within our laboratory. Much of the efforts for future systems concern MCARDLE et al.: RECONFIGURABLE OPTICAL INTERCONNECTIONS 835

8 further integration, for example, integration of the PD array with the PE array. This is relatively straightforward, given the recent advances of VLSI integration, since both devices rely on silicon. For the PE array chips, in our laboratory we are designing chips with integrated photodetectors and more compact PE s to match the pitch of commonly available VCSEL arrays (125 and 250 m). This can be achieved by optimizing the layout of each pixel, reducing the number of transistors used, and using CMOS with a smaller feature size. As an example of what is possible with current technology, a related project in our laboratory (so-called Vision Chip ) uses a chip that has a array of PE s (with an almost identical design to that shown in Fig. 4) with a horizontal and vertical device pitch of 150 m. There is also an integrated silicon PD at each pixel with an area of approximately m. There is also some simple receiver and amplifier circuitry at each pixel. The number of transistors for each PE is 527. The complete chip (which includes some specialized vision processing circuitry) is 5 5mm. The technology used was a m CMOS three-metal process. This chip can operate at clock rates of 100 MHz and is used for parallel high-speed vision applications, such as robot vision and real-time image processing. We plan to use some of these techniques and experience in future OCULAR systems. For future OCULAR systems, we need to integrate the PD array, amplifiers, and comparators with the CMOS PE s. In order to include the VCSEL array with the PD and PE s to make a completely integrated unit, we are investigating various bonding techniques, some of which have been successfully used by other researchers [17], [18]. Keeping the PE pitch the same as the VCSEL pitch also allows simplified unit magnification relay optics to be used. Another advantage of increased integration density is to allow more circuit area for features such as fast, sensitive, and low-power optical receivers, analog-to-digital converters for grayscale image processing, and increased local memory and functionality for each PE. There is a slight mismatch between the wavelength of the PD s and the VCSEL s (see Table 1). Further work needs to be done to resolve this, for example, by lowering the VCSEL wavelength or by increasing the PD wavelength range well above 800 nm, possibly by using GaAs devices. Most of the efforts of VCSEL device manufacturers are concentrated on one-dimensional linear arrays because of their rapidly growing use in parallel fiber optical links. However, two-dimensional VCSEL arrays have recently become available in sizes up to about 8 8 devices with a pitch of 125 or 250 m for optical interconnections. One of the major problems in making larger arrays is heat dissipation when all devices are operating at the same time. However, to overcome this problem, many researchers are investigating techniques to reduce threshold currents and improve efficiency [19]. Heat dissipation is not only a problem for VCSEL s. When densely packed electronic PE s are integrated with optical detectors, receivers, amplifiers, and laser diode driver circuitry, all operating at high clock rates (hundreds of megahertz to 1 GHz), then heat removal becomes a serious problem. However, efforts to make compact, low-power, high-speed electronics, receivers, and VCSEL drivers for optical interconnections should alleviate this problem [20]. We can also make more use of microoptics, diffractive optical elements, and custom-designed optical packaging and optomechanics. This would allow us to further reduce the system volume and number of components required. This has the advantages of reduced cost and increased stability, reliability, and alignment tolerances. The SLM we are currently using is a nematic liquid crystal device and therefore suffers from relatively slow response time (around 70-Hz frame rate). Using SLM s based on ferroelectric liquid crystals or multiquantum-well semiconductor modulators would drastically improve the response times. Some further work needs to be done to determine the optimum reconfiguration rate of the optical interconnections for various algorithms and applications. By taking a modular approach in the design of the optics and optomechanics, we have demonstrated the ease of extending our system to more complex architectures, for example, those consisting of several layered arrays in a pipeline. Other work in our laboratory is investigating alternative architectures for parallel optoelectronic processing. As mentioned in Section V, various types of algorithms can be implemented on OCULAR-II. We are investigating the mapping of algorithms such as sorting, image processing, matrix operations, and data-base searching onto the OCULAR-II architecture such that the algorithms effectively use the reconfigurability to achieve performance improvements. VII. SUMMARY We have constructed a parallel processing system for a variety of applications. Extending our previous work on scaled-up system demonstrators, we have designed and are constructing a fully pipelined, two-layer system known as OCULAR-II. By using VCSEL surface-emitting laser arrays, we utilize free-space optics for global connectivity between layers of optoelectronic processing element arrays, and the use of a phase modulating SLM allows the dynamic reconfiguration of the optical interconnection paths. OCULAR-II is an intermediate step to realizing a fully integrated, multilayer pipelined parallel processing system. It is a demonstration system that allows us to investigate issues such as architectures, interfacing and control, optical interconnection, reconfigurable topologies, packaging, alignment, applications, and algorithms. Although the processing layers are implemented as separate components, the specifications and dimensions of the FPGA PE array, VCSEL array, and PD array are very similar to those that would be achieved if complete integration was possible. By compactly integrating optoelectronic input and output devices with electronic processing elements and optical communication paths, we can demonstrate compact, general-purpose parallel optoelectronic processing systems. These systems are capable of performing a variety of tasks from low- 836 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 6, JUNE 2000

9 level image processing to globally interconnected signal processing and sorting operations. REFERENCES [1] The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, [2] K. W. Goosen, J. A. Walker, L. A. D Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, and D. A. B. Miller, GaAs MQW modulators integrated with silicon CMOS, IEEE Photon. Technol. Lett., vol. 7, pp , [3] A. V. Krishnamoorthy and D. A. B. Miller, Scaling optoelectronic-vlsi circuits into the 21st century: A technology roadmap, IEEE J. Select. Topics Quantum Electron., vol. 2, pp , [4] R. G. Rozier, F. E. Kiamilev, and A. Krishnamoorthy, Design of a parallel photonic FFT processor, in Proc. MPPOI97. Los Alamitos, CA, 1995, pp [5] M. P. Y. Desmulliez, F. A. P. Tooley, J. A. B. Dines, N. L. Grant, D. J. Goodwill, D. Baillie, B. S. Wherrett, P. W. Foulk, S. Ashcroft, and P. Black, Perfect-shuffle interconnected bitonic sorter: Optoelectronic design, Appl. Opt., vol. 34, pp , [6] J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, and A. A. Sawchuk, Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: System demonstration and performance scaling, Opt. Comput., OSA Technic. Dig. Ser., vol. 8, pp , [7] M. Ishikawa, Parallel optoelectronic computing systems and applications, Inst. Phys. Conf. Ser., pt. I, no. 139, p. 41, [8], Optoelectronic parallel computing system with reconfigurable optical interconnection, Crit. Rev., vol. CR62, pp , [9] N. McArdle, M. Naruse, T. Komuro, H. Sakaida, M. Ishikawa, Y. Kobayashi, and H. Toyoda, A smart-pixel parallel optoelectronic computing system with free-space dynamic interconnections, in Proc. MPPOI96. Los Alamitos, CA, 1996, pp [10] M. Ishikawa and N. McArdle, Optically interconnected parallel computing systems, IEEE Comput., pp , Feb [11] N. McArdle, M. Naruse, T. Komuro, and M. Ishikawa, Experimental realization of a smart-pixel parallel optoelectronic computing system, in Proc. MPPOI97. Los Alamitos, CA, 1997, pp [12] N. McArdle, M. Naruse, and M. Ishikawa, Optoelectronic parallel computing using optically interconnected pipelined processing arrays, IEEE J. Select. Topics Quantum Electron., vol. 5, no. 2, pp , [13] A. Kirk, T. Tabata, and M. Ishikawa, Design of an optoelectronic cellular processing system with a reconfigurable holographic interconnect, Appl. Opt., vol. 33, pp , [14] T. Komuro, I. Ishii, and M. Ishikawa, Vision chip architecture using general-purpose processing elements for 1ms vision system, in Proc. 4th IEEE Int. Workshop Computer Architecture for Machine Perception (CAMP 97). Los Alamitos, CA, 1997, pp [15] H. Toyoda, Y. Kobayashi, N. Yoshida, Y. Igasaki, T. Hara, N. McArdle, M. Naruse, and M. Ishikawa, Compact optical interconnection module for OCULAR-II: A pipelined parallel processor, Optics in Computing 99 Tech. Dig., pp , [16] M. Naruse, N. McArdle, H. Yamamoto, and M. Ishikawa, An algorithmic approach to hierarchical parallel optical processing systems, Optical Computing (OC 96) Tech. Dig., vol. 1, pp , [17] S. Matsuo, K. Tateno, T. Nakahara, H. Tsuda, and T. Kurokawa, Use of polyimide bonding for hybrid integration of a vertical cavity surface emitting laser on a silicon substrate, Electron. Lett., vol. 33, no. 12, pp , [18] R. Pu, E. M. Hayes, R. Jurrat, C. W. Wilmsen, K. D. Choquette, H. Q. Hou, and K. M. Geib, VCSEL s bonded directly to foundry fabricated GaAs smart pixel arrays, IEEE Photon. Technol. Lett., vol. 9, no. 12, pp , [19] P. D. Dapkus, M. MacDougal, G. M. Yang, and Y. Cheng, Ultralow threshold VCSEL s for application to smart pixels, Smart Pixels Tech. Dig. IEEE/LEOS Summer Topical Meetings, p. 5, Aug [20] T. K. Woodward, VLSI-compatible smart-pixel interface circuits and technology, Smart Pixels Tech. Dig., IEEE/LEOS Summer Topical Meetings, p. 65, Aug Neil McArdle received the B.Sc. degree in laser physics and optoelectronics from the University of Strathclyde, Scotland, in 1990 and the Ph.D. degree in physics from Heriot-Watt University, Scotland, in He was a Visiting Researcher in the Department of Mathematical Engineering and Information Physics, Graduate School of Engineering, University of Tokyo, from 1995 to 1999, and a Postdoctoral Researcher at Heriot-Watt University and the University of Erlangen-Nuremberg, Germany. His research interests include optoelectronic computing, optical interconnections, and optical design. Dr. McArdle is a member of the Institute of Physics and the Optical Society of America. Makoto Naruse received the B.S., M.S., and Ph.D. degrees from the University of Tokyo, Tokyo, Japan, in 1994, 1996, and 1999, respectively, all in engineering. He is a Research Associate in the Department of Mathematical Engineering and Information Physics, Graduate School of Engineering, University of Tokyo. Dr. Naruse is a member of the Japanese Applied Physics Society and the Optical Society of America. Haruyoshi Toyoda received the B.E. degree in the Department of Instrumentation, Keio University, Japan, in He is a Researcher in the Central Research Laboratory of Hamamatsu Photonics. From 1987 to 1989, he was on leave at the Industrial Products Research Institute in the Ministry of International Trade and Industry. He was engaged in research and development of optical neural networks. He is presently with the 4th Research Group, Central Research Laboratory of Hamamatsu Photonics. He has been engaged in research on optical computing and parallel processing. Mr. Toyoda is a member of the Japan Society of Applied Physics. Yuji Kobayashi received the B.E. degree in mechanical engineering from Waseda University, Japan, in He is a Senior Researcher in the Central Research Laboratory of Hamamatsu Photonics. He has been with the optical information processing research group at Hamamatsu Photonics K.K., Hamakita, Japan. His research interests include photography, optical computing, optical measuring, optical system design, and spatial light modulators. Mr. Kobayashi is a member of the Japan Society of Applied Physics. Masatoshi Ishikawa received the B.S., M.S., and Ph.D. degrees from the University of Tokyo, Tokyo, Japan, in 1977, 1979, and 1988, respectively, all in engineering. He is a Professor in the Department of Mathematical Engineering and Information Physics, Graduate School of Engineering, University of Tokyo. He has been employed by the Ministry of International Trade and Industry in the Industrial Products Research Laboratory. His research interests include optoelectronic computing, parallel processing, machine vision, sensor fusion, and robotics. MCARDLE et al.: RECONFIGURABLE OPTICAL INTERCONNECTIONS 837