Real Time Implementation of Medical Images Segmentation Using Xilinx System Generator

Transcription

1 International Review on Computers and Software (I.RE.CO.S.), Vol. 7, N. 6 ISSN November 2012 Real Time Implementation of Medical Images Segmentation Using Xilinx System Generator Fayçal Hamdaoui 1, Anis Ladgham 1, Anis Sakly 2, Abdellatif Mtibaa 1,2 Abstract This paper focuses on the contribution to the realization of the real time implementation of medical image segmentation. We start by the simple model of segmentation to success the implementation of a hardware system for medical images segmentation. This operation is applied on a medical image. We started by the conversation to grayscale space color. Then we made the threshold, and we close by morphological operations that summarized by erosion and closing. Our system was implemented on Virtex-V FPGA using Xilinx System Generator tool. To demonstrate the quality of our system we give some results of microscopic and brain MRI image after applied our system of segmentation. Copyright 2012 Praise Worthy Prize S.r.l. - All rights reserved. Keywords: Xilinx System Generator (X.S.G), FPGA, Thresholding, Morphological Operations, Implementation I. Introduction Thresholding segmentation is the most widely technique used to extract bottom objects of an image. The basic assumption of this technique is that objects can be distinguished by their gray level. Segmentation operation means giving each image pixel a label belonging to a given region. It plays an indispensable role in solving many problems in computer vision [1], [2], road sign detection, classification and recognition [3], [4], and medical imaging [5], [6]. Segmentation is the operation between processing and analysis of images. Therefore, this explains the huge number of methods and algorithms that have been developed in the recent years. Similarly, it has become a very important field of research. Also, in the field of medical imaging several studies have been addressed, the segmentation of MRI images [7], segmentation of sperms [8], and microscopic images [9]. The advantages of this technique are its ease of implementation and its effectiveness in real-time systems [11]. Even if the research community is very active on the topic subject of medical imaging, there no evaluation methodologies and tools that is developed yet in implementation of a real-time systems for segmentation. It is for this reason that our work focuses on the implementation of a real-time system for segmentation of medical images. Our method is based on the extraction of color information. We use System Generator tools to generate the bitstream code and upload it into the Virtex-V FPGA. Our method is evaluated and improved by experimental results. In section I we present the Xilinx System Generator (X.S.G) high level tool and we give reason for use. In section II we give an overview about our system for segmentation. In section III we explain the method used to achieve the conversion of RGB space grayscale space, we detail the thresholding step to eliminate insignificant colored pixels and we close our work by explaining the two morphological operations of erosion and closing which are intended to highlight areas of interest to make segmentation s result better. In Section IV, we give experimental results observed from the environment of simulation; MATLAB which was updated by the library of the System Generator tool. Section V offers a conclusion and future works. II. System Generator Setup II.1. Design Flow System Generator is a modeling tool that facilitates system-level FPGA design. It extends Simulink with many ways to provide a modeling environment that is well suited to the hardware design. The tool provides high-level abstractions that are automatically compiled into an FPGA. The tool also provides access to under lying resources of the FPGA through the low-level abstractions, allowing the construction of highly efficient FPGA designs [12]. System Generator maintains an entirely consistent level of abstraction with the blocksets SIMULINK traditional result in hardware implementations that are faithful, synthesizable and efficient. The implementation is effective through the instantiation of the existing blocks and provides a range of features from arithmetic to complex processing Manuscript received and revised October 2012, accepted November 2012 Copyright 2012 Praise Worthy Prize S.r.l. - All rights reserved 2861

2 functions. The design flow of this programming tool is shown in the following Fig. 1. III. System Overview As shown in Fig. 3 below, the input image is first converted to grayscale. Then passed by the thresholding step, we obtained a binary image in which the image was segmented clearly. After, we applied the closing step to the binary image to obtain an improved image. Fig. 1. Xilinx System Generator (X.S.G) design flow System Generator consists of a library called 'the Xilinx Blockset' in SIMULINK is used to create applications such as the application required in this project. II.2. Loading Data Into XSG Generally we manipulate the image as a 2- dimensional matrix in the software process. In this work XGS is a hardware tool. So, it manipulates images as an array with one dimension. Conversion from a 2- dimensional matrix to an array of one dimension [14] is necessary and it s done automatically. This array can be stored in an input ROM or we use a RAM to save images after treatment. The image conversion is shown in the Fig. 2 below. Fig. 2. Data acquisition A pixel with position x, y in the original image will take the position y 1 * n x in the output vector. Fig. 3. System Overview The setup for implementation consists of a compact flash memory to store a data of 512 x 512 images connected to a Xilinx ML507 FPGA, XC5VSXT platform. The segmentation system is applied in the Processing block on the input signal arriving from the memory block. The output signal is an image segmented and improved. In Fig. 4 below, we presented the completed architecture of our system as it is implemented on the XSG tool. IV. IV.1. Implementation Grayscale Conversion Segmentation operation allows the passage of a representation in light intensity (gray levels) to a symbolic representation (pixels belonging to different classes of area) [13]. The RGB color space is the most basic level, it consists of three components very dependent as given in the figure below. This color space is very sensitive to lighting changes. In against part, due to simplicity of calculation and representation, many researchers uses RGB color space in the step of thresholding. Kamada et al. [16] uses a color ratio between the intensity of specific components RGB color and the sum of the intensity of RGB. This report is used to detect bright colors in the image. This model is made based on the mathematical equations linking YCrCb space to RGB space. In Eq. (1) we cited only the Y component that will be used in our work: Y R G R (1) 2862

3 Fig. 4. Block Diagram of the complete architecture The R, G and B are classified into three registers. Each register contains values refer to the size of the image that is 512x512 pixels. This data is then sent to a FIFO (First in, First out) to organize the processing of these data. The number of multiplier used is three and the number of adder is four. Data processing is done in parallel to give more gain in terms of computation time, latency is used to make up the time lag between two successive stages of computation. Fig. 5 shows the model performed on SYSTEM GENERATOR. IV.2. Thresholding Thresholding is a processing operation that changes the digital representation of an image [15]. This symbolic representation is to structure the information of this picture. Thresholding is a technique for segmentation of grey scaled images based on grayscale value. This operation transforms the original image into binary image. Each pixel whether it is outside a specified range will be illuminated. The histogram will be processed depending user s choice of threshold values. A Threshold image t(x,y) may be determinate by a test function is shown as follow: t x 0 if f x T 1 otherwise Fig. 5. Block architecture: RGB to Grayscale Each color component R, G and B is set to eight bits. This defines a number of colors supported by 256 pallets. After conversion, we use only one component Y. Likewise, it is defined on eight bits. Fig. 5 describes exactly what has been already explained. We used three multipliers and two adders. Accumulators are a simple registers used to store pixels of all three colors components. We used only one accumulator. where T is the threshold value. To achieve this thresholding operation and implement it into FPGA, we realize the assembly given in the following Fig. 6. Thresholding is applied to achieve the detection of regions of interest: ROI (Region of Interest) [10], [17]. Since the Y component stored in a register of the FPGA in the conversion process to the image gray levels. The processor reads the pixel values and compares them to a threshold. The pixels that have value above this threshold are set to 1, while those who are below the threshold value is 0. Then, the pixel values are stored in a new register. 2863

4 a FIFO. Later we had done pixel by pixel by keeping each one in a register, then another FIFO. So we need two FIFO registers per operation and seven in total. Fig. 8 illustrates the idea detailed the windowing architecture 3x3. Fig. 6. Block architecture of thresholding IV.3. Morphological Operations Morphological operations concern image preprocessing step whose role is to improve the image quality by eliminating noise. Topically the image can be subject to two preprocessing operations: closing and opening. In this work, and in order to eliminate the border pixels in the ROI, we applied closing operation to the binary image. First, the image is expanded to remove the pixels boundaries and then eroded to recover the effects of expansion on ROI. In VHDL, the morphological operations are based on windowing systems mobile. As already explained in the previous chapter, the close operation is based on a dilation followed by erosion. Dilation is an operation that applies on matrices. For this, we must first think about adapting the information stored in the registers after thresholding. This adaptation is to convert the pixels arriving to FIFO in disordered data into ordered data in a matrix. First time and for more explain, we give in the figure the general architecture of closing (Fig. 7). Afterward, it goes to explain the two blocks one by one. The idea is simple, here we take an example of a matrix of size 3x3 pixels. Just take the first three pixels reached by putting it in three successive registers then in Fig. 7. Block architecture of closing To succeed the closing stage, we use this type of window with a window of size 3x3. In this way, we can easily exploit pixels knowing their positions in the rows and columns on window s matrix (also called mask). A 3x3 window size is quite small for easily allow its implementation on the target FPGA. It is also considered suitable for the most commonly used formats of images. With larger window sizes, we need more and scales FIFO. This will increase the use of FPGAs resources. To perform the closing operation, we will use the generating windows architecture explained before. We begin, firstly by explaining the architecture of dilation. The idea is to use a mask of size 3x3 pixels (window). This mask is placed on a pixel, then we swing it on pixel by pixel to finaly testing the entire image. The pixel under test U t is out through a multiplexer which is normally in the block f(2, 2) of the matrix window. Likewise, via another multiplexer, it brings the other pixels. Fig. 8. Block architecture of windowing generation 2864

5 Fayçal Hamdaoui, Anis Ladgham, Anis Sakly, Abdellatif Mtibaa If the central pixel U t is a background, thus looking the other pixels of the first multiplexer. Indeed, if one of the other pixel is an object pixel, then the pixel is converted into a pixel object U t. If not, we keep it as a background. Now, if U t is an object pixel we bring it out directly. Fig. 9. Block architecture of dilation The pixels gets out of the dilation stage will be placed in a register, one by one. Then they will be used in the erosion stage. For this, we will now proceed to introduce the architecture used to implement erosion. Indeed, architecture is the same. The only change is given in the implementation of the comparator structure. Firstly, we test the pixel U t. If it is a part of background, it must be done out directly without change. If the pixel is an object, so it will depend on the neighbor pixels, one by one. If there is at least one pixel background, so the pixel value U t would type background too. Is given in Fig. 10 the architecture model of erosion and it clear that s similar to dilation. V. When acquisition of the image from the compact flash to FPGA registers was successfully done, image will be converted from the RGB space to the grayscale level. Then, the segmentation will be processed and to end with the closing operation. This combination provides a complete architecture shown in Fig. 11. It is the RTL model of this architecture generated by System Generator to be synthesized and implemented into the FPGA. The output images for input images of resolution 512 x 512 discussed above are shown below. In Figs. 12 below we give the experimental results of a microscopic image and then in Figs. 13 we give the experimental results of a brain MRI image. The architecture has been implemented on a Virtex 5 ML507 target, XC5VSXT platform. The most important parameter in the use of resources is the number of flip flops used in FPGA. Unused Flip Flops shows the availability of the FPGA logic. The second important parameter in the use of resources of the FPGA is the use of ressources memory. The memories requirements of small size can be filled using the external on-chip RAM. In this Fig. 14, we give the resource utilization of the hardware architecture achieved. In this architecture, only 2% of the FPGA logic resources (Flip Flop) and 3% of buffers (RAM memory) are used. Experimental Results The hardware system of segmentation of medical images consists on the association of all blocks presented above. Fig. 10. Block architecture of erosion Fig. 11. Block architecture of erosion Copyright 2012 Praise Worthy Prize S.r.l. - All rights reserved International Review on Computers and Software, Vol. 7, N

6 (a) (b) (c) Figs. 12. Experimental results, (a) original acquisition: microscopic image, (b) segmentation step, (c) segmentation after closing (a) (b) (c) Figs. 13. Experimental results, (a) original acquisition: brain MRI image, (b) segmentation step, (c) segmentation after closing Fig. 14. Resource estimation of the hardware architecture of segmentation system VI. Conclusion In this paper, segmentation of medical images was implemented on FPGA for an input image of resolution 512x512. The design was tested for an microscopic and brain images input. The estimation use of resource FPGA demonstrates that this architecture can be implemented in smaller and less expensive FPGAs. The implementation can be extended to color and video images. References [1] H. Wang, and D. Suter (2003f). "Robust Adaptive-Scale Parametric Model Estimation for Computer Vision." submitted to IEEE Trans. Pattern Analysis and Machine Intelligence (in revised form); [2] H. Wang, and D. Suter (2004). Robust Fitting by Adaptive-Scale Residual Consensus. 8th European Conference on Computer Vision (ECCV04), Prague, Czech Republic; [3] A. Soetedjo, K. Yamada.; Traffic sign classification using ring 2866

7 partitioned method, IEICE, Trans Fundam E 88 A (9) : , 2005; [4] H. Fleyeh, S. Gilani, M. Dougherty.; Road sign detection and recognition using Fuzzy ARTMAP: a case study swedish speedlimit signs, In: Proceedings of artificial intelligence and soft computing, 2006; [5] H.S.Prasantha, Shashidhara.H.L, K.N.B.Murthy, Madhavi Lata.G, Medical Image Segmentation, (IJCSE) International Journal on Computer Science and Engineering, Vol. 02, No. 04, 2010, ; [6] Bello, M., Ju, T., Carson, J., Warren, J., Chiu, W., Kakadiaris, I.A.: Learning-based segmentation framework for tissue images containing gene expression data. IEEE Transactions on Medical Imaging 26(5) (2007) [7] K.Somasundaram, P.alavathi, A hybrid method for automatic skull striping of magnetic resonance images (MRI) of human head scans, 2010 Second International conference on Computing, Communication and Networking Technologies (2010). [8] F. N. Rahatabad., M. H. Moradi, and V. R. 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Sánchez G., Ricardo Alvarez G., Sully Sánchez G., Architecture for filtering images using Xilinx System Generator; International Journal of Mathematical Models and Methods in Applied Sciences, Issue 4, Volume 1, 2007, pp [15] R. Dhir, C. Singh. (2006) Recognition of Bilingual Segmented Characters (Gurmukhi and Roman), International Review on Computers and Software (IRECOS), Vol. 01, No. 02, pp ; [16] H. Kamada, S. Naoi, T. Gotoh, A compact navigation system using image processing and fuzzy control, in Proc. Southeastcon, New Orleans, LA, vol. 1, pp , Apr. 1990; [17] A. Hechri, F. Hamdaoui, A. Ladgham,. A. Mtibaa, (2011). Using Fuzzy Logic Path Tracking for an Autonomous Robot, International Review of Automatic Control (IRECO); 4 (1), Anis Ladgham did his schooling in the national school of engineering of monastir (ENIM). In 2007, he graduated with a diploma after two years of preparatory classes leading to highly engineering schools. In 2010, he graduated with a national diploma of engineering in Electrical engineering from ENIM. In 2011, he he graduated with a Master diploma from ENIM, Tunisia. He is currently pursuing his thesis in the Electronics and Microelectronics Laboratory (EµE) at the Faculty of Sciences of Monastir with the Reconfigurable Circuit System team at ENIM. His research interests include medical image processing ans embedded system. ladghamanis02@gmail.com Anis Sakly was born in Tunisia in He received the Electrical Engineering diploma in 1994 from National Engineering School of Monastir (ENIM), then the PhD degree in Electrical Engineering in 2005 from National Engineering School of Tunis (ENIT). Since 2012 he has been a Professor at ENIM. His research interests are in analysis, synthesis and implementation of intelligent control systems, particularly soft computing-based control approaches. sakly_anis@yahoo.fr Abdellatif Mtibaa is currently a Professor of Micro-Electronics and Hardware Design at the Electrical Department, National School of Engineering of Monastir and Head of Circuits Systems Reconfigurable-ENIM-Group at Electronic and Microelectronic Laboratory. He holds a Diploma in Electrical Engineering in 1985 and received his PhD in Electrical Engineering in His current research interests include system on programmable chip, high level synthesis, rapid prototyping and reconfigurable architecture for real-time multimedia applications. He has authored/co-authored over 100 papers in international journals and conferences. He served on the technical programme committees for several international conferences. He also served as a Co-Organiser of several international conferences. abdellatif.mtibaa@enim.rnu.tn Authors information 1 Laboratory EµE, Faculty of Sciences of Monastir, University of Monastir, Tunisia. 2 Department of electrical engineering, National Engineering School of Monastir, University of Monastir, Tunisia. Fayçal Hamdaoui received the Electrical Engineering degree (specialty Industrial Computers Science) from the National School of Engineering of Monastir, University of Monastir, Tunisia in In July 2011, he graduated with a Master diploma from ENIM, Tunisia. Since November 2011, he has been a PhD. researcher in the Electronics and Microelectronics Laboratory (EµE) at the Faculty of Sciences of Monastir with the Reconfigurable Circuit System team at ENIM. His research interests are medical image processing, embedded system and soft computing. faycel_hamdaoui@yahoo.fr 2867