Integration of the Omega-3 Readout Chip into a High Energy. Physics Experimental Data Acquisition System. H. Beker, E. Chesi, P.

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1 Integration of the Omega-3 Readout Chip into a High Energy Physics Experimental Data Acquisition System H. Beker, E. Chesi, P. Martinengo; CERN May 21, 1996 Abstract The Omega-3 readout chip is presented in detail elsewhere in the same proceedings [1]. We here describe the integration of the chip into present and future experiments describing both hardware and software aspects. We cover preliminary tests in the laboratory and on the beam. The WA97 experiment has already used a pixel telescope in the past [4] and intends to upgrade to the Omega- 3 chip. A newly proposed experiment at CERN studying strangeness production in heavy ion collisions also plans to use a similar telescope. Finally we give an outlook on the ongoing developments in the pixel readout architecture in the context of ALICE, the heavy ion experiment at the LHC collider. 1 Front End Hardware The front end hardware as well as the software are the continuation of previous developments for the present WA97 silicon pixel telescope. Fig 1 shows the schematics of the pixel frontend electronics. 1.1 The Detector Multi-layer Board Six Omega-3 chips are bump bonded [2] to the same high resistivity silicon detector covering a total area of about 6x50 mm 2. After a full functional test of the readout chips before cutting the wafer and of the ladders on the probe station, four of the ladders are mounted on the same ceramics support forming a physical plane covering slightly more than 50% of the intended coverage of 50x50 mm 2. Two such physical planes, made up of a total of 8 ladders and 48 readout chips mounted face to face, cover the whole acceptance. The ladders are glued to the 250 m multi-layer ceramics support and the supply, bias, control and data lines are wire bonded to the Omega-3 chip. Each chip has 16 bidirectional data lines for readout and programming which are paired to a single 32 wide data bus. 12 chip pairs are multiplexed on this bus corresponding to a total of 1524 pixel rows. In order to reduce the radiation length of the detector we are studying the use of aluminium supports with deposited polyamid layers. They can be thinned to less then 100 m after layer deposition forming a exible and hence non-fragile support. A exible vetronite foil of about 20 cm long is glued to the ceramics and the traces are wire bonded to the ceramics. 1.2 The Intermediate Board This card drives the long distance dierential TTL bus (about 30 m) to the counting room, makes all chip functions available to the 1

2 Detector Ceramics 5 cm Kapton Detector Omega 3 Ceramics 5 cm Side view This card makes all chip functions available to any commercial processor. It contains the digital to analogue converters for the analogue parameters, the control logic for programming the digital parameters and a buer memory for the reception of the event data. It can perform zero-suppression using its own mask memory. It can also mask stuck data bits which cannot be masked by the Omega-3 chip. The data format presented to the processor contains two 32 bit words, i.e. 8 bytes for a single hit pixel. The rst data words contain the bit pattern of the 32 columns of a given row of a chip pair, the second the combined row and chip pair number. Hits occurring in the same row share the same data word pair. The card supplies also the interface to the experimental trigger system to which it communicates over front panel LEMO inputs and outputs. Intermediate board ~ 20 cm Twisted pair ribbon cable ~ 30 m readout and control card Figure 1: Detector and front end electronics mounting schematics card (analogue parameters: gross and ne delay, threshold, compensation and amplication bias, digital parameters: On-chip mask, test pulse mask, ne delay adjust). It contains its own sequencer which performs the chip pair multiplexing and optionally can perform zero suppression of the data sent to the card. The sequencer runs at a speed of 5 MHz allowing the complete readout of an event in about 300 s. 1.3 The Card 2 Software Integration 2.1 Laboratory Test and Calibration Software A program giving easy access to all the chip functions and allowing to perform threshold and delay calibration is provided under OS9. The program is written in the C language without using of operating system dependent libraries and is easily portable to any other platform. An adapted version of this program has been used in the wafer and ladder tests on the probe station. 2.2 Test Beam Measurements at the CERN SPS Detectors equipped with the Omega-3 chip were successfully tested at the CERN SPS at the beginning of April 96. Other than the pixel detector, a silicon microstrip telescope with strips of down to 10 m pitch was included in the set-up to serve as a reference detector both for spatial resolution and eciency. Both detectors were read out by an OS9 CPU running the ALICE test beam Data Acquisition System [3]. In this system the data are shipped to a general purpose UNIX workstation over the network on the y. The workstation stores the data on disk or on tape and permits real-time online monitoring. A number of packages are available under 2

distinct pixel readout systems and a number of other detectors. It then transfers the data via an FDDI point to point link to an Alpha workstation.

3 distinct pixel readout systems and a number of other detectors. It then transfers the data via an FDDI point to point link to an Alpha workstation. Data are recorded on tape and a subsample of the events is provided to user written monitoring and display tasks. Figure 2: Beam Prole in Pixel Event Display UNIX (and not under OS9) dealing with graphics [5] and statistics [6] which allows on-line analysis and visualisation of the data, as indicated in g. 2. We plan to use the recently available processors running UNIX allowing us to perform high level data treatment already in the front end crate. 2.3 Integration into WA97 In WA97, we are confronted with an existing complex high performance data acquisition system based on the bus which provides a de- ned interface for including new detectors. We will use two crates for the total of 14 readout cards covering 7 logical planes. During the SPS particle burst we store the data from the readout cards inside the local CPU memory. Outside the burst, and hence without causing dead time, they are read by an external event builder which accesses the front-end crates through a transparent interconnect. It sequentialises the sub-events coming from the two 2.4 Integration in to a Future Fixed Target Heavy Ion Experiment WA97 is scheduled to take data for the last time in 1996 due to the closure of the CERN SPS West Area. The collaboration proposes a continuation and upgrade of the experiment in the CERN SPS North Area, starting in We also plan a substantial upgrade of the readout and data acquisition system. Not only the experimental goals of this experiment will be linked very strongly to ALICE [7], but also the Data Acquisition System will serve as a milestone in the development of ALICE DAQ system. It will resemble very much the one of the AL- ICE test beams, insuring code re-usability. Each parallel readout systems and hence also the two pixel readout crates will be linked directly to the recording machines through a high speed bre connection using a network protocol. The readout will be parallelised as well as the event building. The parallel readout systems are connected to the parallel event building and recording machine through a switched network. We are condent to achieve readout times which are almost an order of magnitude higher than the ones in WA97. 3 Development for the Pixel Readout in ALICE The pixel detector is an integral part of the AL- ICE inner tracking system, the mechanical layout is outlined in [7]. 3

4 Detector Data Link Front end bus interface Readout state machine FIFO FULL Multi event FIFO state machine To trigger Hard Busy Trigger Sync Trigger ReadOut Soft Busy Abort Figure 3: Multi event buers in the Pixel Readout Card Active In AM0..AM5,A1.A31, AS DTACK Address decoding Active Bus FIFO RS Filling machine first card C-BLT transfer DO..D31 Active out... Active In AM,A1.A31,AS,... AM0..AM5,A1.A31, AS Address decoding Active DTACK FIFO RS Filling machine last card Standard master DO..D31 D0..D31 DTACK, BERR BERR Figure 4: Chained Block Transfer in Active out Reference [8] describes the necessary improvements of the readout chip itself, here we outline the improvements on the readout electronics. We have to signicantly reduce the dimensions of all components mounted on the detector. The intermediate card which is presently built in discrete and reprogrammable electronics will have to be integrated in a custom silicon design. The interconnection between the counting room and the front end electronics will be performed serially over a pair of optical bre rather than over the twisted pair copper cables. This implies that all DACs for analogue parameters have to be generated on the intermediate card or chip or directly integrated into a future version of the pixel readout chip. The readout card will have to be able to store multiple events in its readout FIFO in order to reduce the dead time. This allows to re-enable the trigger already when an event has been transferred into the FIFO before the data have been acquired by a processor. This requires a tighter interface of the readout card with the trigger system, as shown in Fig 3. This will be implemented in connection with the newly proposed extension of the chained block transfer [9] sketched in Fig 4. In this mode all readout cards appear like a single FIFO to the processor responding to a single address. When a card no longer has data it passes a token to the neighbouring one on a special line instead of producing a bus error. Only one card holds the token at any given time avoiding conicts. If the last card passes back the token to the rst one for the next event, the sequentialisation of multiple events can be performed at up to 80 MBytes/s with presently commercially available processors. 4

5 The total readout time of one event has to be kept below 200 s in order to meet the ALICE requirements. A single 16 bit pixel number will be produced directly by the sparse data scanner on the readout chip similar to the one proposed in [10]; a further 50% data reduction performed in software [11] will reduce the amount of data to be recorded on tape by a factor of 8 compared to the present Omega-3 data format. 4 Conclusions In RD19 we are providing a versatile turn-key system including both hardware and software for the integration of the Omega-3 chip into high energy physics experiments or other applications. The versatility was insured by adopting widespread standards such as and UNIX. We have also shown the present road map of the readout and data acquisition developments for a pixel detector through a number of present and future heavy ion experiments up to ALICE, scheduled for data taking in References [1] Omega-3/LHC1 Pixel Detector M. Campbell, P. Middelkamp same proceedings. [2] Bump Bonding in GEC-Marconi, A. Needham, same proceedings. al, Nucl. Instrum. Methods Phys. Res., A : 360 (1-2)(1995) [5] The Tcl and the Tk Toolkit, John K. Ousterhout, Addison-Wesley Professional Computing Series, 1993, ISBN X [6] Physics Analysis Workstation - PAW, manual available from the CERN CN/ASD Group. [7] Technical Proposal of ALICE, A Large Ion Collider Experiment, CERN/LHCC 95-71, LHCC/P3, 15 December [8] Pixel Detector System for the ALICE Heavy-Ion Experiment at LHC, F.Antinori, same proceedings [9] Recommended Practices of the use of the bus in Physics applications Draft 0.4, ESONE CERN bus Steering Commitee, availble from C. Parkman, CERN-ECP and ESS/VSC/Recommended P/ [10] A sparse data scan circuit for pixel detector readout, Jaeger, J J et al., IEEE Trans. Nucl. Sci. : 41 (1994) [11] Data compression on zero suppressed High Energy Physics Data, H. Beker, M. Schindler, AL- ICE Technical note 42. Available also under [3] The ALICE Test Beam Data Acquisition System, documentation and software available on the Web Beam-DAQ [4] Experience with a 30 cm 2 silicon pixel plane in CERN experiment WA97, Antinori F. et. 5

Firmware development and testing of the ATLAS IBL Read-Out Driver card

Firmware development and testing of the ATLAS IBL Read-Out Driver card *a on behalf of the ATLAS Collaboration a University of Washington, Department of Electrical Engineering, Seattle, WA 98195, U.S.A.