datasheet PRELIMINARY SPECIFICATION 1/3.2" CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology OV8810

Transcription

1 datasheet PRELIMINARY SPECIFICATION 1/3.2" CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology OV8810

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3 i 00Copyright 2009 OmniVision Technologies, Inc. All rights reserved. This document is provided as is with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. OmniVision Technologies, Inc. and all its affiliates disclaim all liability, including liability for infringement of any proprietary rights, relating to the use of information in this document. No license, expressed or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. The information contained in this document is considered proprietary to OmniVision Technologies, Inc. and all its affiliates. This information may be distributed to individuals or organizations authorized by OmniVision Technologies, Inc. to receive said information. Individuals and/or organizations are not allowed to re-distribute said information. Trademark Information OmniVision and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. OmniBSI is a trademark of OmniVision Technologies, Inc. All other trademarks used herein are the property of their respective owners. color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology datasheet (CSP3) PRELIMINARY SPECIFICATION version 1.42 june 2009 To learn more about OmniVision Technologies, visit OmniVision Technologies is publicly traded on NASDAQ under the symbol OVTI PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

4 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

5 iii 00applications ordering information cellular phones digital cameras 00features OmniBSI technology with high sensitivity, low noise, low dark current and low crosstalk flexible frame exposure control mode flexible strobe output to control flash programmable controls: gain, exposure, frame rate, image size, horizontal mirror, vertical flip, cropping, windowing, and panning automatic image control functions: automatic exposure (AEC), automatic gain control (AGC), automatic white balance (AWB), automatic 50/60 Hz luminance detection, and automatic black level calibration (ABLC) image quality controls: defect pixel correction and lens shading correction two-wire serial bus control 00key specifications active array size: 3264 x 2448 power supply: core: 1.4 ~ 1.6V (1.5V typical) analog: 2.6 ~ 3.1V (2.8V typical) I/O: 1.7 ~ 3.1V (1.8V/2.8V typical) power requirements: active: 200 ma standby: 800 µa power down: 150 µa temperature range: operating: -30 C to 70 C (see table 8-2) OV08810-A67A (color, lead-free) 67-pin CSP3 MIPI serial output interface digital video port (DVP) parallel output interface support for second camera chip-sharing MIPI interface support for output formats: 8-/10-/12-bit RAW RGB support for image sizes: 8 10 fps, 30 fps, 60 fps, and 60 fps support for black sun cancellation embedded one-time programmable (OTP) memory on-chip phase lock loop (PLL) built-in 1.5V regulator for core frame exposure mode for still image (with mechanical shutter) stable image: 0 C to 50 C (see table 8-2) output formats: 8-/10-/12-bit RAW RGB lens size: 1/3.2" lens chief ray angle: 27 non-linear (see figure 10-2) input clock frequency: 6 ~ 27MHz S/N ratio: 35 db dynamic range: 67 db standard image transfer rate: 8 Mpixel (3264x2448): 10 fps 1080p: 30 fps 720p: 60 fps VGA: 60 fps QVGA: 120 fps sensitivity: 650 mv/(lux-sec) shutter: rolling shutter scan mode: progressive maximum exposure interval: 2476 x T line pixel size: 1.4 µm x 1.4 µm well capacity: 4.5 Ke - dark current: 7.6 mv/s at 60ºC fixed pattern noise (FPN): < 1% of V PEAK-TO-PEAK image area: 4614 µm x 3506 µm package dimensions: 6235 µm x 6535 µm PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

6 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

7 v 00table of contents 1 signal descriptions system level description overview architecture format and frame rate system clock control SCCB interface slave address message type read/write operations multi-byte registers MIPI PHY power up sequence power up with internal DVDD and I2C access during power up period power up with internal DVDD and no I2C access during power up period power up with external DVDD source and I2C access during power up period power up with external DVDD and no I2C access during power up period power on reset (POR) power down (PWDN) block level description pixel array structure analog amplifier bit A/D converters VCM driver output current control mode image sensor core digital functions mirror and flip image cropping and windowing test pattern /60 Hz detection AEC and AGC algorithms outside control zone inside control zone PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

8 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology average luminance (YAVG) AEC/AGC steps strobe flash control strobe in rolling shutter mode strobe pulse xenon flash control LED1 & 2 mode LED 3 mode strobe in frame exposure mode frame exposure (FREX mode) through YFREX input pin (mode 1) through register control (mode 2) strobe output in frame exposure compensation for mechanical shutter latency one-time programmable (OTP) memory image sensor processor digital functions BLC and EvenOdd LENC digital gain AWB WBC VarioPixel frame average image sensor output interface digital functions digital video port (DVP) overview HSYNC mode three modes of VSYNC output DVP control registers mobile industry processor interface (MIPI) normal high speed mode HOST single write registers sequenced through ESCAPE mode HOST sequence write registers sequenced through ESCAPE mode HOST sequence read registers sequenced through ESCAPE mode MIPI control registers register tables 7-1 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

9 rev-vii 8 operating specifications absolute maximum ratings functional temperature DC characteristics AC characteristics mechanical specifications physical specifications IR reflow specifications optical specifications sensor array center lens chief ray angle (CRA) spectrum response curve PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

10 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

11 ix 00list of figures figure 1-1 pin diagram 1-4 figure 2-1 OV8810 block diagram 2-2 figure 2-2 system clock control diagram 2-4 figure 2-3 example of MIPI with two data lanes and RAW12 data 2-5 figure 2-4 example of MIPI with two data lanes and RAW10 data 2-5 figure 2-5 SCCB message format 2-6 figure 2-6 power up timing with internal DVDD and I2C access during power up period 2-7 figure 2-7 power up timing with internal DVDD and no I2C access during power up period 2-8 figure 2-8 power up timing with external DVDD source and I2C access during power up period 2-9 figure 2-9 power up timing with external DVDD source and I2C access during power up period 2-10 figure 2-10 OV8810 reference schematic 2-11 figure 3-1 sensor array region color filter layout 3-1 figure 3-2 pixel readout: binning versus skip 3-2 figure 3-3 VCM block diagram 3-2 figure 3-4 1/4 to 3/4 scale settling time (directly jump mode, VDD = 3.0V) 3-5 figure 3-5 sink current vs. code (VDD = 3.0V, reg 0x30A5 = 0x05, VCM resistance = 23ohms) 3-6 figure 4-1 mirror and flip samples 4-1 figure 4-2 image windowing and cropping 4-2 figure 4-3 color bar 4-4 figure 4-4 desired convergence 4-6 figure 4-5 xenon flash mode 4-12 figure 4-6 LED 1 & 2 mode - one pulse output 4-13 figure 4-7 LED 1 & 2 mode - multiple pulse output 4-14 figure 4-8 LED 3 mode 4-14 figure 4-9 FREX modes 4-16 figure 4-10 FREX mode figure 4-11 FREX mode figure 6-1 DVP timing diagram 6-1 figure 6-2 VSYNC output timing 6-2 figure 8-1 SCCB interface timing 8-5 figure 8-2 line/pixel output timing 8-6 figure 8-3 frame timing PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

12 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology figure 9-1 package specifications 9-1 figure 9-2 IR reflow ramp rate requirements 9-3 figure 10-1 sensor array center 10-1 figure 10-2 chief ray angle (CRA) 10-2 figure 10-3 spectrum response curve 10-4 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

13 xi 00list of tables table 1-1 signal descriptions 1-1 table 2-1 format and frame rate 2-3 table 3-1 VCM driver control 3-3 table 3-2 VCM control registers 3-4 table 3-3 single step mode 3-4 table 3-4 multi-code step mode 3-5 table 4-1 mirror and flip function control 4-1 table 4-2 windowing and cropping control registers 4-2 table 4-3 test pattern selection control 4-4 table 4-4 AEC/AGC control registers 4-5 table 4-5 AEC control functions 4-7 table 4-6 AGC control functions 4-8 table 4-7 strobe flash control functions 4-11 table 4-8 flashlight modes 4-12 table 4-9 strobe flash control functions in frame exposure mode 4-15 table 4-10 frame exposure control functions 4-19 table 4-11 OTP memory control functions 4-20 table 5-1 BLC control registers 5-1 table 5-2 LENC control registers 5-3 table 5-3 digital gain control registers 5-4 table 5-4 AWB control registers 5-4 table 5-5 WBC control registers 5-6 table 5-6 VarioPixel control registers 5-8 table 5-7 frame average control registers 5-10 table 6-1 DVP timing 6-2 table 6-2 DVP VSYNC settings 6-3 table 6-3 DVP control registers 6-3 table 6-4 MIPI control registers 6-7 table 7-1 system control registers 7-1 table 7-2 ISP control registers 7-14 table 7-3 DVP control registers 7-22 table 7-4 MIPI control registers PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

14 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 8-1 absolute maximum ratings 8-1 table 8-2 functional temperature 8-1 table 8-3 DC characteristics (-30 C < TA < 70 C) 8-2 table 8-4 AC characteristics (TA = 25 C, VDD-A = 2.8V) 8-4 table 8-5 timing characteristics 8-4 table 8-6 SCCB interface timing specifications 8-5 table 8-7 pixel timing specifications 8-6 table 8-8 control parameter for standard resolution output 8-7 table 8-9 VCM characteristics 8-8 table 9-1 package dimensions 9-1 table 9-2 reflow conditions 9-3 table 10-1 CRA versus image height plot 10-2 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

15 1-1 1 signal descriptions table 1-1 lists the signal descriptions and their corresponding pin numbers for the OV8810 image sensor. The package information is shown in section 9. table 1-1 signal descriptions (sheet 1 of 3) pin number signal name pin type description A1 YY8 I/O bit[8] of parallel output port / input A2 YY7 I/O bit[7] of parallel output port / input A3 YVSYNC I/O vertical synchronization (VSYNC) output A4 SGND ground pixel array ground A5 YRESET_B input hardware reset, active low A6 VREFN reference A7 SVDD power pixel array power (2.6~3.1V) A8 AGND ground analog ground A9 NC no connect B1 DOGND ground I/O circuit ground B2 DOVDD power I/O circuit power (1.7~3.1V) B3 YFREX I/O frame exposure control B4 SVDD power pixel array power (2.6~3.1V) internal reference (requires a 0.1 µf capacitor between VREFN and AGND) B5 YPWDN input power down (hardware standby), active high B6 VREFH reference B7 SGND ground pixel array ground B8 AVDD power analog power (2.6~3.1V) internal reference (requires a 0.1 µf capacitor between VREFH and AGND) B9 YHREF I/O horizontal reference (data valid) output C1 YY6 I/O bit[6] of parallel output port / input C2 YY5 I/O bit[5] of parallel output port / input C3 NC no connect C4 NC no connect C5 NC no connect C6 NC no connect PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

16 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 1-1 signal descriptions (sheet 2 of 3) pin signal pin number name type description C7 NC no connect C8 YSCL input SCCB clock C9 YSDA I/O SCCB data D1 YY4 I/O bit[4] of parallel output port / input D2 YY3 I/O bit[3] of parallel output port / input D3 NC no connect D7 NC no connect D8 NC no connect D9 YSTROBE I/O strobe output control E1 YY2 I/O bit[2] of parallel output port / input E2 YY1 I/O bit[1] of parallel output port / input E8 AVDD power analog power (2.6~3.1V) E9 YXVCLK input system clock input F1 YY[0] I/O bit[0] of parallel output port / input F2 YPCLK I/O pixel clock output input F3 NC no connect F7 YY9 I/O bit[9] of parallel port output / input F8 YY11 I/O bit[11] of parallel port output / input F9 AGND ground analog ground G1 DOVDD power I/O circuit power (1.7~3.1V) G2 DOGND ground I/O circuit ground G3 NC no connect G4 NC no connect G5 NC no connect G6 MDN2 I/O MIPI data lane 2 negative output G7 MDP2 I/O MIPI data lane 2 positive output G8 DOGND ground I/O circuit ground G9 YY10 I/O bit[10] of parallel port output / input H1 DGND ground digital core logic ground proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

17 1-3 table 1-1 signal descriptions (sheet 3 of 3) pin signal pin number name type H2 DVDD power H3 NC no connect H4 MCN I/O MIPI clock negative output H5 MCP I/O MIPI clock positive output H6 EGND ground MIPI ground digital core logic power reference (external supply: 1.35~1.65V, 1.5V typical) (requires a 0.1 µf capacitor between DVDD and DGND) H8 PVDD power PLL circuit power (2.6~3.1V) H9 DOVDD power I/O circuit power (1.7~3.1V) I1 VCMISNK I/O VCM current sink input I2 VCMGND ground VCM ground I3 MDN1 I/O MIPI data lane 1 negative output I4 MDP1 I/O MIPI data lane 1 positive output I6 EVDD power description I8 EGND ground MIPI ground I9 NC no connect MIPI power (1.5V, should connect to DVDD) (requires a 0.1 µf capacitor between EVDD and DGND) PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

18 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology figure 1-1 pin diagram A1 YY[8] B1 A2 A3 OV8810 top view A4 A5 YY[7] YVSYNC SGND YRESET_B VREFN SVDD AGND B2 B3 B4 DOGND DOVDD YFREX SVDD YPWDN VREFH SGND AVDD YHREF C1 YY[6] D1 YY[4] E1 YY[2] F1 YY[0] G1 C2 YY[5] D2 YY[3] E2 YY[1] F2 YPCLK DOVDD DOGND H1 DGND I1 G2 H2 DVDD I2 C3 NC D3 NC F3 NC G3 NC H3 NC I3 C4 NC G4 NC H4 MCN I4 VCMISNK VCMGND MDN1 MDP1 B5 C5 NC G5 NC H5 MCP A6 B6 C6 NC G6 MDN2 H6 EGND I6 EVDD A7 B7 C7 NC D7 NC F7 YY[9] G7 MDP2 A8 B8 C8 YSCL D8 NC E8 A9 NC B9 C9 YSDA D9 YSTROBE E9 AVDD YXVCLK F8 YY[11] G8 F9 AGND G9 DOGND YY[10] H8 H9 PVDD DOVDD I8 EGND I9 NC 8810_CSP_DS_1_1 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

19 2-1 2 system level description 2.1 overview The OV8810 (color) image sensor is a low-voltage, high-performance 1/3.2-inch 8 megapixel CMOS image sensor that provides the full functionality of a single chip 8 megapixel (3264x2448) camera using OmniBSI technology in a small footprint package. It provides full-frame, sub-sampled, windowed 8-bit/10-/12-bit images in various formats via the control of the Serial Camera Control Bus (SCCB) interface or MIPI interface. The OV8810 has an image array capable of operating at up to 10 frames per second (fps) in full resolution with complete user control over image quality, formatting and output data transfer. All required image processing functions, including exposure control, white balance and defective pixel canceling, etc., are programmable through the SCCB interface. In addition, Omnivision image sensors use proprietary sensor technology to improve image quality by reducing or eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to produce a clean, fully stable, color image. For storage purposes, the OV8810 includes a one-time programmable (OTP) memory. The OV8810 has a two-lane MIPI interface and a traditional parallel digital video port. The sensor can also be used to communicate to an external secondary camera (digital video port) while providing continued output through the MIPI interface. 2.2 architecture The OV8810 sensor core generates stream pixel data at a constant frame rate indicated by YHREF and YVSYNC. The maximum pixel rate is 96 megapixels per second. figure 2-1 shows the functional block diagram of the OV8810 image sensor. The timing generator outputs signals to access the rows of the image array, precharging and sampling the rows of array in series. In the time between pre-charging and sampling a row, the charge in the pixels decreases with the time exposed to the incident light. This is known as exposure time. The exposure time is controlled by adjusting the time interval between precharging and sampling. After the pixel s data in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data with corresponding gain. The ADC then outputs 12-bit data for each pixel in the array PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

20 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology figure 2-1 OV8810 block diagram row select column sample/hold image array 50/60Hz auto detection PLL YXVCLK image sensor core B/R channel AMP AMP gain control YPWDN Gb/Gr channel black level calibration timing generator and system control logic YRESET_B YFREX 12-bit ADC 12-bit ADC YSTROBE YVSYNC B/R Gb/Gr YHREF YPCLK OV8810 image sensor processor image output interface digital gain 12-bit RAW external sensor input DSP control register bank SCCB slave interface YSCL YSDA formatter MIPI control interface DI VCM driver VCMGND DVP MIPI VCMISNK YY[11:0] MDP1 MDN1 MDP2 MDN2 8810_DS_1_1 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

21 format and frame rate table 2-1 format and frame rate format resolution frame rate scaling method pixel clock (RAW) 8 megapixel 3264 x fps 96 MHz 5 megapixel 2592 x fps cropping 96 MHz 1080p 1920 x fps cropping 96 MHz 720p 1280 x fps binning, cropping 96 MHz 1/4 full size a 1/16 full size b 1632 x fps binning 96 MHz 816 x fps binning, VarioPixel 48 MHz VGA 640 x fps binning, VarioPixel 48 MHz QVGA 320 x fps binning, VarioPixel 48 MHz a. 1632x1224 is the maximum 2:1 downsample size b. 816x612 is the maximum 4:1 downsample size PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

22 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 2.4 system clock control The OV8810 PLL allows for an input clock frequency ranging from 6~27 MHz. figure 2-2 system clock control diagram input SCLK PRE_DIVIDER /1/2/4/8 R3011[3:0] VT_SYS_DIV /1/2/4/8 R300E[7:4] RPCLKDiv /1/2/4/8 R3083[1:0] DVP_PCLK pll_sys_clk PLL controller PLL multiplier R3010[6:1]*2 DIV8 /1/4/5/6 R300E[2:0] pll_mipi_clk MIPI_CLK OP_SYS_DIV /1/2/4/8 R300F[7:4] OP_PIX_DIV /1/2/4/8 R300F[3:0] MIPI_PCLK note If DVP is enabled, DIV8*VT_SYS_DIV must be even of 1 to get 50% duty cycle SCLK. 8810_DS_2_2 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

23 2-5 figure 2-3 example of MIPI with two data lanes and RAW12 data xvclk 24MHz pll_sys_clk PRE DIVIDER / 2 VT_SYS_DIV / 1 pll_mipi_clk 576MHz 12MHz OP_SYS_DIV / 1 PLL multiplier x 48 RPCLKDiv / 1 SCLK 96MHz PCLK 96MHz OP PIX DIV / 4 figure 2-4 example of MIPI with two data lanes and RAW10 data xvclk 24MHz pll_sys_clk PRE DIVIDER / 2 VT_SYS_DIV / 1 pll_mipi_clk 480MHz 12MHz OP_SYS_DIV / 1 PLL multiplier x 40 RPCLKDiv / 1 SCLK 96MHz PCLK 96MHz OP PIX DIV / 4 DIV8 / 6 MIPI_PCLK 144MHz MIPI_CLK 576MHz DIV8 / 5 MIPI_PCLK 120MHz MIPI_CLK 480MHz pll_sys_clk 96MHz pll_mipi_clk 576MHz pll_sys_clk 96MHz 8810_DS_2_3 pll_mipi_clk 480MHz 8810_DS_2_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

24 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 2.5 SCCB interface The Serial Camera Control Bus (SCCB) interface controls the image sensor operation. Refer to the OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port slave address The device/slave address of the OV8810 is 0x6C for write and 0x6D for read message type The OV8810 supports the message format shown in figure 2-5. figure read/write operations SCCB message format message type: 16-bit index, 8-bit data, and 8-bit slave address S slave address R/W A sub address A sub address [15:8] [7:0] A The OV8810 supports four different read operations and two different write operations: single read from random location sequential read from random location single read from current location sequential read from current location single write to random location sequential write to random location The index in the slave device must be auto incremented after each read/write operation multi-byte registers addr[7:1] addr[0] index[7:0] from slave to master from master to slave direction depends on operation The OV8810 has both 8-bit and 16-bit registers. Partial access to multi-byte registers is not allowed. A multi-byte register shall only be accessed by a single sequential message. When a multi-byte register is accessed, its first byte is accessed first, its second byte is accessed second, etc. When a multi-byte register is accessed, the following re-timing rules must be followed: S P Sr START condition STOP condition data repeated START condition A/A A A P acknowledge negative acknowledge 8810_DS_2_5 for a write operation, the updating of the register shall be deferred to a time when the last bit of the last byte has been received for a read operation, the value read shall reflect the status of all bytes at the time that the first bit of the first byte has been read proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

25 MIPI PHY The CSI-2 specification defines standard data transmission and control interfaces between transmitter and receiver. The MIPI data transmission interface is a unidirectional differential serial interface with data and clock signals. The physical layer of this interface is the MIPI Alliance Standard for D-PHY. 2.7 power up sequence Based on the system power configuration (1.8V or 2.8V for I/O power, using external DVDD or internal DVDD, requiring access to the I2C during power up period or not), the power up sequence will differ. If 1.8V is used for I/O power, using the internal DVDD is preferred. If 2.8V is used for I/O power, due to a high voltage drop at the internal DVDD regulator, there is a potential heat issue. Hence, for a 2.8V power system, OmniVision recommends using an external DVDD source. Due to the higher power down current when using an external DVDD source, OmniVision strongly recommends cutting off all powers, including the external DVDD, when the sensor is not in use in the case of 2.8V I/O and external DVDD power up with internal DVDD and I2C access during power up period For powering up with the internal DVDD and I2C access during the power ON period, the following conditions must occur: 1. if V DD-IO and V DD-A are turned ON at the same time, make sure V DD-IO becomes stable before V DD-A becomes stable 2. YPWDN is active high with an asynchronized design (does not need clock) 3. YPWDN must go high if I2C is accessed during the power up period 4. for YPWDN to go low, power up must first become stable (AVDD to PWDN > 1 ms) 5. YRESET_B is active low with an asynchronized design 6. state of YRESET_B does not matter during power up period once DOVDD is up figure 2-6 power up timing with internal DVDD and I2C access during power up period VDD_IO (DOVDD) VDD_A (AVDD) YPWDN I2C VDD_IO first, then VDD_A, and rising time is less than 5 ms T0 power on period T2 I2C activity is okay during entire period power down note T0 0 ms: delay from VDD_IO stable to VDD_A stable T2 1 ms: delay from VDD_A stable to sensor power up stable 8810_DS_2_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

26 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology power up with internal DVDD and no I2C access during power up period For powering up with the internal DVDD and no I2C access during the power ON period, the following conditions must occur: 1. if V DD-IO and V DD-A are turned ON at the same time, make sure V DD-IO becomes stable before V DD-A becomes stable 2. YPWDN is not required if there is no I2C access during the power up period 3. no I2C activity is allowed during the power up period (see gray area in figure 2-7) 4. YRESET_B is active low with an asynchronized design 5. state of YRESET_B does not matter during power up period once DOVDD is up figure 2-7 power up timing with internal DVDD and no I2C access during power up period VDD_IO (DOVDD) VDD_A (AVDD) note I2C VDD_IO first, then VDD_A, and rising time is less than 5 ms T0 power on period no I2C activity in power on period (gray area) T0 0 ms: delay from VDD_IO stable to VDD_A stable T2 1 ms: delay from VDD_A stable to sensor power up stable T2 8810_DS_2_7 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

27 power up with external DVDD source and I2C access during power up period For powering up with an external DVDD source and I2C access during the power ON period, the following conditions must occur: 1. if V DD-IO and V DD-A are turned ON at the same time, make sure V DD-IO becomes stable before V DD-A becomes stable 2. if V DD-A and V DD-D are turned ON at the same time, make sure V DD-A becomes stable before V DD-D becomes stable 3. YPWDN is active high with an asynchronized design (does not need clock) 4. for YPWDN to go low, power up must first become stable (DVDD to PWDN > 1 ms) 5. all powers are cut off when the camera is not in use (power down mode is not recommended 6. YRESET_B is active low with an asynchronized design 7. state of YRESET_B does not matter during power up period once DOVDD is up figure 2-8 power up timing with external DVDD source and I2C access during power up period VDD_IO (DOVDD) VDD_A (AVDD) VDD_D (DVDD) YPWDN note I2C VDD_IO first, then VDD_A, followed by VDD_D, and rising time is less than 5 ms T0 power on period T1 T2 I2C activity is okay during entire period T0 0 ms: delay from VDD_IO stable to VDD_A stable T1 0 ms: delay from VDD_A stable to VDD_D stable T2 1 ms: delay from VDD_D stable to sensor power up stable cut off power 8810_DS_2_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

28 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology power up with external DVDD and no I2C access during power up period For powering up with an external DVDD source and no I2C access during the power ON period, the following conditions must occur: 1. if V DD-IO and V DD-A are turned ON at the same time, make sure V DD-IO becomes stable before V DD-A becomes stable 2. if V DD-A and V DD-D are turned ON at the same time, make sure V DD-A becomes stable before V DD-D becomes stable 3. all powers are cut off when the camera is not in use (power down mode is not recommended 4. YRESET_B is active low with an asynchronized design 5. state of YRESET_B does not matter during power up period once DOVDD is up figure 2-9 VDD_IO (DOVDD) VDD_A (AVDD) VDD_D (DVDD) note I2C 2.8 power on reset (POR) power up timing with external DVDD source and I2C access during power up period The power ON reset (POR) can be controlled from an external pin. However, inside the OV8810, there is a power ON reset generation function to auto detect core power at stable state. 2.9 power down (PWDN) VDD_IO first, then VDD_A, followed by VDD_D, and rising time is less than 5 ms T0 power on period T1 no I2C activity during power on period (gray area) T0 0 ms: delay from VDD_IO stable to VDD_A stable T1 0 ms: delay from VDD_A stable to VDD_D stable T2 1 ms: delay from VDD_D stable to sensor power up stable T2 cut off power 8810_DS_2_9 The OV8810 can be set to standby/sleep mode by setting register 0x30FA[0] to be "0" or assert YPWDN pin to be high. In power down or standby/sleep mode, all pads are powered down, no drive for output pad (tri-state) and input is fixed at high. YPWDN is an asynchronized design. No clock is needed to enter power down mode. The input clock can be on all the time with no need to stop. The I2C starts to work after YPWDN is released from high to low. It is strongly recommended to set sensor into sleep mode before switching sensor's resolution and wake it up after loading the registers related to resolution change. proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

29 2-11 figure 2-10 OV8810 reference schematic AVDD C7 C10 DOVDD DGND AGND AGND AGND C14 C17 C19 C20 AGND 0.1μF μF μF/6V 10μF/6V 10μF/6V 10μF/6V DGND AVDD SVDD PVDD DOVDD HREF SIOC SIOD STROBE EXCLK D11 D10 D9 D0 R AGND L3 L5 L6 L7 C11 B9 C8 C9 D9 E9 E8 F9 F8 G9 F7 G1 G2 F1 B7 SGND YHREF YSCL YSDA B8 YSTROBE YXVCLK AVDD AGND YY11 YY10 YY9 DOVDD DOGND YY0 EM2 I9 EGND C3 0.1μF-0603 AVDD PVDD H8 0.1μF-0603 A8 AGND EGND I8 PVDD 3.3μH-L μH-L μH-L μH-L1008 SVDD C4 0.1μF-0603 A4 SGND MDP2 G7 MDP2 V_2.8V A7 SVDD MDN2 G6 MDN2 C15 0.1μF-0603 GND VREFH B6 VREFH VREFN A6 VREFN PWDN B5 U1 YPWDN RESETB A5 YRESET_B VSYNC A3 OV8810 CSP EGND H6 C12 0.1μF-0603 EVDD I6 C1 C2 MCP H5 MCP EVDD 2 1 VIN DGND 0.1μF μF-0603 MCN H4 MCN U2 XC6203E1502P-SOT89 YVSYNC MDP1 I4 MDP1 FREX B3 YFREX MDN1 I3 MDN1 D8 A1 YY8 VCMGND I2 VCM_GND OUT 3 D7 YY7 A2 VCMISNK I1 VCMISNK F L2 L4 B4 SVDD DOGND DOVDD YY6 YY5 YY4 YY3 YY2 YPCLK DOVDD DOGND EM1 A9 C5 0.1μF-0603 DGND DVDD YY1 B1 B2 C1 C2 D1 D2 E1 F2 H9 G8 H1 H2 E2 D6 D5 D4 D3 D2 PCLK D1 DGND 3.3μH-L μH-L1008 C6 C8 R μF μF-0603 C9 DOVDD 0.1μF-0603 DVDD C13 EVDD C16 DVDD 10μF/6V DGND 10μF/6V EGND V_2.8V L1 VCMISNK STROBE DGND R R R R R R note 1 note 2 note 3 note 4 note 5 note 6 10μH AGND MDP2 MDN2 MCP MCN MDP1 MDN1 D5 1 D7 3 D9 5 D11 7 RESETB 9 VCM_GND J2 HEADER6X1 11 HREF 13 VSYNC 15 PCLK D3 23 D1 25 R R GND F D3 D5 D7 D9 RESET NC HREF VSYNC PCLK PWR PWR D1 NC NC NC GND EGND J1 CON32A D2 2 D4 4 D6 6 D8 8 PWDN 10 SIOD 12 SIOC 14 GND 16 GND 18 XCLK 20 GND 22 D0 24 NC 26 NC 28 NC 30 GND 32 AVDD, SVDD and PVDD should be 2.8V ±5%. D4 D6 D8 D10 PWDN SIOD SIOC EXCLK D2 D0 DOVDD DOVDD can be from V. In this reference design, it is 2.8V. R8 10K-0603 C18 0.1μF-0603 R FREX RESETB For compact design, short SVDD and AVDD by mounting R7 and removing L5, C17. For compact design, short EVDD and DVDD by mounting R6 and removing L4, C16. If you want to use internal 1.5V regulator for DVDD, remove C15, U2, L2 and L4. From power consumption point of view, external DVDD is recommended for 2.8V DOVDD and internal DVDD is recommended for 1.8V DOVDD. J2 is for MIPI interface PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

30 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

31 3-1 3 block level description 3.1 pixel array structure The OV8810 sensor has an image array of 3296 columns by 2480 rows (8,174,080 pixels). figure 3-1 shows a cross-section of the image sensor array. The color filters are arranged in a Bayer pattern. The primary color BG/GR array is arranged in line-alternating fashion. Of the 8174,080 pixels, 8,121,344 (3296 x 2464) are active pixels and can be output. The top 16 rows are used for black level calibration. Considered about the defect pixel correction function and interpolation, the center 3288x2456 output from the whole active pixel array is the suggested max output size. The backend processor can use the boundary pixels for additional processing. The sensor array design is based on a field integration read-out system with line-by-line transfer and an electronic shutter with a synchronous pixel read-out scheme. figure 3-1 sensor array region color filter layout columns OV8810 array support 2x1 Binning in H direction to get higher sensitivity and lower noise in downsample mode. In V direction, array can do skip only. rows B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R line optical 6 black B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R B Gb B Gb B Gb Gr R Gr R Gr R 8810 DS PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

32 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology figure 3-2 pixel readout: binning versus skip 3.2 analog amplifier When the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. The amplifier gain can either be programmed by the user or by the internal automatic gain control (AGC) circuit bit A/D converters After the analog amplifier, the Bayer pattern raw signal is fed to two 12-bit analog-to-digital (A/D) converters, one for G channel and one that is shared by BR channels. These A/D converters operate at speeds up to 48 MHz and are fully synchronous to the pixel rate (actual conversion rate is related to the frame rate). 3.4 VCM driver figure 3-3 VCM block diagram G R G R G R G R column 2x binning, row 2x skip resistor Rs = 3.3 Vvcm current sinking pad RP1 G R G R column and row 2x skip G R G R 8810_DS_3_2 voice coil motor RVCM Vds VCM GND PAD RP2 8810_DS_3_3 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

33 3-3 The maximum SINK current can be estimated as: ISINK = (Vvcm - Vds) / (Rs + Rvcm + Rp1 + Rp2) Vds is the transistor headroom Rp1 and Rp2 are the resistance in the current path RVCM is the resistance of the voice coil motor. The OV8810 VCM driver is a single 10-bit DAC with 100 ma output current sink capability. It is designed for linear control of the VCM. The DAC is controlled via the SCCB interface with clock rates up to 400 Hz. The OV8810 VCM driver provides three types of output current control modes that allow users to adjust transient response of the sinking current output current control mode The OV8810 VCM driver uses 4 bits (S3, S2, S1, and S0) to control the output current response. 1. S[3:0] = X000: Directly jump mode: code directly jumps to target code. Output current transient response time is shown in table S[3:0] = 0001 to 0111: Single step mode: code increases/decreases by a single step. Single step time durations are 50µs, 100µs, 200µs, 400µs, 800µs, 1600µs, and 3200µs, which are controlled by S2, S1, and S0 see table S[3:0] = 1001 to 1111: Multi-code steps mode: Code increases/decreases in multi-code steps. If the target code and the current code have a difference larger than 128, the 64-code step is applied first. When the difference in between target and current codes is no more than 128 but larger than 16, the 16-code step is used. When the difference is less than 16, it will directly jump to the target code. Single step time options are 50µs, 100µs, 200µs, 400µs, 800µs, 1600µs, and 3200µs, which are controlled by S2, S1, and S0, see table 3-4. table 3-1 VCM driver control function register description Bit[3:0]: Current transient response control current transient response x000: mode 0 0x30ED control 0001~0111: mode ~1111: mode 2 10-bit DAC code clock divider 0x30EC[5:0], 0x30ED[7:4] 0x30EE[3:0], 0x30EF[7:0] 0x30EC[5:0]: 0x30ED[7:4]: D[9:4] D[3:0] divide external clock to obtain a 20 KHz clock for VCM control block VCM control clock = external clock / Rdiv[11:0] PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

34 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 3-2 VCM control registers address register name 0x30EC VCM[15:8] 0x01 RW 0x30ED VCM[7:0] 0x50 RW default value R/W description Bit[7]: Bit[6]: Bit[5:0]: Bit[7:4]: Bit[3]: Bit[2:0]: PD Reserved D[9:4] D[3:0] S3 S[2:0] 0x30EE SLEW[11:8] 0x05 RW Bit[3:0]: Rdiv[11:8] 0x30EF SLEW[7:0] 0x46 RW Bit[7:0]: Rdiv[7:0] 0x30A5 SLEW 0x00 RW table 3-3 single step mode mode S3 S2 S1 S0 single step mode Bit[2:0]: single step transition time VCM output current control 000: 0.71 * Id 001: 0.77 * Id 010: 0.83 * Id 011: 0.91 * Id 100: 1.00 * Id 101: 1.11 * Id 110: 1.25 * Id 111: 1.43 * Id µs 51.15ms µs 102.3ms µs 204.6ms µs 409.2ms µs 818.4ms µs 1.637s µs 3.274s full scale transition time (1023 steps) proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

35 3-5 table 3-4 multi-code step mode mode S3 S2 S1 S0 single step mode figure 3-4 single step transition time 1/4 to 3/4 scale settling time (directly jump mode, VDD = 3.0V) full scale transition time (22 steps) a a. a full scale transition includes fourteen 64-code steps, seven 16-code steps and one directly jump step. output current (ma) 1.00E E E E E E E E E E E E µs 1.1ms µs 2.2ms µs 4.4ms µs 8.8ms µs 17.6ms µs 35.2ms µs 70.4ms 1.27E E E E-03 1/4 to 3/4 scale settling time (VDD = 3.0V) 1.35E E _DS_3_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

36 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology figure 3-5 sink current vs. code (VDD = 3.0V, reg 0x30A5 = 0x05, VCM resistance = 23ohms) IOUT (ma) CODE _DS_3_5 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

37 4-1 4 image sensor core digital functions 4.1 mirror and flip The OV8810 provides two independent options for alternating the readout order of the image data, horizontally mirrored and vertically flipped readout modes, which respectively reverse the sensor data readout order horizontally and vertically. In mirror mode, since the Bayer order changes BGBG to GBGB, we usually delay the readout sequence by one pixel. In vertical flip mode, the ISP block will detect whether the pixel is in a red line or in a blue line and make the necessary adjustment. Thus, the OV8810 supports four pixel readout modes, standard, horizontally mirrored, vertically flipped, and both horizontally mirrored and vertically flipped, which is shown in figure 4-1. figure 4-1 mirror and flip samples F original image mirrored image F F flipped image table 4-1 mirror and flip function control function register description Bit[6]: mirror ON/OFF select mirror a 0x30F8 0: mirror OFF 1: mirror ON Bit[7]: flip ON/OFF select flip b 0x30F8 0: flip OFF 1: flip ON a. To get correct color with mirror function ON, skip on pixel by setting register bit 0x3316[0] to 1 b. To get correct color with flip function ON, skip one row by setting register bit 0x3079[0] to1 F mirrored and flipped image 8810_DS_4_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

38 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 4.2 image cropping and windowing The image cropping area is defined by four parameters, x_start_address, x_end_address, y_start_address, and y_end_address. By properly setting these parameters, any portion within the sensor array can be cropped as a visible area. Cropping is achieved by simply masking the pixels outside the cropped window. It is independent of flip and mirror. The output size of the image data is determined by the window size defined by x_output_size and y_output_size, which means that only part of the visible pixel data is output. The difference between cropping and windowing is that cropping can achieve a higher frame rate by adjusting the frame timing appropriately while windowing cannot. figure 4-2 (x_addr_min, y_addr_min) (x_addr_start, y_addr_start) image windowing and cropping table 4-2 windowing and cropping control registers (sheet 1 of 2) function register description x_addr_min physical limit 0 y_addr_min physical limit 0 x_addr_max physical limit 3295 y_addr_max physical limit 2463 x_addr_start y_addr_start H_start V_start output Image visible pixel array region addressable pixel array region 0x3024 ~ 0x3025 0x3026 ~ 0x _DS_4_2 x_output_size, y_output_size (x_addr_end, y_addr_end) (x_addr_max, y_addr_max) cropping start address relative to the addressable pixel array region in H direction x_addr_start[15:0] = {0x3024[7:0], 0x3025[7:0]} cropping start address relative to the addressable pixel array region in V direction y_addr_start[15:0] = {0x3026[7:0], 0x3027[7:0]} proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

39 4-3 table 4-2 windowing and cropping control registers (sheet 2 of 2) function register description x_addr_end y_addr_end x_output_size y_output_size H_start H_end V_start V_end 0x3028 ~ 0x3029 0x302A ~ 0x302B 0x302C ~ 0x302D 0x302E ~ 0x302F 0x3318, 0x3316 0x3318, 0x3317 0x331B, 0x3319 0x331B, 0x331A cropping end address relative to the addressable pixel array region in H direction x_addr_end[15:0] = {0x3028[7:0], 0x3029[7:0]} cropping end address relative to the addressable pixel array region in V direction y_addr_end[15:0] = {0x302A[7:0], 0x302B[7:0]} output image size in H direction x_output_size[15:0] = {0x302C[7:0], 0x302D[7:0]} output image size in V direction y_output_size[15:0] = {0x302E[7:0], 0x302F[7:0]} windowing start address relative to the visible pixel array region in H direction H_start[11:0] = {0x3318[3:0], 0x3316[7:0]} windowing end address relative to the visible pixel array region in H direction H_end[11:0] = {0x3318[7:4], 0x3317[7:0]} windowing start address relative to the visible pixel array region in V direction V_start[11:0] = {0x331B[3:0], 0x3319[7:0]} windowing end address relative to the visible pixel array region in V direction V_end[11:0] = {0x331B[7:4], 0x331A[7:0]} PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

40 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 4.3 test pattern For testing purposes, the OV8810 offers one type of test pattern, color bar. figure 4-3 table 4-3 color bar test pattern selection control function register description test pattern ON/OFF color bar 0x3508 0x3303 color bar Bit[7]: test pattern ON/OFF select 0: OFF 1: ON Bit[6:5]: mode select 00: 10-bit shift 01: 12-bit shift 10: 8-bit shift 11: Not used Bit[4]: data duplicate enable 0: data shift one bit every pixel 1: data shift one bit every two pixels Bit[7]: Bit[0]: bar move enable 0: disable bar move 1: enable a H bar moving from top to bottom color bar enable 0: color bar OFF 1: color bar enable proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

41 /60 Hz detection When the integration time is not an integer multiple of the period of light intensity, the image will flicker. Since man-made light sources are usually powered by AC power sources, most of them have a frequency of 50 Hz or 60 Hz. The function of the detector is to check whether the sensor is under a 50 Hz or 60 Hz light source so that the basic step of integration time can be determined. Auto 50/60Hz detection function can be turned on by setting register 0x3014[6] to be "1". The detection result can be read out through an indirect mapping y setting register 0x304C to be 0x0C and read out the value from register 0x303D[0] "1" indicates it is a 50Hz environment and "0" indicates it is a 60Hz environment. 4.5 AEC and AGC algorithms Auto Exposure Control (AEC) and Auto Gain Control (AGC) allow the OV8810 to adjust the image brightness to a desired range by setting the proper exposure time and gain applied to the image. Besides automatic adjustment, exposure time and gain can also be manually controlled externally. The related registers are listed in table 4-4 There are two different algorithms that detect whether the current frame is too bright or too dark and determine if the exposure time/gain should increase or decrease for the next frame. The AEC algorithm uses the average luminance of the current frame to determine exposure time of the next frame. table 4-4 AEC/AGC control registers function register description AEC enable 0x3013 The average-based AEC controls image luminance using registers WPT (0x3018) and BPT (0x3019). The value of register WPT (0x3018) indicates the high threshold value and the value of register BPT (0x3019) indicates the low threshold value. When the target image luminance average value YAVG (0x301B) is within the range specified by registers WPT (0x3018) and BPT (0x3019), the AEC keeps the current exposure time unchanged. When YAVG (0x301B) is greater than the value in register WPT (0x3018), meaning it is too bright, the AEC will decrease the exposure time. When YAVG (0x301B) is less than the value in register BPT (0x3019), meaning it is too dark, the AEC will increase the Bit[0]: AEC enable 0: manual 1: auto AEC (exposure time) 0x3002 ~ 0x3003 AEC[15:0] = {0x3002[7:0], 0x3003[7:0]} AGC (gain) AGC enable 0x3000 0x3013 Global analog gain, up to 15.5x AGC[6:0] = 0x3000[6:0] Gain = (AGC[6]+1)*(AGC[5]+1)* (AGC[4]+1)*(AGC[3:0]/16+1) Bit[2]: AGC enable 0: manual 1: auto PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

42 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology exposure time. Accordingly, the value in register WPT (0x3018) should be greater than the value in register BPT (0x3019). The gap between the values of registers WPT (0x3018) and BPT (0x3019) controls the image stability. The AEC function supports both standard and fast adjustment when updating the exposure time so that the consequent image luminance falls into the range between WPT and BPT. AEC in standard mode allows single-step increment or decrement in the adjustment. AEC in fast mode updates the increment or decrement ten times faster. Register VPT (0x301A) controls the fast AEC range. If the target image YAVG (0x301B) is greater than 0x301A[7:4] 16, AEC will decrease by 2. If YAVG (0x301B) is less than 0x301A[3:0] 16, AEC will increase by 2. As shown in figure 4-4, the AEC/AGC convergence uses two regions, the inner stable operating region and the outer control zone, which defines the convergence step size change as follows: outside control zone step size: 2 (AEC[15:0]) t STEP : t ROW (2 AEC[15:0]) inside control zone step size: 2 (AEC[15:0]) 16) t STEP : t ROW (2 AEC[15:0] 16) Once the current value is inside the stable operating region, the AEC/AGC value has converged. The Step Limit register acts to create a "middle ground" by limiting the maximum step size to 32 rows (delay time = t ROW 32). figure 4-4 control zone desired convergence control zone upper limit: {VPT[7:4] (0x301A[7:4]), 4'b0000} control zone lower limit: {VPT[3:0] (0x301A[3:0]), 4'b0000} desired convergence stable operating region 8810_DS_4_3 stable operating region upper limit: WPT[7:0] (0x3018) stable operating region lower limit: BPT[7:0] (0x3019) proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

43 average luminance (YAVG) Auto exposure time calculation is based on a frame brightness average value. table 4-5 AEC control functions function register description WPT BPT VPT YAVG AEC update speed 0x3018 0x3019 0x301A 0x301B 0x3013 luminance signal / histogram high range for AEC/AGC operation AEC/AGC value decreases in auto mode when average luminance histogram is greater than WPT[7:0]. luminance signal / histogram low range for AEC/AGC operation AEC/AGC value increases in auto mode when average luminance histogram is less than BPT[7:0]. fast mode large step range thresholds - effective only in AEC/AGC fast mode Bit[7:4]: high threshold Bit[3:0]: low threshold AEC/AGC may change in larger steps when luminance average is greater than VPT[7:4] or less than VPT[3:0]. luminance average - this register will auto update. Average luminance is calculated from the B/Gb/Gr/R channel average as follows: B/Gb/Gr/R channel average = (BAVG[7:0] + GbAVG[7:0] + GrAVG[7:0] + RAVG[7:0]) 0.25 Bit[7]: AEC speed select 0: standard 1: fast PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

44 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 4-6 AGC control functions (sheet 1 of 2) function register description LAEC ON/OFF LAEC manual ON/OFF banding ON/OFF VAEC ON/OFF auto banding VAEC ceiling (maximum integration time) AGC ceiling (maximum gain) maximum band for 50 Hz 0x3013 0x3014 0x3013 0x3014 0x3013 0x3015 maximum band for 60 Hz 0x3015 0x301C 0x301D Bit[3]: Bit[1]: Bit[5]: Bit[3]: Bit[4]: Bit[6:4]: Bit[2:0]: Bit[5:0]: Bit[5:0]: LAEC enable 0: OFF 1: ON LAEC manual ON/OFF (when register 0x3013[3] = 1) 0: auto mode 1: manual mode Banding filter enable 0: OFF 1: ON VAEC enable 0: OFF 1: ON Auto banding enable (turn OFF banding automatically when it is too bright) ON/OFF 0: OFF 1: ON VAEC ceiling 000: 1 frame 001: 1.5 frame 010: 2 frames 011: 3 frames 100: 4 frames 101: 6 frames 110: 8 frames 111: 12 frames AGC ceiling 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x : Not used Maximum band for 50 Hz in terms of row exposure Maximum band for 60 Hz in terms of row exposure band step for 50 Hz 0x305C ~ 0x305D BD50st[9:0] = {0x305C[1:0], 0x305D[7:0]} band step for 60 Hz 0x305E ~ 0x305F BD60st[9:0] = {0x305E[1:0], 0x305F[7:0]} proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

45 4-9 table 4-6 AGC control functions (sheet 2 of 2) function register description auto 50/60Hz detection 50/60Hz selection AEC/AGC steps The AEC and AGC work together to obtain adequate exposure/gain based on the current environmental illumination. In order to achieve the best SNR, extending the exposure time is always preferred rather than raising the gain when the current illumination is getting brighter. Vice versa, under dark conditions, the action to decrease the gain is always taken prior to shortening the exposure time auto exposure control (AEC) The function of the AEC is to calculate the integration time of the next frame and send the information to the timing control block. Based on the statistics of previous frames, the AEC is able to determine whether the integration time should increase, decrease, fast increase, fast decrease, or remain the same. In extremely bright situations, the LAEC activates, allowing integration time to be less than one row. In extremely dark situations, the night mode activates, allowing integration time to be larger than one frame. To avoid image flickering under a periodic light source, the integration time can be adjusted in steps of integer multiples of the period of the light source. This new AEC step system is called the banding filter, suggesting that the exposure time is not continuous but falls in some steps. Banding filter ON/OFF can be set in register bit 0x3013[5] LAEC With LAEC function ON, if the integration time is only one row period but the image is too bright, AEC will enter LAEC mode. Within LAEC, the integration time can be further decreased. LAEC and AEC will not work simultaneously in auto mode. LAEC will be triggered only when {0x3002, 0x3003} equals to 0. LAEC ON/OFF can be set in register bit 0x3013[3]. Manual LAEC adjustment can be turned by setting register bit 0x3014[1]. The integration time is indicated by 0x3002-0x3005. It includes two kinds of integration time: AEC {0x3002[7:0], 0x3003[7:0]} indicates the number of Tline, and LAEC {0x3004[7:0], 0x3005[7:0]} indicates number of Tp. The minimum LAEC value is 0x180 Tp. 0x3014 0x3014 Bit[6]: Bit[7]: Auto 50/60Hz detection enable 0: OFF 1: ON 50/60Hz manual selection (functions only when register 0x3014[6] = 0) 0: 60Hz 1: 50Hz The maximum LAEC value is (line length - 0x3B2). With OV8810's default value, the max LAEC equals to 0xB66 Tp PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

46 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology banding mode ON with AEC In Banding ON mode, the exposure time will fall in steps of integer multiples of the period of light intensity. This design is to reject image flickering when the light source is not steady but periodical. For a given light flickering frequency, the band step can be expressed in units of row period. Band Step = 'period of light intensity' 'frame rate' 'rows per frame'. The band steps for 50Hz and 60Hz light sources can be set in registers {0x305C[1:0], 0x305D[7:0]} and {0x305E[1:0], 0x305F[7:0]}, respectively. When auto banding is ON, if the next integration time is less than the minimum band step, banding will automatically turn OFF. It will turn ON again when the next integration time becomes larger than the minimum band. If auto banding is disabled, the minimum integration time is one band step. Auto banding can be set in register bit 0x3013[4] banding mode OFF with AEC When banding mode is OFF, integration time increases/decreases as normal. It is not necessarily multiples of band steps VAEC (night mode) The OV9810 supports long integration time such as 1 frame, 1.5 frames, 2 frames, 3 frames, 4 frames, 6 frames, 8 frames, and 12 frames in dark conditions. This is achieved by slowing down the original frame rate and waiting for exposure. Night mode ceiling can be set in register bits 0x3015[6:4]. Night mode can be disabled by setting register bit 0x3014[3] to 0. In night mode, the increase and decrease step controlled by the width of VSYNC is based frame. Night mode is triggered by sensor analog gain threshold which is defined in register 0x3015[2:0] auto gain control (AGC) Unlike prolonging integration time, increasing gain will amplify both signal and noise. Thus, AGC usually starts after AEC is full. However, in cases where adjacent AEC step changes are too large (>1/16), AGC steps should be inserted in between; otherwise, the integration time will keep switching between two adjacent steps and the image flickers. The OV8810 supports up to 15.5x analog gain controlled by AGCL (0x3000[6:0]) and additional 4x digital gain controlled by AGC (0x3006[1:0]) in AGC control. Sensor's gain is indicated by register {0x3006[1:0], 0x3000[6:0]}. The total gain = (AGC[1]+1)*(AGC[0]+1)*(AGCL[6]+1)*(AGCL[5]+1)*(AGCL[4]+1)*(AGCL[3:0]/16+1) integration time between 1~16 rows When integration time is less than 16 rows, the changes between adjacent AEC steps are larger than 1/16, which may possibly make the image oscillate between two AEC levels; thus, some AGC steps are added in between gain insertion between AEC banding steps When banding mode is ON, the integration time changes in step of the period of light intensity. For the first 16 band steps, since the exposure time change between adjacent steps is larger than 1/16, AGC steps are inserted to ensure image stability. proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

47 gain insertion between night mode steps Between night mode steps (e.g., integration time = 1 frame and 2 frames), AGC steps are inserted to ensure no adjacent step change is larger than 1/ when AEC reaches maximum When AEC reaches its maximum step while the image is still too dark, the gain starts to increase until the new frame average falls into the stable range or AGC reaches its maximum step. The AGC ceiling can be set in 0x3015[2:0]. 4.6 strobe flash control To achieve the best image quality possible under low light conditions, the use of strobe flash is recommended. The OV8810 supports two different strobe flash control source: one is in rolling shutter mode and one is for frame exposure mode. The selection of the strobe mode is defined in register 0x30E7[1] strobe in rolling shutter mode For strobe in rolling shutter mode, defined by set register 0x30E7[1] = 1, the OV8810 provides a programmable strobe signal function which supports both Xenon and LED flash through the strobe output pin.table 4-7 lists the strobe pulse control registers. table 4-7 strobe flash control functions function register description strobe source selection strobe function enable strobe output pulse polarity control xenon mode strobe pulse width strobe mode 0x30E7 0x30E8 0x30E8 0x30E8 Bit[1]: Bit[7]: Bit[6]: Bit[3:2]: Strobe source selection 0: frame exposure mode strobe source 1: rolling shutter mode strobe source strobe enable 0: disable 1: enable strobe output pulse polarity 0: positive pulse 1: negative pulse xenon mode strobe pulse width 00: 1 line 01: 2 lines 10: 3 lines 11: 4 lines 0x30E8 Bit[1:0]: strobe mode 00: xenon mode 01: LED1&2 mode 10: LED1&2 mode 11: LED3 mode PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

48 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology strobe pulse The strobe signal is programmable and supports both LED and Xenon modes. The polarity of the pulse can be changed. The strobe signal is enabled (turned high/low depending on the pulse s polarity) by requesting the signal via the SCCB. Flash modules are typically triggered by the rising edge (falling edge if the signal polarity is changed). It supports the flash modes shown in table 4-8. table xenon flash control After a strobe request is submitted, the strobe pulse will be activated at the beginning of the third frame. The third frame will be correctly exposed. The pulse width is programmable in Xenon mode between 1H and 4H, where H is one horizontal period ([1 / fps] [1 / number of total lines] sec). figure 4-5 flashlight modes mode output AEC/AGC AWB xenon one pulse no no LED1 pulse no no LED2 pulse no yes LED3 continuous yes yes vertical blanking exposure time xenon flash mode data out strobe request strobe pulse correctly exposed frame request here strobe pulse zoomed 1H 8810_DS_4_4 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

49 LED1 & 2 mode Two frames after the strobe request is submitted, the third frame is correctly exposed. The strobe pulse will be activated only one time if the strobe end request is set correctly (see figure 4-6). If end request is not sent, the strobe signal is activated intermittently until the strobe end request is set (see figure 4-7). The number of skipped frames is programmable. figure 4-6 LED 1 & 2 mode - one pulse output frame in is skipped vertical blanking exposure time data out strobe request strobe pulse correctly exposed frame start end request here the number of skipped frames is programmable 8810_DS_4_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

50 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology figure 4-7 LED 1 & 2 mode - multiple pulse output LED 3 mode In LED 3 mode, the strobe signal stays active until the strobe end request is sent (see figure 4-8). figure 4-8 vertical blanking exposure time data out strobe request strobe pulse vertical blanking exposure time correctly exposed frame data out strobe request LED 3 mode start request here frame in is skipped the number of skipped frames is programmable 8810_DS_4_6 strobe signal correctly exposed frame start request here end request here 8810_DS_4_7 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

51 strobe in frame exposure mode For strobe in frame exposure shutter mode, defined by setting register 0x30E7[1] = 0, the OV8810 supports Xenon flash through the strobe output pin. table 4-8 lists the strobe pulse control registers. Different from rolling shutter mode, strobe function in frame exposure mode is always ON. The only way to turn it off is by changing the YSTROBE pin from output to input by setting register bit 0x30B1[6] to "0", table 4-9 strobe flash control functions in frame exposure mode function register description strobe source selection strobe pin output enable 0x30E7 0x30B1 Bit[1]: Bit[6]: Strobe source selection 0: frame exposure mode strobe source 1: rolling shutter mode strobe source strobe pin I/O control 0: input 1: output strobe pulse width 0x30EA Bit[3:0]: strobe pulse width (1-16 Tline) PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

52 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 4.8 frame exposure (FREX mode) The OV8810 provides a frame exposure mode where an external mechanical shutter controls the pixel integration time. In FREX mode, whole frame pixels start integration at the same time, rather than integrating row by row. After the user-defined exposure time, the shutter closes, preventing further integration and the image begins to read out. After the readout finishes, the shutter opens again and the sensor resumes normal mode, waiting for the next FREX request. Frame exposure is valid only for full resolution mode. The OV8810 supports two modes of FREX (see figure 4-9): mode 1 - frame exposure request comes from the external system via the YFREX pin. The sensor will send a strobe output signal to control the flash light. External system also need to handle external mechanical shutter control and make it synchronized with YFREX pin. mode 2 - frame exposure request comes from the external system via the I2C register 0x30EB[0]. The sensor will output two signals, shutter control signal through the YFREX pin and strobe signal through the YSTROBE pin. In mode 1, the YFREX pin is configured as an input while it is configured as an output in mode 2. figure 4-9 note FREX modes sensor FREX shutter I2C data/sync MCLK system FREX and shutter inputs are removed. sensor shutter system I2C data/sync FREX MCLK shutter 8810_DS_4_8 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

53 through YFREX input pin (mode 1) When the YFREX input pin is pulled from low to high, the whole pixel array is charged at the same time. After a programmed time, the sensor begins to be exposed until the YFREX pin is pulled low. After that, the sensor enters standard readout mode and pixel data is read out progressively. figure 4-10 FREX mode 1 YVSYNC YFREX (INPUT) YSTROBE SHUTTER DATA/HREF this frame data should be reset rolling mode note 1 frame mode is triggered by the rising edge of FREX. note 2 TFE2V --- timing between FREX falling edge to VSYNC falling edge, not programmable. Around 7 Tlines. note 3 TR --- pre-charge time, controlled by register 0x30E4. note 4 TV2H --- timing between VSYNC falling edge to HREF's rising edge, default is around 12 Tlines. Programmable (see section 4.7.4). note 5 TSH --- shutter's latency, related to mechanical shutter's performance. note 6 TFL -- STROBE pulse width, controlled by register 0x30EA[3:0]. note 7 TEXP --- timing between STROBE rising edge to shutter close. note 8 STROBE should be triggered as soon as pre-charge is done. TR TFL note 9 shutter should be completely closed before the first HREF's rising edge and open after the frame mode data is read out. 8810_DS_4_9 TSH TEXP frame mode rolling mode TFE2V TV2H PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

54 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology through register control (mode 2) In this mode, the register is written to trigger frame exposure. The global reset time and exposure time are both programmable. After the global exposure finishes, the pixel data is read out progressively. figure 4-11 FREX mode 2 VSYNC frame exposure mode request (I2C) YFREX (output) YSTROBE shutter (controlled by FREX) DATA/HREF this frame data should be reset rolling mode note 1 frame mode is triggered by register bit 0x30EB[0] set to "1". note 2 TFE2V --- timing between FREX falling edge to VSYNC falling edge, not programmable. Around 7 Tlines. note 3 TR --- pre-charge time, controlled by reg0x30e4. ister note 4 TV2H --- timing between VSYNC falling edge to HREF's rising edge, default is around 12 Tlines. Programmable. note 5 TSH --- shutter's latency, related to mechanical shutter's performance. note 6 TFL -- STROBE pulse width, controlled by register 0x30EA[3:0]. note 7 TEXP --- timing between STROBE rising edge to shutter close. note 8 TFREX --- timing between frame mode trigger to the falling edge of FREX. if TSH = 0, TFREX = TEXP + TR. Controlled by {0x30E5, 0x30E6} note 9 STROBE will be triggered as soon as pre-charge is done. note 10 shutter should be completely closed before the first HREF's rising edge and open after the frame mode data is read out. 8810_DS_4_10 TR TFL TFREX TSH TEXP frame mode TFE2V TV2H rolling mode proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

55 strobe output in frame exposure In both frame exposure modes mentioned above, the strobe output pin can be pulled high as soon as pre-charge is done to indicate the pixel array is in global exposure mode. Thus, the strobe pin can be used to control the flash to sync with mechanical shutter. table 4-10 frame exposure control functions function register description frame exposure mode 0x30E7 Bit[0]: Frame exposure mode 0: From external YFREX pin 1: Register controlled frame exposure start register 0x30EB Bit[0]: Register-controlled global reset start FREX I/O control 0x30B2 Bit[4]: FREX pin I/O control 0: YFREX pin as input 1: YFREX pin as output Strobe width in frame exposure mode 0x30EA Bit[3:0]: Strobe pulse width (1-16Tline) Pre-Charge width 0x30E4 Bit[7:0]: Pre-charge width (Tline) Exposure time in frame exposure mode 0x30E5[7:0], 0x30E6[7:0] Frame mode exposure time (functions only when register 0x30E7[0] = 1) FREX output polarity 0x30E7 Bit[6]: YFREX output polarity control 0: Normal output is low, after trigger become high 1: Normal output is high, after trigger become low PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

56 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 4.9 compensation for mechanical shutter latency Due to the latency on mechanical shutter, data output might need to be delayed in frame exposure mode, so that shutter can be completely closed before data is sending out to make whole frame the same exposure time. When YFREX works as input signal, the whole timing control between YFREX and mechanical shutter is handled by external system. So external system may need to control shutter to close before pulling YFREX to low. When YFREX works as output, mechanical shutter is controlled by YFREX, so the latency compensation is more important. To add the delay for the data output, need to follow step below: 1. Set register {0x30E5, 0x30E6} to the correct exposure time. 2. Set register {0x301E, 0x301F} to the value of register {0x30E5,30E6} + TV2H (rows need to be delayed) just before enters into frame exposure mode 3. Set all other register related to frame exposure mode 4. Set register 0x30EB = 1 during a video stream output - not in vertical blank period 5. HREF will be delayed TV2H lines after falling edge of VSYNC one-time programmable (OTP) memory The high-density one-time programmable (OTP) memory of the OV8810 is organized as 128-bit by 1 electrical fuse with a random access interface. The main function is to store chip identification and manufacturing information. The OTP memory has three operation modes, program, read, and inactive. It is in inactive mode by default. When register 0x303E is set to 0xAA, the OTP memory enters program mode and data in the OTP registers (0x30D0~0x30DF) are sequentially burned into the OTP memory. When register 0x303E is set to 0x55, the OTP memory enters read mode and data in the OTP memory are read out and loaded into the OTP registers (0x30D0~0x30DF). table 4-11 summarizes the corresponding registers. The operation voltage for OTP write is AVDD = 2.5 ± 10% and for OTP read is AVDD = V. table 4-11 OTP memory control functions function register description OTP program data a OTP program/read enable 0x30D0 ~ 0x30DF 0x303E a. 0x30D0~0x30D4 for OmniVision and 0x30D5~0x30DF for customer data to be programmed into / read from the OTP memory 0x55: read OTP memory 0xAA: program OTP memory proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

57 5-1 5 image sensor processor digital functions 5.1 BLC and EvenOdd This module uses black lines to perform black level correction and to remove vertical even odd noise. It also has the option to use image information to remove vertical even odd noise. It uses 13-bit RAW input and 12-bit RAW data output. The BLC/even_odd options are as follows: manual mode reset mode freeze mode In preview mode, set sensor into gain trig mode by setting register 0x3071[4] = 1 can get smooth BLC adjustment. When switching between snapshot and preview mode, the sensor's resolution is changed, but gain and exposure might not be changed and BLC must be finished in one frame. Setting BLC into free running mode by setting register 0x3071[1] = 0 can make BLC work every frame. table 5-1 address BLC control registers (sheet 1 of 3) a register name 0x3300 TOP 0xFF RW 0x3071 TMC 0x00 RW default value R/W description ISP Enable Control 00 - corresponding clock will be stopped if one module is disabled Bit[1]: EvenOdd_en (functions only when Bit[0] = 1) 0: Disable 1: Enable Bit[0]: BLC_en 0: Disable 1: Enable Bit[7]: BLC freeze enable 0: BLC updating enable 1: Freeze current BLC value Bit[4]: BLC trig option 0: BLC keep adjusting every frame 1: BLC trig by Gain change Bit[3:2]: BLC reset frame counter (functions only when Bit[4] = 1, if there is no further change in gain, number of frames to be reset before BLC freeze) 00: 1 frame 01: 64 frames 10: 4 frames 11: 2 frames 0x3330 BLC RW BLC Control PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

58 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 5-1 BLC control registers (sheet 2 of 3) a address register name 0x3331 BLC 0x10 RW Bit[7:0]: BLC target low byte 0x3332 BLC 0x10 RW 0x3333 BLC 0x02 RW 0x3334 BLC 0x00 RW 0x3336 BLC_MAN0 0x00 RW 0x3337 BLC_MAN1 0x00 RW 0x3338 BLC_MAN2 0x00 RW 0x3339 BLC_MAN3 0x00 RW 0x333A BLC_MAN4 0x00 RW Bit[7:0]: Bit[5:4]: Bit[3:2]: BLC debug must be set to same value as register 0x3331 BLC target high byte BLC debug must be set to same value as register Bit[5:4] BLC option 0: BLC value is controlled by register 0x3347[1] 1: If gain is changed, no matter BLC is in average mode (register 0x3347[1] = 1), BLC will use current frame BLC value 0x333B BLC_MAN5 0x00 RW 0x333C BLC_MAN6 0x00 RW default value R/W description Bit[0]: Bit[5]: Bit[4]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Manual BLC offset option (functions only when Bit[4] = 1) 0: Use different registers for different channels 1: Use blc_man0 to compensate all channels BLC Manual BLC adjust enable (functions only when register 0x3300[0] = 1) 0: Auto BLC 1: Manual BLC BLC offset low byte B channel BLC offset low byte Gb channel BLC offset low byte Gr channel BLC offset low byte R channel BLC debug must be set to same value as register 0x3336 BLC debug must be set to same value as register 0x3337 BLC debug must be set to same value as register 0x3338 0x333D BLC_MAN7 0x00 RW Bit[7:0]: BLC debug must be set to same value as register 0x3339 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

59 5-3 table 5-1 BLC control registers (sheet 3 of 3) a address 0x333E BLC_MAN0/1 0x00 RW 0x333F BLC_MAN2/3 0x00 RW 0x3340 BLC_MAN5/6 0x00 RW 0x3341 BLC_MAN6/7 0x00 RW 5.2 LENC Bit[7:4]: Bit[3:0]: Bit[7:4]: Bit[3:0]: Bit[7:4]: Bit[3:0]: Bit[7:4]: Bit[3:0]: BLC offset high byte B channel BLC offset high byte Gb channel BLC offset high byte Gr channel BLC offset high byte R channel a. BLC target for short exposure and BLC target for long exposure should have the same value BLC debug must be set to same value as register 0x333E[7:4] BLC debug must be set to same value as register 0x333E[3:0] BLC debug must be set to same value as register 0x333F[7:4] BLC debug must be set to same value as register 0x333F[3:0] The LENC module corrects lens shading. Please use the OmniVision tool for lens correction tuning if you want to use the OV8810 LENC function. table 5-2 address LENC control registers register name 0x3300 TOP 0xFF RW 0x3350~ 0x33E3 register name default value R/W description LENC RW LENC Control ISP Enable Control 00 - corresponding clock will be stopped if one module is disabled (0: disable; 1: enable) Bit[4]: LENC_en 0x33E4 LENC 0x02 RW default value R/W description Bit[3:2]: Bit[1:]: Bit[0]: LENC vertical skip LENC auto gain enable LENC horizontal skip For full resolution or cropping from full resolution, set register 0x33E4 to 0x02 For 2:1 downsampling, set register 0x33E4 to 0x07 For 4:1 downsampling, set 0x33E4 to 0x0B For 8:1 downsampling, set 0x33E4 to 0x0F PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

60 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 5.3 digital gain This module supports up to 5x and precision is 1/64. It has two modes: auto mode manual mode table 5-3 address 5.4 AWB In this module, the simple AWB algorithm is used to automatically calculate white balance. AWB has a manual mode, freeze mode option and two stable ranges. The AWB gain precision is 12-bit and supports up to 4x gain. AWB gain = AWB_gain[11:0] / digital gain control registers register name 0x3301 TOP 0x08 RW 0x3308 BLC 0x33 RW 0x3309 DIG_GAIN 0x40 RW default value R/W description table 5-4 AWB control registers (sheet 1 of 2) address register name 0x3300 TOP 0xFF RW ISP Enable Control 01 - corresponding clock will be stopped if one module is disabled Bit[1]: digital_gain_en 0x3320 AWB 0x82 RW Bit[3]: Bit[7:0]: default value R/W description dg_man_en (functions only when register 0x3301[1] = 1) 0: dig_gain auto mode 1: dig_gain manual mode dg_gain[7:0] Manual digital gain Digital gain =(Bit[7]+1)*(Bit[6]+1) + Bit[5:0]/64 ISP Enable Control 00 - corresponding clock will be stopped if one module is disabled (0: disable; 1: enable) Bit[6]: AWB_stat_en Bit[5]: AWB_gain_en Bit[7]: Bit[6]: Bit[5:0]: fast_awb Fast AWB awb_man_en awb_delta AWB gain adjustment step proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

61 5-5 table 5-4 AWB control registers (sheet 2 of 2) default address register name value R/W description 0x3321 AWB 0x04 RW Bit[7:0]: stable_range[7:0] Threshold from unstable to stable Bit[7:0]: stable_rangew[7:0] 0x3322 AWB 0x08 RW Threshold from stable to unstable. This should be greater than stable_range. 0x3323 AWB 0x00 RW Bit[7:0]: AWB_frame_cnt[7:0] Change AWB gain speed 0x3324 AWB 0x40 RW Bit[7:0]: Manual WB_R_gain[11:4] 0x3325 AWB 0x40 RW Bit[7:0]: Manual WB_G_gain[11:4] 0x3326 AWB 0x40 RW Bit[7:0]: Manual WB_B_gain[11:4] 0x3327 AWB 0x00 RW Bit[7:4]: Bit[3:0]: Bit[7]: Bit[6]: 0x3328 AWB 0x00 RW Bit[5:4]: Bit[3:0]: Manual WB_R_gain[3:0] Manual WB_G_gain[3:0] AWB_freeze_en AWB_sel 0: From VarioPixel 1: From AWB_gain Reserved Manual WB_B_gain[3:0] Indirect mapping for auto white balance parameter generated by AWB block. Set register 0x330E for below address and read out from register 0x330F for the value. 0x07 R_avg[9:2] 0x08 G_avg[9:2] 0x09 B_avg[9:2] 0x0A {2'b0, R_avg[1:0], G_avg[1:0], B_avg[1:0]} 0x0B AWB_R_gain[11:4] 0x0C AWB_G_gain[11:4] 0x0D AWB_B_gain[11:4] 0x0E {4'b0, AWB_R_gain[3:0]} 0x0F {4'b0, AWB_G_gain[3:0]} 0x10 {4'b0, AWB_B_gain[3:0]} PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

62 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 5.5 WBC This module does white/black pixel cancellation. It has two working modes: auto mode - white, black (thresholds for white/black pixel detection) and detail_en are automatically calculated according to the input sensor gain manual mode - white, black and detail_en are set manually table 5-5 WBC control registers (sheet 1 of 2) address register name 0x3300 TOP 0xFF RW 0x330A WBC 0x3F RW 0x330B WBC 0x20 RW 0x330C WBC 0x40 RW 0x330D WBC 0x30 RW default value R/W description ISP Enable Control 00 - corresponding clock will be stopped if one module is disabled (0: disable; 1: enable) Bit[3]: WC_en (white pixel cancellation) Bit[2]: BC_en (black pixel cancellation) Bit[7:6]: Bit[5:4]: Reserved wbc_bd_sel[1:0] Boundary select options wbc_se_en Enable same channel detection wbc_dc_en Enable different channel detection wbc_smooth_en Enable using average G values when doing recovery wbc_detail_en Enable detail detection method 0x332A WBC 0x20 RW Bit[3]: Bit[2]: Bit[1]: Bit[0]: Bit[7]: Bit[6:0]: Bit[7:0]: Bit[7:0]: Debug mode wbc_wthre[6:0] Threshold value for detecting white pixels wbc_bthre[7:0] Threshold value for detecting black pixels wbc_thre[7:0] Threshold value used in recovery Bit[7]: WBC_man Enable manual mode in which wthre, bthre, and detail_en can be set manually Bit[6:0]: wbc_wthre[6:0] Reference threshold when determining wthre in auto mode proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

63 5-7 table 5-5 WBC control registers (sheet 2 of 2) default address register name value R/W description Bit[7]: WBC_gain_man_en Bit[6:4]: WBC_refgain_pwr[2:0] 0x332B WBC 0x31 RW Range: 0~5 Bit[2:0]: WBC_shift[2:0] Range: 0~7 Bit[2:0]: 0x332C WBC 0x03 RW WBC_gainbd_pwr[2:0] Range: 0~5 0x332D WBC 0x02 RW Bit[7:0]: WBC_gain_man[7:0] Bit[7]: 0x3329 WBC RW Bit[6]: Bit[5]: Remove cross cluster option enable Remove tail option enable Anti-artifact option enable PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

64 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 5.6 VarioPixel In the horizontal direction, VarioPixel has 1/2 drop, 3/4 drop, or average mode. In the vertical direction, it has only 1/2 or 3/4 drop mode. table 5-6 VarioPixel control registers (sheet 1 of 2) address register name default value R/W description Bit[5]: RISPsubV Disable V subsample in sensor Bit[4]: RISPsub Disable H subsample in sensor Bit[3:2]: VSUB 00: Full 01: 1:2 10: 1:4 11 1:8 0x30F8 IMAGE_TRANSFORM 0x00 RW Bit[1:0]: HSUB 00: Full 01: 1:2 10: 1:4 11: 1:8 Note: H subsample can be implemented in ARRAY and ISP depending on the value of RISPsub V subsample is performed in ARRAY only 0x3091 R_ARRAY 0x00 RW 0x3301 TOP 0x08 RW Bit[7:6]: Array binning control 00: Horizontal sum 01: Not allowed 10: Not allowed 11: Horizontal 2:1 skip ISP Enable Control 01 - corresponding clock will be stopped if one module is disabled Bit[2]: vario_pixel_en proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

65 5-9 table 5-6 VarioPixel control registers (sheet 2 of 2) default address register name value R/W description Bit[5:4]: Bit[3:2]: 0x33E5 VAP 0x00 RW Bit[1:0]: vap_addopt[1:0] VarioPixel option Manual gain enable vap_vskip[1:0] Vertical skip 00: 1:1 01: 1:2 10: 1:4 11: 1:1 vap_hskip[1:0] Horizontal skip 00: 1:1 01: 1:2 10: 1:4 11: 1:1 0x33E6 VAP 0x00 RW Bit[3:0]: vap_avg_eb[3:0] Average enable VAP_H_mode[7:0] Bit[7:6]: B_mode[1:0] 00: Average 01: Drop second 1x: Drop first Bit[5:4]: Gb_mode[1:0] 00: Average 01: Drop second 0x3700 VAP_H 0x00 RW 1x: Drop first Bit[3:2]: Gr_mode[1:0] 00: Average 01: Drop second 1x: Drop first Bit[1:0]: R_mode[1:0] 00: Average 01: Drop second 1x: Drop first PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

66 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 5.7 frame average This module outputs R, G, and B average values of each frame. The module has the option to calculate the average from the output of different modules (can select from BLC, LENC, AWB_gain, or WBC output for frame average). table 5-7 address frame average control registers register name 0x3301 TOP 0x08 RW 0x331C~ 0x331F AVG RW default value R/W description ISP Enable Control 01 - corresponding clock will be stopped if one module is disabled Bit[3]: frame_average_en Frame Average Control Avg_xstart[11:0] = {Reg0x331C[7:0], 4'b0} Avg_ystart[11:0] = {Reg0x331D[7:0], 4'b0} Avg_width[11:0] = {Reg0x331E[7:0], 4'b0} Avg_height[11:0] = {Reg0x331F[7:0], 4'b0} proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

67 6-1 6 image sensor output interface digital functions 6.1 digital video port (DVP) overview The Digital Video Port (DVP) provides 12-bit, 10-bit and 8-bit parallel data output in all formats supported and extended features including HREF, CCIR656 format, HSYNC mode and test pattern output HSYNC mode In this mode, the line blanking time and VSYNC to the first image line are fixed. Also, there are dummy lines when vertical blanking. To enable HSYNC mode, the user only needs to write 0x30 to register 0x3506. figure 6-1 DVP_VSYNC DPV_HREF (HREF mode) DVP_HREF (HSYNC mode) DVP_DATA DPV_PCLK tip DVP timing diagram pad left eof2v_dly pad right vertical blanking dummy lines vsync_width 3264 x tp row 2446 row 2447 dummy datas row 0 row 1 note: 1. DVP_PCLK can be optional gated when DVP_HREF is low. 2. polarity of DVP_VSINC, DVP_HREF, DVP_PCLK can be switched separately _DS_6_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

68 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 6-1 DVP timing note The timing values shown in figure 6-1 may vary depending upon register settings. symbol parameter registers typ unit Tp PCLK period 10.4 ns eof2v_dly a v2h_dly a h2v_dly a a. eof2v_dly, vsync_width, h2v_dly, and v2h_dly are variables for different VSYNC modes three modes of VSYNC output The OV8810 supports three different VSYNC output timing modes, vsync_old, vsync_new, and vsync_three. vsync_three is the default output mode. figure 6-2 describes the three VSYNC timing modes and table 6-2 are the relative registers of VSYNC. figure 6-2 PCLK numbers from the last HREF falling edge to VSYNC rising edge of the next frame in VSYNC_THREE mode PCLK numbers from VSYNC falling edge to the first HREF rising edge PCLK from the last HREF falling edge to VSYNC rising edge of the next frame in VSYNC_NEW mode VSYNC output timing {0x3509, 0x350A, 0x350B} 0x tp 0x tp pad_right dummy pixel numbers at the end of a line 0x350C 0 tp pad_left vysnc_width a DVP_HREF (HSYNC mode) VSYNC_OLD (DVP_CTRL00[7:6] = 00) VSYNC_NEW (DVP_CTRL00[7:6] = 01) dummy pixel numbers at the beginning of a line PCLK numbers of VSYNC 0x350D 0 tp {0x350E[5:4], 0x3507[7:1], 5 h0} VSYNC_THREE (DVP_CTRL00[7:6] = 10) h2v_dly eofd_dly vsync_width v2h_dly tp 8810_DS_6_2 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

69 6-3 table 6-2 DVP VSYNC settings default mode control mode timing control registers value vsync_old 0x3500[7:6] = 2 h0 vsync_width {0x350E[5:4], 0x3507[7:1], 5 h0} 2048 vsync_new 0x3500[7:6] = 2 h1 vsync_three 0x3500[7:6] = 2 h2 h2v_dly 0x v2h_dly 0x eof2v_dly {0x3509, 0x350A, 0x350B} 256 vsync_width {0x350E[5:4], 0x3507[7:1], 5 h0} DVP control registers The OV8810 supports DVP and MIPI on simultaneously. To reduce power consumption in MIPI output mode, DVP port can be disabled by setting register 0x3100 to 0x88 and register 0x3101 to 0x77 to reset DVP and disable DVP clock table 6-3 DVP control registers (sheet 1 of 4) address register name default value R/W description System Reset Enable (0: disable; 1: enable) Bit[7]: DVP SCLK reset 0x3100 SYS_RST 0x00 RW Bit[3]: DVP PCLK reset Bit[2]: MIPI PCLK reset Bit[1]: MIPI SCLK reset Bit[0]: ISP reset System Clock Enable (0: disable; 1: enable) Bit[7]: DVP SCLK clock enable 0x3101 CLOCK_EN 0xFF RW Bit[3]: DVP PCLK clock enable Bit[2]: MIPI PCLK clock enable Bit[1]: MIPI SCLK clock enable Bit[0]: ISP clock enable PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

70 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 6-3 DVP control registers (sheet 2 of 4) address register name 0x3500 DVP_CTRL00 0x80 RW 0x3501 DVP_CTRL01 0x00 RW DVP Control 00 Bit[7:6]: VSYNC select 00: Select vsync_old 01: Select vsync_new 10: Select vsync_three 11: Reserved Bit[5]: pclk_gate_en 1: Gate dvp_pclk when HREF is low Bit[4]: vsync_gate 0: Do not gate dvp_pclk when VSYNC is high 1: Gate dvp_pclk when VSYNC and pclk_gate_en is high Bit[3]: Reserved Bit[2]: Change polarity of PCLK Bit[1]: Change polarity of HREF Bit[0]: Change polarity of VSYNC DVP Control 01 Bit[7]: ccir656_en Bit[6]: sync_code_sel 0: Auto generate sync_code 1: Use FS, FE, LS and LE as ccir656 sync_code Bit[5]: Reserved Bit[4]: data_order 0: DVP output dvp_data[11:0] 1: DVP output dvp_data[0:11] Bit[3]: dvp_bit8 0: Swap 2 bit when dvp_h and dvp_l 1: Swap 4 bit Bit[2]: dvp_h 0: Output dvp_data[11:0] 1: Output dvp_data{n:0, 11:n-1} n: 7 or 9 Bit[1]: dvp_l 0: Select dvp_data[11:0] 1: Select dvp_data{n:0, 11:n+1} n: 3 or 1 Bit[0]: ch_flag Write 1 to it to generate flag for HSYNC mode 0x3502 DVP_CTRL02 0xAB RW default value R/W description DVP Control 02 Bit[7:0]: CCIR656 sync code for FS 0x3503 DVP_CTRL03 0xB6 RW DVP Control 03 Bit[7:0]: CCIR656 sync code for FE proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

71 6-5 table 6-3 DVP control registers (sheet 3 of 4) default address register name value R/W description 0x3504 DVP_CTRL04 0x80 RW 0x3505 DVP_CTRL05 0x9D RW 0x3506 DVP_CTRL06 0x20 RW 0x3507 DVP_CTRL07 0x80 RW DVP Control 04 Bit[7:0]: CCIR656 sync code for LS DVP Control 05 Bit[7:0]: CCIR656 sync code for LE DVP Control 06 Bit[7:6]: Reserved Bit[5]: dvp_en Bit[4]: hsync_en Bit[3:0]: Reserved DVP Control 07 Bit[7:1]: vsync_width[7:1] Width of VSYNC when selecting vsync_old and vsync_three Bit[0]: hskip_man_o[0] DVP Control 08 Bit[7]: tst_ptn_en Bit[6]: tst_bit8 0x3508 DVP_CTRL08 0x00 RW Bit[5]: tst_bit12 Bit[4]: tst_mode 0: 00, 01, 02,..., 80, FF 1: 00, 00, 01, 01,..., FF, FF Bit[3:0]: dmy_line_nu 0x3509 DVP_CTRL09 0x00 RW DVP Control 09 Bit[7:0]: eof2v_dly[23:16] 0x350A DVP_CTRL0A 0x01 RW 0x350B DVP_CTRL0B 0x00 RW 0x350C DVP_CTRL0C 0x00 RW 0x350D DVP_CTRL0D 0x00 RW 0x350E DVP_CTRL0E 0x40 RW DVP Control 0A Bit[7:0]: eof2v_dly[15:8] DVP Control 0B Bit[7:0]: eof2v_dly[7:0] DVP Control 0C Bit[7:0]: pad_right DVP Control 0D Bit[7:0]: pad_left DVP Control 0E Bit[7:6]: Reserved Bit[5:4]: vsync_width[9:8] Bit[3:1]: Reserved Bit[0]: skip_man_en_o PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

72 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 6-3 DVP control registers (sheet 4 of 4) address register name 0x350F DVP_CTRL0F 0x88 RW 0x3510 DVP_CTRL10 0x09 RW 0x3511 DVP_CTRL11 0xAA RW 0x3512 DVP_CTRL12 0x55 RW DVP Control 0F Bit[7]: eav_first 0: sav_first 1: eav_first Bit[6]: f_sel Bit[5]: f_value Bit[4]: fix_f 0: Auto generate ccir_f 1: Use f_value as ccir_f Bit[3:2]: blk_sel 00: Select 12 h800 and 12 h100 as toggle data x1: Selet 12 h000 as toggle data 10: Select tog0 and tog1 as toggle data Bit[1]: no_sof 0: Reset state machine at SOF 1: Do not reset state machine at SOF Bit[0]: no_clip 0: Clip output data between 10 h004 and 10 h3fb 1: Do not clip output data when in CCIR656 mode DVP Control 10 Bit[7:4]: Reserved Bit[3:2]: tog0[11:10] Toggle data0 when line blanking or dummy lines Bit[1:0]: tog1[11:10] Toggle data1 when line blanking or dummy lines DVP Control 11 Bit[7:0]: tog0[9:2] - toggle data0 when line blanking or dummy lines DVP Control 12 Bit[7:0]: tog1[9:2] Toggle data1 when line blanking or dummy lines 0x3513 DVP_CTRL13 0x02 RW 0x3514 DVP_CTRL14 0x00 RW default value R/W description DVP Control 13 Bit[7:0]: Reserved DVP Control 14 Bit[7:0]: h2v_dly 0x3515 DVP_CTRL15 0x00 RW DVP Control 15 Bit[7:0]: v2h_dly proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

73 mobile industry processor interface (MIPI) The MIPI interface fully supports the MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) and the MIPI Alliance Specification for D-PHY. The MIPI interface provides a single uni-directional clock lane and two bi-directional data lane solution for communication links between components inside a mobile device. The two data lanes fully support the HS (uni-direction) and LP (bi-direction) data transfer modes normal high speed mode The default is to use two lanes to output HS data with a free running clock lane. The user only needs to set pclk_period (0x3610), which is the pixel clock period of MIPI_TOP. It will affect the global timing of MIPI_DPHY_spec. The default value is 8 ns (one bit decimal) HOST single write registers sequenced through ESCAPE mode HOST: 0xE1 0x69 addr_h adddr_l wdata0 addr_h addr_l wdata1... Mark1 LP11 All ESCAPE modes are high bit first. And since the OV8810 will go to TX mode after power on, the user should send a sequence to make sure CD can be detected. For example, HOST can send a start and then a stop before sending the valid command HOST sequence write registers sequenced through ESCAPE mode HOST: 0xE1 0x68 addr_h addr_l wdata_0 wdata_1... wdata_n Mark1 LP HOST sequence read registers sequenced through ESCAPE mode HOST: 0XE1 0x6A addr_h addr_l byte_h byte_l Mark1 LP11 turnaround OV8810: 0xE1 0x6B addr_h addr_l rdata_0 rdata_ MIPI control registers table 6-4 MIPI control registers (sheet 1 of 7) address register name default value R/W description Bit[2:0]: 0x300E R_PLL1 0x05 RW Bit[3:2]: 0x300F R_PLL_2 0x04 RW PLL control 0xx: /1 100: /4 (RAW8) 101: /5 (RAW10) 110: /6 (RAW12) PLL control 01: Use two lanes to transmit HS data 10: Use one lane to transmit HS data PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

74 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 6-4 MIPI control registers (sheet 2 of 7) default address register name value R/W description 0x3600 MIPI_CTRL00 0x00 RW 0x3601 MIPI_CTRL01 0x10 RW MIPI Control 00 Bit[7]: lp_p1_out Bit[6]: lp_n1_out Bit[5]: lp_p2_out Bit[4]: lp_n2_out Bit[3]: lp_sel1 0: Auto generate lp_dir1 1: Use lp_dir_man1 as lp_dir1 Bit[2]: lp_sel2 0: Auto generate lp_dir2 1: Use lp_dir_man2 as lp_dir2 Bit[1]: lp_dir_man1 0: Input 1: Output Bit[0]: lp_dir_man2 0: Input 1: Output MIPI Control 01 Bit[7]: Reserved Bit[6]: line_sync_en 1: Enable line sync short packet Bit[5]: lane_sel 0: Use lane1 as default data lane 1: Select lane 2 as default data lane Bit[4]: lp_tx_lane_sel 0: Select lane1 as lp_tx_lane 1: Select lane2 as lp_tx_lane Bit[3]: Reserved Bit[2]: ph_byte_order2 PH sequence for ECC calculation 0: {DI, WC} 1: {WC, DI} Bit[1]: ph_byte_order PH sequence for ECC calculation 0: {WC_l, WC_h} 1: {WC_h, WC_l} Bit[0]: ph_bit_order 0: DI[7:0], WC[7:0], WC[15:8] 1: DI[0:7], WC[0:7], WC[8:15] MIPI Control 02 Bit[7:6]: VC 0x3602 MIPI_CTRL02 0x12 RW Virtual channel ID Bit[5:0]: dt_dmy Data type for dummy lines 0x3603 MIPI_CTRL03 0x2A RW MIPI Control 03 Bit[7:6]: Reserved Bit[5:0]: dt_man Manually set data type proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

75 6-9 table 6-4 MIPI control registers (sheet 3 of 7) address 0x3604 MIPI_CTRL04 0x58 RW 0x3605 MIPI_CTRL05 0x00 RW 0x3606 MIPI_CTRL06 0x00 RW 0x3607 MIPI_CTRL07 0x68 RW 0x3608~ 0x3609 register name RSVD Reserved 0x360A MIPI_CTRL0A 0x01 RW 0x360B MIPI_CTRL0B 0x3C RW default value R/W description MIPI Control 04 Bit[7:3]: Reserved Bit[2]: spkt_dt_sel 1: Use dt_dmy as short packet Bit[1]: lpkt_dt_sel 0: Use dt_auto 1: Use dt_man as long packet Bit[0]: spkt_wc_sel 1: Select spkt_wc_reg as short packet wc MIPI Control 05 Bit[7:0]: High byte of spkt_wc_reg[15:8] MIPI Control 06 Bit[7:0]: Low byte of spkt_wc_reg[7:0] MIPI Control 07 Bit[7]: Reserved Bit[6]: ta_en Enable send turnaround command after read data transmission is finished Bit[0]: Reserved MIPI Control 0A Bit[7]: Reserved Bit[6]: gate_sc_en 0: Clock is in free running mode 1: Gate MIPI clock when there is no packet Bit[5:0]: Reserved MIPI Control 0B Bit[7]: cd1_int_en 1: Enable internal cd1 enable Bit[6]: cd2_int_en 1: Enable internal cd2 enable Bit[5]: lp_cd_en1 1: Enable LP CD detection on lane1 Bit[4]: lp_cd_en2 1: Enable LP CD detection on lane2 Bit[3:2]: Reserved Bit[1]: lane_disable1 1: Disable MIPI data lane1 to LP00 state Bit[0]: lane_disable2 1: Disable MIPI data lane2 to LP00 state PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

76 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 6-4 MIPI control registers (sheet 4 of 7) address register name 0x360C MIPI_CTRL0C 0x03 RW 0x360D RSVD Reserved 0x360E MIPI_CTRL0E 0x02 RW 0x360F RSVD Reserved 0x3610 MIPI_CTRL10 0x10 RW 0x3611 MIPI_CTRL11 0x4F RW default value R/W description 0x3612 RSVD Reserved MIPI Control 0C Bit[7:2]: Reserved Bit[1]: inc_en 1: mipi_reg_addr will auto increment by 1 Bit[0]: Reserved MIPI Control 0E Bit[7]: lpx_p_sel 0: Select lpx_p_cal 1: Select lpx_p_reg[7:0] as t_lpx_p Bit[6]: Reserved Bit[5:0]: wkup_dly 1 ms wakeup delay/4096 for MIPI ultra low power resume MIPI Control 10 Bit[7:0]: pclk_period pclk2x period, 1-bit decimal, unit ns MIPI Control 11 Bit[7:4]: T_lpx SCLK domain Bit[3:0]: T_clk_pre unit pclk2x cycle proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

77 6-11 table 6-4 MIPI control registers (sheet 5 of 7) address register name 0x3613 MIPI_CTRL13 0x00 RW 0x3614 MIPI_CTRL14 0x28 RW 0x3615 MIPI_CTRL15 0x96 RW 0x3616 MIPI_CTRL16 0x10 RW MIPI Control 13 - MIPI Timing Register Select (0: auto calculated parameter, relate to register 0x3622 to 0x3637; 1: use low byte of parameter) Bit[7]: clk_zero_sel 0: Auto calculate t_clk_zero 1: Use t_clk_zero_reg Bit[6]: hs_trail_sel 0: Auto calculate t_hs_trail 1: Use t_hs_trail_reg Bit[5]: hs_zero_sel 0: Auto calculate t_hs_zero 1: Use t_hs_zero_reg Bit[4]: hs_exit_sel 0: Auto calculate t_hs_exit 1: Use t_hs_exit_reg Bit[3]: clk_trail_sel 0: Auto calculate t_clk_trail 1: Use t_clk_trail_reg Bit[2]: clk_post_sel 0: Auto calculate t_clk_post 1: Use t_clk_post_reg Bit[1]: clk_prepare_sel 0: Auto calculate t_clk_prepare 1: Use t_clk_prepare_reg Bit[0]: hs_prepare_sel 0: Auto calculate t_hs_prepare 1: Use t_hs_prepare_reg MIPI Control 14 Bit[7:2]: N UI for t_hs_zero Minimum high speed zero Bit[1:0]: Min_hs_zero_high[9:8] Unit is pclk2x cycles when hs_zero_sel = 1 and unit is ns when hs_zero_sel = 0 MIPI Control 15 Bit[7:0]: Min_hs_zero_low[7:0] MIPI Control 16 Bit[7:2]: N UI for t_hs_trail Minimum high speed trail Bit[1:0]: Min_hs_trail_high[9:8] Unit is pclk2x cycles when hs_trail_sel = 1 and ns when hs_trail_sel = 0 0x3617 MIPI_CTRL17 0x3C RW default value R/W description MIPI Control 17 Bit[7:0]: Min_hs_trail_low[7:0] PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

78 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 6-4 MIPI control registers (sheet 6 of 7) address register name 0x3618 MIPI_CTRL18 0x01 RW 0x3619 MIPI_CTRL19 0x86 RW 0x361A MIPI_CTRL1A 0x00 RW 0x361B MIPI_CTRL1B 0x32 RW 0x361C MIPI_CTRL1C 0x00 RW 0x361D MIPI_CTRL1D 0x8C RW 0x361E MIPI_CTRL1E 0xD0 RW 0x361F MIPI_CTRL1F 0x56 RW 0x3620 MIPI_CTRL20 0x08 RW MIPI Control 18 Bit[7:2]: N UI for t_clk_zero Minimum clock zero Bit[1:0]: Min_clk_zero_high[9:8] Unit is pclk2x cycles when clk_zero_sel = 1 and ns when clk_zero_sel = 0 MIPI Control 19 Bit[7:0]: Min_clk_zero_low[7:0] MIPI Control 1A Bit[7:2]: N UI for min_clk_pre Minimum clock prepare time Bit[1:0]: Min_clk_pre_high[9:8] Unit is pclk2x cycles when clk_prepare_sel = 1 and ns when clk_prepare_sel = 0 MIPI Control 1B Bit[7:0]: Min_clk_pre_low[7:0] MIPI Control 1C Bit[7:2]: N UI for max_clk_pre Maximum clock prepare time Bit[1:0]: Max_clk_pre_high[9:8] Unit is ns MIPI Control 1D Bit[7:0]: Max_clk_pre_low[7:0] MIPI Control 1E Bit[7:2]: N UI for min_clk_post Minimum clock post time Bit[1:0]: Min_clk_post_high[9:8] Unit is pclk2x cycles when clk_post_sel = 1 and ns when clk_post_sel = 0 MIPI Control 1F Bit[7:0]: Min_clk_post_low[9:8] MIPI Control 20 Bit[7:2]: N UI for min_clk_trail Minimum clock trail Bit[1:0]: Min_clk_trail_high[9:8] Unit is pclk2x cycles when clk_trail_sel = 1 and ns when clk_trail_sel = 0 0x3621 MIPI_CTRL21 0x3C RW default value R/W description MIPI Control 21 Bit[7:0]: Min_clk_trail_low[7:0] proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

79 6-13 table 6-4 MIPI control registers (sheet 7 of 7) address 0x3622 MIPI_CTRL22 0x00 RW 0x3623 MIPI_CTRL23 0x32 RW 0x3624 MIPI_CTRL24 0x10 RW 0x3625 MIPI_CTRL25 0x2A RW 0x3626 MIPI_CTRL26 0x18 RW 0x3627 MIPI_CTRL27 0x55 RW 0x3628 MIPI_CTRL28 0x00 RW 0x3629 MIPI_CTRL29 0x64 RW 0x362A~ 0362D register name DEBUG MODE Debug Mode 0x362E MIPI_CTRL2E 0x06 RW 0x362F MIPI_CTRL2F 0x08 RW 0x3630 MIPI_CTRL30 0x14 RW default value R/W description MIPI Control 22 Bit[7:2]: N UI for min_lpx_p Bit[1:0]: Min_lpx_p_high[9:8] Unit is pclk2x cycles when lpx_p_sel = 1 and ns when lpx_p_sel = 0 MIPI Control 23 Bit[7:0]: Min_lpx_p_low[7:0] MIPI Control 24 Bit[7:2]: N UI for min_hs_prepare Bit[1:0]: Min_hs_prepare_high[9:8] Unit is pclk2x cycles when hs_prepare_sel = 1 and ns when hs_prepare_sel = 0 MIPI Control 25 Bit[7:0]: Min_hs_prepare_low[7:0] MIPI Control 26 Bit[7:2]: N UI for max_hs_prepare Bit[1:0]: Max_hs_prepare_high[9:8] Unit is ns MIPI Control 27 Bit[7:0]: Max_hs_prepare_low[7:0] MIPI Control 28 Bit[7:2]: N UI for min_hs_exit Bit[1:0]: Min_hs_exit_high[9:8] Unit is pclk2x cycles when hs_exit_sel = 1 and ns when hs_exit_sel = 0 MIPI Control 29 Bit[7:0]: Max_hs_exit_low[7:0] MIPI Control 2E Bit[7:0]: t_ta_go MIPI Control 2F Bit[7:0]: t_ta_sure MIPI Control 30 Bit[7:0]: t_ta_get PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

80 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

81 7-1 7 register tables The following tables provide descriptions of the device control registers contained in the OV8810. For all registers enable/disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 0x6C for write and 0x6D for read. table 7-1 system control registers (sheet 1 of 14) address register name 0x3000 AGCL 0x00 RW default value R/W description 0x3001 NOT USED Not Used 0x3002 AECL 0x00 RW 0x3003 AECL 0x08 RW 0x3004 LAEC 0x20 RW 0x3005 LAEC 0x40 RW 0x3006 AGC 0x40 RW 0x3007~ 0x3009 Sensor Gain Auto or Manual Gain = (Bit[6]+1) * (Bit[5]+1) * (Bit[4]+1) * (Bit[3:0]/16+1) Coarse Exposure Time Auto or Manual Byte: High Units: Lines Coarse Exposure Time Auto or Manual Byte: Low Units: Lines Fine Exposure Time Auto or Manual Units: System clocks Fine Exposure Time Auto or Manual Units: System clocks Bit[7:2]: Bit[1:0]: NOT USED Not Used 0x300A PIDH 0x88 R 0x300B PIDL 0x1x R ID Byte: ID Byte: 0x300C SCCB_ID 0x6C RW SCCB_ID 0x300D R_PLL 0x00 RW Debug mode High gain High Low PLL Analog Control Bit[7:3]: Debug mode Bit[2:0]: PLL charge pump current control PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

82 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-1 system control registers (sheet 2 of 14) address register name 0x300E R_PLL1 0x05 RW 0x300F R_PLL2 0x04 RW 0x3010 R_PLL3 0x32 RW 0x3011 R_PLL4 0x21 RW 0x3012 SYS 0x00 RW default value R/W description Bit[7:4]: Bit[3]: Bit[2:0]: Bit[7:4]: Bit[3:0]: Bit[7]: Bit[6:0]: Bit[7:6]: Bit[5:4]: Bit[3:0]: VT_SYS_DIV 000x: 1 001x: 2 01xx: 4 1xxx: 8 Debug mode DIV[8] 0xx: 1 100: 4 101: 5 110: 6 111: Debug mode OP_SYS_DIV / MIPI system clock divider 000x: 1 001x: 2 01xx: 4 1xxx: 8 OP_PIX_DIV / MIPI PCLK divider 000x: 1 001x: 2 01xx: 4 1xxx: 8 Debug mode PLL multiplier Debug Debug option PRE-DIVIDER 000x: 1 001x: 2 01xx: 4 1xxx: 8 System Control Bit[7]: Software system reset Bit[6:0]: Debug mode proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

83 7-3 table 7-1 system control registers (sheet 3 of 14) default address register name value R/W description Bit[7]: Bit[6]: Bit[5]: Bit[4]: 0x3013 AUTO_1 0x00 RW Bit[3]: Bit[2]: Bit[0]: AEC speed select 0: Standard 1: Fast AEC big step enable 0: Disable 1: Enable Banding filter enable 0: OFF 1: ON Auto banding enable (turn odd banding automatically when it is too bright) 0: OFF 1: ON LAEC enable 0: OFF 1: ON AGC enable 0: Manual 1: Auto AEC enable 0: Manual 1: Auto Bit[7]: Manual 50/60Hz selection 0: 60Hz 1: 50Hz Bit[6]: 50/60Hz auto detection enable 0: OFF 0x3014 AUTO_2 0x00 RW 1: ON Bit[3]: VAEC enable 0: OFF 1: ON Bit[1]: Manual LAEC enable 0: Auto mode 1: Manual mode PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

84 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-1 system control registers (sheet 4 of 14) address 0x3015 AUTO_3 0x33 RW 0x3016~ 0x3017 register name Bit[7]: Bit[6:4]: Bit[3]: Bit[2:0]: DEBUG MODE Debug Mode 0x3018 WPT 0x78 RW 0x3019 BPT 0x68 RW 0x301A VPT 0xD4 RW 0x301B YAVG R 0x301C AECG_MAX50 0x05 RW Debug mode VAEC ceiling 000: 1 frame 001: 1.5frame 010: 2 frames 011: 3 frames 100: 4 frames 101: 6 frames 110: 8 frames 111: 12 frames Debug mode Gain ceiling 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x :Debug mode Luminance Signal/Histogram High Range for AEC/AGC operation Luminance Signal/Histogram Low Range for AEC/AGC operation Fast Mode Large Step Range Thresholds - effective only in AEC/AGC fast mode Bit[7:4]: High threshold Bit[3:0]: Low threshold Luminance Average - this register will auto update Average luminance is calculated from the B/Gb/Gr/R channel average as follows: B/Gb/Gr/R channel average = (BAVG[7:0] + GbAVG[7:0] + GrAVG[7:0] + RAVG[7:0]) Hz Smooth Banding Maximum Steps Control Bit[7:6]: Debug mode Bit[5:0]: 50 Hz smooth banding maximum steps 0x301D AECG_MAX60 0x07 RW default value R/W description 60 Hz Smooth Banding Maximum Steps Control Bit[7:6]: Debug mode Bit[5:0]: 60 Hz smooth banding maximum steps proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

85 7-5 table 7-1 system control registers (sheet 5 of 14) default address register name value R/W description Extra VSYNC Pulse Width 0x301E ADDVS 0x00 RW Byte: High Units: Lines Extra VSYNC Pulse Width 0x301F ADDVS 0x00 RW Byte: Low Units: Lines 0x3020 0x3021 FRAME_LENGTH_ LINES FRAME_LENGTH_ LINES 0x07 0xBC RW RW Frame Length Byte: High Units: Lines Frame Length Byte: Low Units: Lines 0x3022 LINE_LENGTH_PCK 0x0C RW Line Length Byte: High Units: System clocks 0x3023 LINE_LENGTH_PCK 0xA0 RW Line Length Byte: Low Units: System clocks 0x3024 X_ADDR_START 0x00 RW X Address of the Top Left Corner of the Visible Pixel Byte: High Units: Pixels 0x3025 X_ADDR_START 0x00 RW X Address of the Top Left Corner of the Visible Pixel Byte: High Units: Pixels 0x3026 Y_ADDR_START 0x00 RW Y Address of the Top Left Corner of the Visible Pixel Byte: High Units: Lines 0x3027 Y_ADDR_START 0x00 RW Y Address of the Top Left Corner of the Visible Pixel Byte: High Units: Lines 0x3028 X_ADDR_END 0x0A RW X Address of the Bottom Right Corner of the Visible Pixel Byte: High Units: Pixels 0x3029 X_ADDR_END 0x1F RW X Address of the Bottom Right Corner of the Visible Pixel Byte: High Units: Pixels PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

86 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-1 system control registers (sheet 6 of 14) address register name 0x302A Y_ADDR_END 0x07 RW 0x302B Y_ADDR_END 0x97 RW 0x302C X_OUTPUT_SIZE 0x0A RW 0x302D X_OUTPUT_SIZE 0x20 RW 0x302E Y_OUTPUT_SIZE 0x07 RW 0x302F Y_OUTPUT_SIZE 0x98 RW 0x3030~ 0x303B DEBUG MODE Debug Mode 0x303C DATR_D56 R 5060 Register 0x303E DATR_OTP 0x00 RW 0x304C R_SIGMA 0x09 RW 0x305C BD50ST 0x00 RW 0x305D BD50ST 0x55 RW Y Address of the Bottom Right Corner of the Visible Pixel Byte: High Units: Lines Y Address of the Bottom Right Corner of the Visible Pixel Byte: High Units: Lines Width of Image Data Output from Sensor Byte: High Units: Pixels Width of Image Data Output from Sensor Byte: Low Units: Pixels Height of Image Data Output from Sensor Byte: High Units: Lines Height of Image Data Output from Sensor Byte: Low Units: Lines OTP Register 0xAA: Program OTP 0x55: Read OTP Bit[7:5]: Debug mode Bit[4:0]: Indirect subaddress to read 5060 status Bit[7:2]: Bit[1:0]: Bit[7:0]: Debug mode Band step for 50Hz Byte: High Unit: Lines Band step for 50Hz Byte: Low Unit: Lines 0x305E BD60ST 0x55 RW default value R/W description Bit[7:2]: Bit[1:0]: Debug mode Band step for 60Hz Byte: High Unit: Lines proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

87 7-7 table 7-1 system control registers (sheet 7 of 14) default address register name value R/W description Bit[7:0]: Band step for 60Hz 0x305F BD60ST 0x01 RW Byte: Low Unit: Lines Bit[7]: BLC freeze enable 0: BLC updating enable 1: Freeze current BLC value Bit[4]: BLC trig option 0: BLC keep adjusting every frame 1: BLC trig by Gain change 0x3071 TMC 0xF0 RW Bit[3:2]: BLC reset frame counter (functions only when Bit[4] = 1, if no more Gain change, number of frames to be reset before BLC freeze) 00: 1 frame 01: 64 frames 10: 4 frames 11: 2 frames 0x3075 TMC 0x25 RW 0x3076 TMC 0x24 RW Horizontal Window Initialized Address (MIRROR OFF mode) Horizontal Window Initialized Address (MIRROR ON mode) 0x3077 TMC 0x25 RW Horizontal window initialized address in Subsample Mode (MIRROR OFF mode) 0x3078 TMC 0x25 RW Horizontal Window Initialized Address in Subsample Mode (MIRROR ON mode) 0x3079 TMC 0x0A RW Vertical Reference Start Lines PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

88 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-1 system control registers (sheet 8 of 14) address register name 0x307E TMC 0x00 RW default value R/W description Bit[7:5]: Debug mode Bit [4:0]: x address bank select, 0x1F following value should be written to Bit[4:0] when MIRROR ON. 0x00: Array bank 0 x_address x01: Array bank 1 x_address x02: Array bank 2 x_address x03: Array bank 3 x_address x04: Array bank 4 x_address x05: Array bank 5 x_address x06: Array bank 6 x_address x07: Array bank 7 x_address x08: Array bank 8 x_address x09: Array bank 9 x_address x0A: Array bank A x_address x0B: Array bank B x_address x0C: Array bank C x_address x0D: Array bank D x_address x0E: Array bank E x_address x0F: Array bank F x_address x10: Array bank 10 x_address x11: Array bank 11 x_address x12: Array bank 12 x_address x13: Array bank 13 x_address x14: Array bank 14 x_address proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

89 7-9 table 7-1 system control registers (sheet 9 of 14) address register name 0x3086 DEBUG MODE Debug Mode 0x3091 R_ARRAY 0x00 RW 0x30A5 SLEW 0x00 RW 0x30A9 R_PWC 0x07 RW Bit[7:6]: Bit[5:0]: Bit[7:3]: Bit[2:0]: Bit[7:4]: Bit[3:]: 0x15: Array bank 15 x_address x16: Array bank 16 x_address x17: Array bank 17 x_address x18: Array bank 18 x_address x19: Array bank 19 x_address x1A: Array bank 1A x_address x1B: Array bank 1B x_address x1C: Array bank 1C x_address x1D: Array bank 1D x_address x1E: array bank 1E x_address x1F: array bank 31 x_address Array binning control 00: Horizontal sum 11: Horizontal 2:1 skip Debug mode Debug mode VCM output current control 000: 0.71 * Id 001: 0.77 * Id 010: 0.83 * Id 011: 0.91 * Id 100: 1.00 * Id 101: 1.11 * Id 110: 1.25 * Id 111: 1.43 * Id Debug mode Bypass internal 1.5V regulator 0: Enable internal regulator 1: Bypass internal regulator Debug 0x30B0 IO_CTRL0 0xFF RW default value R/W description Bit[2:0]: IO_Ctrl0 Enable of Second Camera Interface Bit[7:0]: CY[7:0] PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

90 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-1 system control registers (sheet 10 of 14) default address register name value R/W description 0x30B1 IO_CTRL1 0xEF RW IO_Ctrl1 Enable of Second Camera Interface Bit[7]: C_VSYNC Bit[6]: C_STROBE Bit[5]: C_PCLK Bit[4]: C_HREF Bit[3:0]: CY[11:8] IO_Ctrl2 Enable of Second Camera Interface Bit[7:5]: Not used Bit[4]: C_FREX Bit[3]: C_XVCLK 0x30B2 IO_CTRL2 0x00 RW Bit[2]: Not used Bit[1:0]: I/O drive capability 00: 1x drive 01: 2x drive 10: 2x drive 11: 3x drive 0x30B3 DSIO 0x00 RW 0x30B4 DSIO 0x0C RW 0x30B5~ 0x30B6 Bit[3]: Bit[2]: Bit[1:0]: Bit[7:4]: Bit[3:2]: Bit[1:0]: DEBUG MODE Debug Mode PCLK manual option 0: PCLK division from ISP subsample 1: manual control by using RPCLKdiv Debug mode RPCLKdiv PCLK divisor 00: /1 01: /2 10: /4 11: /8 Debug digital_gain_sel 0x: agc[7:6] as digital gain 10: agc[8:7] as digital gain 11: agc[9:8] as digital gain Debug proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

91 7-11 table 7-1 system control registers (sheet 11 of 14) address register name 0x30B7 FRS 0x80 RW 0x30E4 FRS 0x07 RW 0x30E5 FRS 0x00 RW 0x30E6 FRS 0x00 RW 0x30E7 FRS 0x01 RW default value R/W description Bit[7]: dis_isp_rw Disable R/W or reg from ISP/MIPI Bit[6:4]: Not used Bit[3]: Group latch enable 0: Disable 1: Enable Bit[2:0]: Debug Note: To do group write: 0x6C 0x30B7 0x88 - enable group write Reg1 Reg2 0x6C 0x30B7 0x80 - disable group write 0x6C 0x30FF 0xFF - set group write flag Registers defined between 0x30B7 to 0x30FF will be written into sensor simultaneously at the coming Vertical blank, and after that, group latch will be disabled as register 0x30B7 is also group written to be 0x80. The maximum number of registers can be written into each group write is 16 registers. Frame Mode Pre-charge Time Unit: Lines Frame Mode Exposure Time Byte: High Unit: Lines Frame Mode Exposure Time Byte: Low Unit: Lines Bit[7]: Debug Bit[6]: FREX invert 0: FREX pulse is active high 1: FREX pulse is active low Bit[5:4]: Debug Bit[3:2]: Not used Bit[1]: Strobe source selection 0: Frame exposure mode strobe source 1: Rolling shutter mode strobe source Bit[0]: Frame exposure mode selection 0: Mode 1 - external FREX request 1: Mode 2 - I2C request PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

92 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-1 system control registers (sheet 12 of 14) address register name 0x30E8 FRS 0x00 RW 0x30EA FRS 0x38 RW 0x30EB FRS 0x00 RW 0x30EC VCM[15:8] 0x01 RW 0x30ED VCM[7:0] 0x50 RW 0x30EE SLEW[11:8] 0x05 RW 0x30EF SLEW[7:0] 0x46 RW default value R/W description Strobe Control Bit[7]: Strobe enable in rolling mode 0: Disable 1: Enable Bit[6]: Strobe output pulse polarity control 0: Positive pulse 1: Negative pulse Bit[5:4]: Debug mode Bit[3:2]: Xenon mode strobe pulse width 00: 1 line 01: 2 lines 10: 3 lines 11: 4 lines Bit[1:0]: Strobe mode 00: Xenon mode 01: LED1&2 mode 10: LED1&2 mode 11: LED3 mode Bit[3:0]: Bit[7:1]: Bit[0]: Bit[7]: Bit[6]: Bit[5:0]: Bit[7:4]: Bit[3]: Bit[2:0]: Bit[7:4]: Bit[3:0]: Bit[7:0]: Strobe pulse width in frame exposure mode (1-16 Tlines) Debug mode I2C controlled frame exposure mode (mode 2) reset start VCM power down Debug mode D[9:4] D[3:0] S3 S[2:0] Debug mode Rdiv[11:8] Rdiv[7:0] VCM control clock = external clock / Rdiv[11:0] 0x30F7 DEBUG MODE Debug Mode proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

93 7-13 table 7-1 system control registers (sheet 13 of 14) address register name 0x30F8 IMAGE_TRANSFORM 0x00 RW 0x30F9 DEBUG MODE Debug Mode 0x30FA IMAGE_SYSTEM 0x01 RW default value R/W description Bit[7]: VFLIP enable Bit[6]: HMIRROR enable Bit[5]: RISPsubV Disable V subsample in sensor Bit[4]: RISPsub Disable H subsample in sensor Bit[3:2]: VSUB 00: Full 01: 1:2 10: 1:4 11 1:8 Bit[1:0]: HSUB 00: Full 01: 1:2 10: 1:4 11: 1:8 Note: H subsample can be implemented in ARRAY and ISP depending on the value of RISPsub V subsample is performed in ARRAY only Bit[7]: Bit[6:3]: Bit[2]: Bit[1]: Bit[0]: 0x30FB~ 0x30FE DEBUG MODE Debug Mode 0x30FF GROUP_WR 0x00 RW Group Write Flag Software reset 0: Debug mode 1: All including I2C is reset to default, then goes to standby Debug mode Mask corrupted frames (this function does not work when group latch is ON) 0: No frame drop 1: Frames are dropped due to change in timing, size, etc. Debug Mode select 0: Software sleep / standby 1: Streaming PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

94 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-1 system control registers (sheet 14 of 14) address 0x3100 SYS_RST 0x09 RW 0x3101 CLOCK_EN 0xFF RW table 7-2 ISP control registers (sheet 1 of 8) address register name register name 0x3300 TOP 0xFF RW 0x3301 TOP 0x08 RW default value R/W description default value R/W description System Reset Enable (0: disable; 1: enable) Bit[7]: DVP SCLK reset Bit[6:4]: Debug mode Bit[3]: DVP PCLK reset Bit[2]: MIPI PCLK reset Bit[1]: MIPI SCLK reset Bit[0]: ISP reset System Clock Enable (0: disable; 1: enable) Bit[7]: DVP SCLK clock enable Bit[6:4]: Debug mode Bit[3]: DVP PCLK clock enable Bit[2]: MIPI PCLK clock enable Bit[1]: MIPI SCLK clock enable Bit[0]: ISP clock enable ISP Enable Control 00 - corresponding clock will be stopped if one module is disabled (0: disable; 1: enable) Bit[7]: ISP_en Bit[6]: AWB_stat_en Bit[5]: AWB_gain_en Bit[4]: LENC_en Bit[3]: WC_en (white pixel cancellation) Bit[2]: BC_en (black pixel cancellation) Bit[1]: EvenOdd_en (functions only when Bit[0] = 1) Bit[0]: BLC_en ISP Enable Control 01 - corresponding clock will be stopped if one module is disabled Bit[7:5]: Debug mode Bit[4]: anti_shake_en Bit[3]: frame_average_en Bit[2]: vario_pixel_en Bit[1]: digital_gain_en Bit[0]: Debug mode proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

95 7-15 table 7-2 ISP control registers (sheet 2 of 8) address 0x3302 TOP 0x00 RW 0x3303 CBAR 0x80 RW 0x3304 TOP 0x05 RW 0x3305~ 0x3307 register name ISP Enable Control 00 - corresponding clock will be stopped if one module is disabled (0: disable; 1: enable) Bit[7:5]: Debug mode Bit[4]: gamma_en Bit[3]: horizontal_vario_pixel_en Bit[2]: combine_en Bit[1]: stretch_en Bit[0]: Debug mode Bit[7]: Bit[0]: Bit[7:6]: Bit[5:3]: Bit[2]: Bit[1]: Bit[0]: DEBUG MODE Debug Mode 0x3308 BLC 0x33 RW 0x3309 DIG_GAIN 0x40 RW 0x330A WBC 0x3F RW default value R/W description Bit[3]: Bit[7:0]: Bit[7:6]: Bit[5:4]: Bit[3]: Bit[2]: Bar move enable 0: Disable bar move 1: Enable a H bar moving from top to bottom Color bar enable 0: Color bar OFF 1: Color bar enable avg_sel[1:0] Frame average input select Debug mode buf_ctrl_en bist_en Debug mode dg_man_en (functions only when register 0x3301[1] = 1) 0: dig_gain auto mode 1: dig_gain manual mode dg_gain[7:0] Manual digital gain Digital gain = (Bit[7]+1)*(Bit[6]+1) + Bit[5:0]/64 Debug mode wbc_bd_sel[1:0] Boundary select options wbc_se_en Enable same channel detection wbc_dc_en Enable different channel detection wbc_smooth_en Enable using average G values when doing recovery wbc_detail_en Enable detail detection method Bit[1]: Bit[0]: PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

96 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-2 ISP control registers (sheet 3 of 8) address 0x330B WBC 0x20 RW 0x330C WBC 0x40 RW 0x330D WBC 0x30 RW Bit[7]: Bit[6:0]: Bit[7:0]: Bit[7:0]: 0x330E TOP 0x00 RW Indirect Read Address 0x330F TOP 0x03 R Indirect Read Data Debug mode wbc_wthre[6:0] Threshold value for detecting white pixels wbc_bthre[7:0] Threshold value for detecting black pixels wbc_thre[7:0] Threshold value used in recovery 0x3310~ DEBUG MODE Debug Mode 0x3315 0x3316 SIZE 0x00 RW Bit[7:0]: H_pad_start[7:0] 0x3317 SIZE 0x00 RW Bit[7:0]: H_pad_end[7:0] 0x3318 SIZE 0x00 RW Bit[7:4]: Bit[3:0]: H_pad_end[11:8] H_pad_start[11:8] 0x3319 SIZE 0x00 RW Bit[7:0]: V_pad_start[7:0] 0x331A SIZE 0x00 RW Bit[7:0]: V_pad_end[7:0] 0x331B SIZE 0x00 RW 0x331C~ 0x331F register name Bit[7:4]: Bit[3:0]: V_pad_end[11:8] V_pad_start[11:8] AVG RW Frame Average Control 0x3320 AWB 0x82 RW 0x3321 AWB 0x04 RW 0x3322 AWB 0x08 RW 0x3323 AWB 0x00 RW default value R/W description Bit[7]: Bit[6]: Bit[5:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: fast_awb Fast AWB awb_man_en awb_delta AWB gain adjustment step stable_range[7:0] Threshold from unstable to stable stable_rangew[7:0] Threshold from stable to unstable. This should be greater than stable_range. AWB_frame_cnt[7:0] Change AWB gain speed 0x3324 AWB 0x40 RW Bit[7:0]: AWB_R_gain[11:4] 0x3325 AWB 0x40 RW Bit[7:0]: AWB_G_gain[11:4] proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

97 7-17 table 7-2 ISP control registers (sheet 4 of 8) address register name 0x3326 AWB 0x40 RW Bit[7:0]: AWB_B_gain[11:4] 0x3327 AWB 0x00 RW 0x3328 AWB 0x00 RW 0x3329 WBC 0x03 RW 0x332A WBC 0x20 RW 0x332B WBC 0x31 RW 0x332C WBC 0x03 RW default value R/W description Bit[7:4]: Bit[3:0]: Bit[7]: Bit[6]: Bit[5:4]: Bit[3:0]: Bit[7]: Bit[6]: Bit[5]: Bit[7]: Bit[6:0]: Bit[7]: Bit[6:4]: Bit[3]: Bit[2:0]: Bit[7:3]: Bit[2:0]: AWB_R_gain[3:0] AWB_G_gain[3:0] AWB_freeze_en AWB_sel 0: From VarioPixel 1: From AWB_gain Debug mode AWB_B_gain[3:0] Remove cross cluster option enable Remove tail option enable Anti-artifact option enable WBC_man Enable manual mode in which wthre, bthre, and detail_en can be set manually wbc_wthre[6:0] Reference threshold when determining wthre in auto mode WBC_gain_man_en WBC_refgain_pwr[2:0] Range: 0~5 Debug mode WBC_shift[2:0] Range: 0~7 Debug mode WBC_gainbd_pwr[2:0] Range: 0~5 0x332D WBC 0x02 RW Bit[7:0]: WBC_gain_man[7:0] 0x332E~ 0x332F DEBUG MODE Debug Mode 0x3330 BLC RW BLC Control 0x3331 BLC 0x10 RW Bit[7:0]: BLC target low byte 0x3332 BLC 0x10 RW Bit[7:0]: BLC debug must be set to 0x PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

98 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-2 ISP control registers (sheet 5 of 8) address register name 0x3333 BLC 0x02 RW 0x3334 BLC 0x00 RW 0x3336 BLC_MAN0 0x00 RW 0x3337 BLC_MAN1 0x00 RW 0x3338 BLC_MAN2 0x00 RW 0x3339 BLC_MAN3 0x00 RW 0x333A BLC_MAN4 0x00 RW 0x333B BLC_MAN5 0x00 RW Bit[7:6]: Bit[5:4]: Bit[3:2]: Bit[0]: Debug mode BLC target high byte BLC debug must be set to Bit[5:4] BLC option 0: BLC value is controlled by register 0x3347[1] 1: If Gain is changed, no matter BLC is in average mode (register 0x3347[1] = 1), BLC will use current frame BLC value Bit[7:6]: Debug mode Bit[5]: Manual BLC offset option (functions only when Bit[4] = 1) 0: Use different registers for different channels 1: Use blc_man0 to compensate all channels BLC Bit[4]: Manual BLC adjust enable (functions only when register 0x3300[0] = 1) 0: Auto BLC 1: Manual BLC Bit[3:0]: Debug mode Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: BLC offset low byte B channel BLC offset low byte Gb channel BLC offset low byte Gr channel BLC offset low byte R channel BLC debug must be set to same value as register 0x3336 BLC debug must be set to same value as register 0x3337 0x333C BLC_MAN6 0x00 RW 0x333D BLC_MAN7 0x00 RW default value R/W description Bit[7:0]: Bit[7:0]: BLC debug must be set to same value as register 0x3338 BLC debug must be set to same value as register 0x3339 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

99 7-19 table 7-2 ISP control registers (sheet 6 of 8) address 0x333E BLC_MAN0/1 0x00 RW 0x333F BLC_MAN2/3 0x00 RW 0x3340 BLC_MAN5/6 0x00 RW 0x3341 BLC_MAN6/7 0x00 RW 0x3342~ 0x3346 Bit[7:4]: Bit[3:0]: Bit[7:4]: Bit[3:0]: Bit[7:4]: Bit[3:0]: Bit[7:4]: Bit[3:0]: DEBUG MODE Debug Mode 0x3347 BLC_AVG 0x06 RW 0x3348~ 0x334F 0x3350~ 0x33E3 register name Bit[7:2]: Bit[1]: Bit[0]: DEBUG MODE Debug Mode LENC RW LENC Control BLC offset high byte B channel BLC offset high byte Gb channel BLC offset high byte Gr channel BLC offset high byte R channel BLC debug must be set to same value as register 0x333E[7:4] BLC debug must be set to same value as register 0x333E[3:0] BLC debug must be set to same value as register 0x333F[7:4] BLC debug must be set to same value as register 0x333F[3:0] Debug mode BLC_avg 0: User current frame BLC 1: Average current BLC with previous frame BLC Even/Odd option 0: Extract even/odd information from previous frame 1: Extract even/odd information from black line 0x33E4 LENC 0x02 RW default value R/W description Bit[7:4]: Bit[3:2]: Bit[1:]: Bit[0]: Debug mode LENC vertical skip LENC auto gain enable LENC horizontal skip For full resolution or cropping from full resolution, set register 0x33E4 = 0x02 For 2:1 downsampling, set register 0x33E4 = 0x07 For 4:1 downsampling, set register 0x33E4 = 0x0B For 8:1 downsampling, set register 0x33E4 = 0x0F PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

100 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-2 ISP control registers (sheet 7 of 8) default address register name value R/W description 0x33E5 VAP 0x00 RW 0x33E6 VAP 0x00 RW 0x33E7~ 0x33EF Bit[7:6]: Bit[5:4]: Bit[3:2]: Bit[1:0]: Bit[7:4]: Bit[3:0]: DEBUG MODE Debug Mode Debug mode vap_addopt[1:0] VarioPixel option Manual gain enable vap_vskip[1:0] Vertical skip 00: 1:1 01: 1:2 10: 1:4 11: 1:1 vap_hskip[1:0] Horizontal skip 00: 1:1 01: 1:2 10: 1:4 11: 1:1 Debug mode vap_avg_eb[3:0] Average enable 0x33F0 GAMMA 0x26 RW Bit[7:0]: gma_y1[7:0] 0x33F1 GAMMA 0x35 RW Bit[7:0]: gma_y2[7:0] 0x33F2 GAMMA 0x48 RW Bit[7:0]: gma_y3[7:0] 0x33F3 GAMMA 0x63 RW Bit[7:0]: gma_y4[7:0] 0x33F4 GAMMA 0x6E RW Bit[7:0]: gma_y5[7:0] 0x33F5 GAMMA 0x77 RW Bit[7:0]: gma_y6[7:0] 0x33F6 GAMMA 0x80 RW Bit[7:0]: gma_y7[7:0] 0x33F7 GAMMA 0x88 RW Bit[7:0]: gma_y8[7:0] 0x33F8 GAMMA 0x8F RW Bit[7:0]: gma_y9[7:0] 0x33F9 GAMMA 0x96 RW Bit[7:0]: gma_ya[7:0] 0x33FA GAMMA 0xA3 RW Bit[7:0]: gma_yb[7:0] 0x33FB GAMMA 0xAF RW Bit[7:0]: gma_yc[7:0] 0x33FC GAMMA 0xC5 RW Bit[7:0]: gma_yd[7:0] 0x33FD GAMMA 0xD7 RW Bit[7:0]: gma_ye[7:0] 0x33FE GAMMA 0xE8 RW Bit[7:0]: gma_yf[7:0] 0x33FF GAMMA 0x20 RW Bit[7:0]: gma_yslp[7:0] proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

101 7-21 table 7-2 ISP control registers (sheet 8 of 8) address 0x3700 VAP_H 0x00 RW 0x3701~ 0x370F register name DEBUG MODE Debug Mode 0x3710 SHAKE 0x8A RW 0x3711 SHAKE 0x04 RW VAP_H_mode[7:0] Bit[7:6]: B_mode[1:0] 00: Average 01: Drop second 1x: Drop first Bit[5:4]: Gb_mode[1:0] 00: Average 01: Drop second 1x: Drop first Bit[3:2]: Gr_mode[1:0] 00: Average 01: Drop second 1x: Drop first Bit[1:0]: R_mode[1:0] 00: Average 01: Drop second 1x: Drop first Bit[7]: Bit[6]: Bit[5]: Bit[4:0]: Bit[7:4]: Bit[3:0]: anti_mode anti_capture Debug mode anti_max_frame[4:0] Debug mode anti_precision[3:0] 0x3712 SHAKE 0x00 RW Bit[7:0]: anti_threshold[7:0] 0x3713 SHAKE 0x0A RW Bit[7:0]: anti_threshold[15:8] 0x3714 SHAKE 0x00 RW Bit[7:0]: anti_starth[11:4] 0x3715 SHAKE 0x00 RW Bit[7:0]: anti_startv[11:4] 0x3716 SHAKE 0xCE RW Bit[7:0]: anti_width[11:4] 0x3717 SHAKE 0x99 RW Bit[7:0]: anti_height[11:4] 0x3718 SHAKE 0x00 RW 0x3719 SHAKE 0x80 RW default value R/W description Bit[7:4]: Bit[3:0]: Bit[7:4]: Bit[3:0]: anti_startv[3:0] anti_starth[3:0] anti_height[3:0] anti_width[3:0] PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

102 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-3 DVP control registers (sheet 1 of 3) address register name 0x3500 DVP_CTRL00 0x80 RW 0x3501 DVP_CTRL01 0x00 RW default value R/W description DVP Control 00 Bit[7:6]: VSYNC select 00: Select vsync_old 01: Select vsync_new 10: Select vsync_three 11: Debug mode Bit[5]: pclk_gate_en 1: Gate dvp_pclk when HREF is low Bit[4]: vsync_gate 0: Gate dvp_pclk when VSYNC and pclk_gate_en is high 1: Do not gate dvp_pclk when VSYNC is high Bit[3]: dmy_line_sel 0: Auto generate dummy lines 1: Use first lines as dummy lines Bit[2]: Change polarity of PCLK Bit[1]: Change polarity of HREF Bit[0]: vsync_pol 0: VSYNC = 1 is frame blanking time DVP Control 01 Bit[7]: ccir656_en Bit[6]: sync_code_sel 0: Auto generate sync_code 1: Use FS, FE, LS and LE as ccir656 sync_code Bit[5]: Debug mode Bit[4]: data_order 0: DVP output dvp_data[11:0] 1: DVP output dvp_data[0:11] Bit[3]: dvp_bit8 0: Swap 2 bit when dvp_h and dvp_l 1: Swap 4 bit Bit[2]: dvp_h 0: Output dvp_data[11:0] 1: Output dvp_data{n:0, 11:n-1} n: 7 or 9 Bit[1]: dvp_l 0: Select dvp_data[11:0] 1: Select dvp_data{n:0, 11:n+1} n: 3 or 1 Bit[0]: ch_flag Write 1 to it to generate flag for HSYNC mode 0x3502 DVP_CTRL02 0xAB RW DVP Control 02 Bit[7:0]: CCIR656 sync code for FS proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

103 7-23 table 7-3 DVP control registers (sheet 2 of 3) default address register name value R/W description 0x3503 DVP_CTRL03 0xB6 RW 0x3504 DVP_CTRL04 0x80 RW 0x3505 DVP_CTRL05 0x9D RW 0x3506 DVP_CTRL06 0x20 RW 0x3507 DVP_CTRL07 0x80 RW DVP Control 03 Bit[7:0]: CCIR656 sync code for FE DVP Control 04 Bit[7:0]: CCIR656 sync code for LS DVP Control 05 Bit[7:0]: CCIR656 sync code for LE DVP Control 06 Bit[7:6]: Debug mode Bit[5]: dvp_en Bit[4]: hsync_en Bit[3:0]: Debug mode DVP Control 07 Bit[7:1]: vsync_width[7:1] Width of VSYNC when selecting vsync_old and vsync_three Bit[0]: hskip_man_o[0] DVP Control 08 Bit[7]: tst_ptn_en Bit[6]: tst_bit8 0x3508 DVP_CTRL08 0x00 RW Bit[5]: tst_bit12 Bit[4]: tst_mode 0: 00, 01, 02,..., 80, FF 1: 00, 00, 01, 01,..., FF, FF Bit[3:0]: dmy_line_nu 0x3509 DVP_CTRL09 0x00 RW DVP Control 09 Bit[7:0]: eof2v_dly[23:16] 0x350A DVP_CTRL0A 0x01 RW 0x350B DVP_CTRL0B 0x00 RW 0x350C DVP_CTRL0C 0x00 RW 0x350D DVP_CTRL0D 0x00 RW DVP Control 0A Bit[7:0]: eof2v_dly[15:8] DVP Control 0B Bit[7:0]: eof2v_dly[7:0] DVP Control 0C Bit[7:0]: pad_right DVP Control 0D Bit[7:0]: pad_left DVP Control 0E Bit[7:6]: Debug mode 0x350E DVP_CTRL0E 0x40 RW Bit[5:4]: vsync_width[9:8] Bit[3:1]: Debug mode Bit[0]: skip_man_en_o PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

104 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-3 DVP control registers (sheet 3 of 3) address register name 0x350F DVP_CTRL0F 0x88 RW 0x3510 DVP_CTRL10 0x09 RW 0x3511 DVP_CTRL11 0xAA RW 0x3512 DVP_CTRL12 0x55 RW DVP Control 0F Bit[7]: eav_first 0: sav_first 1: eav_first Bit[6]: f_sel Bit[5]: f_value Bit[4]: fix_f 0: Auto generate ccir_f 1: Use f_value as ccir_f Bit[3:2]: blk_sel 00: Select 12 h800 and 12 h100 as toggle data x1: Select 12 h000 as toggle data 10: Select tog0 and tog1 as toggle data Bit[1]: no_sof 0: Reset state machine at SOF 1: Do not reset state machine at SOF Bit[0]: no_clip 0: Clip output data between 10 h004 and 10 h3fb 1: Do not clip output data when in CCIR656 mode DVP Control 10 Bit[7:4]: Debug mode Bit[3:2]: tog0[11:10] Toggle data0 when line blanking or dummy lines Bit[1:0]: tog1[11:10] Toggle data1 when line blanking or dummy lines DVP Control 11 Bit[7:0]: tog0[9:2] Toggle data0 when line blanking or dummy lines DVP Control 12 Bit[7:0]: tog1[9:2] Toggle data1 when line blanking or dummy lines 0x3513 DVP_CTRL13 0x02 RW 0x3514 DVP_CTRL14 0x00 RW default value R/W description DVP Control 13 Bit[7:0]: Debug mode DVP Control 14 Bit[7:0]: h2v_dly 0x3515 DVP_CTRL15 0x00 RW DVP Control 15 Bit[7:0]: v2h_dly proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

105 7-25 table 7-4 MIPI control registers (sheet 1 of 6) address register name 0x3600 MIPI_CTRL00 0x00 RW 0x3601 MIPI_CTRL01 0x10 RW default value R/W description MIPI Control 00 Bit[7]: lp_p1_out Bit[6]: lp_n1_out Bit[5]: lp_p2_out Bit[4]: lp_n2_out Bit[3]: lp_sel1 0: Auto generate lp_dir1 1: Use lp_dir_man1 as lp_dir1 Bit[2]: lp_sel2 0: Auto generate lp_dir2 1: Use lp_dir_man2 as lp_dir2 Bit[1]: lp_dir_man1 0: Input 1: Output Bit[0]: lp_dir_man2 0: Input 1: Output MIPI Control 01 Bit[7]: Debug mode Bit[6]: line_sync_en 1: Enable line sync short packet Bit[5]: lane_sel 0: Use lane1 as default data lane 1: Select lane 2 as default data lane Bit[4]: lp_tx_lane_sel 0: Select lane1 as lp_tx_lane 1: Select lane2 as lp_tx_lane Bit[3]: Debug mode Bit[2]: ph_byte_order2 PH sequence for ECC calculation 0: {DI, WC} 1: {WC, DI} Bit[1]: ph_byte_order PH sequence for ECC calculation 0: {WC_l, WC_h} 1: {WC_h, WC_l} Bit[0]: ph_bit_order 0: DI[7:0], WC[7:0], WC[15:8] 1: DI[0:7], WC[0:7], WC[8:15] 0x3602 MIPI_CTRL02 0x12 RW MIPI Control 02 Bit[7:6]: VC Virtual channel ID Bit[5:0]: dt_dmy Data type for dummy lines 0x3603 MIPI_CTRL03 0x2A RW MIPI Control 03 Bit[7:6]: Debug mode Bit[5:0]: dt_man Manually set data type PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

106 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-4 MIPI control registers (sheet 2 of 6) address 0x3604 MIPI_CTRL04 0x58 RW 0x3605 MIPI_CTRL05 0x00 RW 0x3606 MIPI_CTRL06 0x00 RW 0x3607 MIPI_CTRL07 0x68 RW 0x3608~ 0x3609 register name DEBUG MODE Debug Mode 0x360A MIPI_CTRL0A 0x01 RW 0x360B MIPI_CTRL0B 0x3C RW default value R/W description MIPI Control 04 Bit[7:3]: Debug mode Bit[2]: spkt_dt_sel 1: Use dt_dmy as short packet Bit[1]: lpkt_dt_sel 0: Use dt_auto 1: Use dt_man as long packet Bit[0]: spkt_wc_sel 1: Select spkt_wc_reg as short packet wc MIPI Control 05 Bit[7:0]: High byte of spkt_wc_reg[15:8] MIPI Control 06 Bit[7:0]: Low byte of spkt_wc_reg[7:0] MIPI Control 07 Bit[7]: Debug mode Bit[6]: ta_en Enable send turnaround command after read data transmission is finished Bit[0]: Debug mode MIPI Control 0A Bit[7]: Debug mode Bit[6]: gate_sc_en 0: Clock is in free running mode 1: Gate MIPI clock when there is no packet Bit[5:0]: Debug mode MIPI Control 0B Bit[7]: cd1_int_en 1: Enable internal cd1 enable Bit[6]: cd2_int_en 1: Enable internal cd2 enable Bit[5]: lp_cd_en1 1: Enable LP CD detection on lane1 Bit[4]: lp_cd_en2 1: Enable LP CD detection on lane2 Bit[3:2]: Debug mode Bit[1]: lane_disable1 1: Disable MIPI data lane1 to LP00 state Bit[0]: lane_disable2 1: Disable MIPI data lane2 to LP00 state proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

107 7-27 table 7-4 MIPI control registers (sheet 3 of 6) default address register name value R/W description MIPI Control 0C Bit[7:2]: Debug mode 0x360C MIPI_CTRL0C 0x03 RW Bit[1]: inc_en 1: mipi_reg_addr will auto increment by 1 Bit[0]: Debug mode 0x360D DEBUG MODE Debug Mode MIPI Control 0E Bit[7]: lpx_p_sel 0: Select lpx_p_cal 1: Select lpx_p_reg[7:0] as t_lpx_p Bit[6]: First bit 0x360E MIPI_CTRL0E 0x02 RW Change clk_lane first bit 0: Output 0x55 1: Output 0xAA Bit[5:0]: wkup_dly 1 ms wakeup delay/4096 for MIPI ultra low power resume 0x360F DEBUG MODE Debug Mode 0x3610 MIPI_CTRL10 0x10 RW 0x3611 MIPI_CTRL11 0x4F RW 0x3612 DEBUG MODE Debug Mode MIPI Control 10 Bit[7:0]: pclk_period pclk2x period, 1-bit decimal, unit ns MIPI Control 11 Bit[7:4]: T_lpx SCLK domain Bit[3:0]: T_clk_pre unit pclk2x cycle PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

108 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-4 MIPI control registers (sheet 4 of 6) address register name 0x3613 MIPI_CTRL13 0x00 RW 0x3614 MIPI_CTRL14 0x28 RW 0x3615 MIPI_CTRL15 0x96 RW 0x3616 MIPI_CTRL16 0x10 RW MIPI Control 13 - MIPI Timing Register Select (0: auto calculated parameter, relate to register 0x3622 to 0x3637; 1: use low byte of parameter) Bit[7]: clk_zero_sel 0: Auto calculate t_clk_zero 1: Use t_clk_zero_reg Bit[6]: hs_trail_sel 0: Auto calculate t_hs_trail 1: Use t_hs_trail_reg Bit[5]: hs_zero_sel 0: Auto calculate t_hs_zero 1: Use t_hs_zero_reg Bit[4]: hs_exit_sel 0: Auto calculate t_hs_exit 1: Use t_hs_exit_reg Bit[3]: clk_trail_sel 0: Auto calculate t_clk_trail 1: Use t_clk_trail_reg Bit[2]: clk_post_sel 0: Auto calculate t_clk_post 1: Use t_clk_post_reg Bit[1]: clk_prepare_sel 0: Auto calculate t_clk_prepare 1: Use t_clk_prepare_reg Bit[0]: hs_prepare_sel 0: Auto calculate t_hs_prepare 1: Use t_hs_prepare_reg MIPI Control 14 Bit[7:2]: N UI for t_hs_zero Minimum high speed zero Bit[1:0]: Min_hs_zero_high[9:8] Unit is pclk2x cycles when hs_zero_sel = 1 and unit is ns when hs_zero_sel = 0 MIPI Control 15 Bit[7:0]: Min_hs_zero_low[7:0] MIPI Control 16 Bit[7:2]: N UI for t_hs_trail Minimum high speed trail Bit[1:0]: Min_hs_trail_high[9:8] Unit is pclk2x cycles when hs_trail_sel = 1 and ns when hs_trail_sel = 0 0x3617 MIPI_CTRL17 0x3C RW default value R/W description MIPI Control 17 Bit[7:0]: Min_hs_trail_low[7:0] proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

109 7-29 table 7-4 MIPI control registers (sheet 5 of 6) address register name 0x3618 MIPI_CTRL18 0x01 RW 0x3619 MIPI_CTRL19 0x86 RW 0x361A MIPI_CTRL1A 0x00 RW 0x361B MIPI_CTRL1B 0x32 RW 0x361C MIPI_CTRL1C 0x00 RW 0x361D MIPI_CTRL1D 0x8C RW 0x361E MIPI_CTRL1E 0xD0 RW 0x361F MIPI_CTRL1F 0x56 RW 0x3620 MIPI_CTRL20 0x08 RW MIPI Control 18 Bit[7:2]: N UI for t_clk_zero Minimum clock zero Bit[1:0]: Min_clk_zero_high[9:8] Unit is pclk2x cycles when clk_zero_sel = 1 and ns when clk_zero_sel = 0 MIPI Control 19 Bit[7:0]: Min_clk_zero_low[7:0] MIPI Control 1A Bit[7:2]: N UI for min_clk_pre Minimum clock prepare time Bit[1:0]: Min_clk_pre_high[9:8] Unit is pclk2x cycles when clk_prepare_sel = 1 and ns when clk_prepare_sel = 0 MIPI Control 1B Bit[7:0]: Min_clk_pre_low[7:0] MIPI Control 1C Bit[7:2]: N UI for max_clk_pre Maximum clock prepare time Bit[1:0]: Max_clk_pre_high[9:8] Unit is ns MIPI Control 1D Bit[7:0]: Max_clk_pre_low[7:0] MIPI Control 1E Bit[7:2]: N UI for min_clk_post Minimum clock post time Bit[1:0]: Min_clk_post_high[9:8] Unit is pclk2x cycles when clk_post_sel = 1 and ns when clk_post_sel = 0 MIPI Control 1F Bit[7:0]: Min_clk_post_low[9:8] MIPI Control 20 Bit[7:2]: N UI for min_clk_trail Minimum clock trail Bit[1:0]: Min_clk_trail_high[9:8] Unit is pclk2x cycles when clk_trail_sel = 1 and ns when clk_trail_sel = 0 0x3621 MIPI_CTRL21 0x3C RW default value R/W description MIPI Control 21 Bit[7:0]: Min_clk_trail_low[7:0] PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

110 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 7-4 MIPI control registers (sheet 6 of 6) address 0x3622 MIPI_CTRL22 0x00 RW 0x3623 MIPI_CTRL23 0x32 RW 0x3624 MIPI_CTRL24 0x10 RW 0x3625 MIPI_CTRL25 0x2A RW 0x3626 MIPI_CTRL26 0x18 RW 0x3627 MIPI_CTRL27 0x55 RW 0x3628 MIPI_CTRL28 0x00 RW 0x3629 MIPI_CTRL29 0x64 RW 0x362A~ 0x362D register name DEBUG MODE Debug Mode 0x362F MIPI_CTRL2F 0x08 RW 0x3630 MIPI_CTRL30 0x14 RW default value R/W description MIPI Control 22 Bit[7:2]: N UI for min_lpx_p Bit[1:0]: Min_lpx_p_high[9:8] Unit is pclk2x cycles when lpx_p_sel = 1 and ns when lpx_p_sel = 0 MIPI Control 23 Bit[7:0]: Min_lpx_p_low[7:0] MIPI Control 24 Bit[7:2]: N UI for min_hs_prepare Bit[1:0]: Min_hs_prepare_high[9:8] Unit is pclk2x cycles when hs_prepare_sel = 1 and ns when hs_prepare_sel = 0 MIPI Control 25 Bit[7:0]: Min_hs_prepare_low[7:0] MIPI Control 26 Bit[7:2]: N UI for max_hs_prepare Bit[1:0]: Max_hs_prepare_high[9:8] Unit is ns MIPI Control 27 Bit[7:0]: Max_hs_prepare_low[7:0] MIPI Control 28 Bit[7:2]: N UI for min_hs_exit Bit[1:0]: Min_hs_exit_high[9:8] Unit is pclk2x cycles when hs_exit_sel = 1 and ns when hs_exit_sel = 0 MIPI Control 29 Bit[7:0]: Max_hs_exit_low[7:0] MIPI Control 2F Bit[7:0]: t_ta_sure MIPI Control 30 Bit[7:0]: t_ta_get proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

111 8-1 8 operating specifications 8.1 absolute maximum ratings table 8-1 absolute maximum ratings parameter ambient storage temperature supply voltage (with respect to ground) b electro-static discharge (ESD) all input/output voltages (with respect to ground) I/O current on any input or output pin 8.2 functional temperature V DD-A 4.5V V DD-D absolute maximum rating a -40 C to +125 C peak solder temperature (10 second dwell time) 245 C a. exceeding the absolute maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. b. for negative voltage with respect to ground, V DD-A (-4.5V), V DD-D (-3V), V DD-IO (-4.5V) 3V V DD-IO 4.5V human body model machine model 2000V 200V -0.3V to V DD-IO + 1V ±200 ma table 8-2 functional temperature parameter range operating temperature range a stable image temperature range b -30 C to +70 C a. sensor functions but image quality may be noticeably different at temperatures outside of stable image range b. image quality remains stable throughout this temperature range 0 C to +50 C PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

112 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 8.3 DC characteristics table 8-3 DC characteristics (-30 C < T A < 70 C) symbol parameter min typ max unit supply V DD-A supply voltage (analog) V V DD-S supply voltage (pixel) V V DD-IO supply voltage (digital I/O) V V DD-D supply voltage (digital core) a V V DD-E supply voltage (MIPI) V internal DVDD, EVDD shorted to DVDD, DOVDD = 2.8V, 8M@96MHz, all ISP on, DVP out I DD-A ma I DD-S 5 15 ma b I DD-DO active (operating) current ma I DD-P 1 5 ma internal DVDD, EVDD shorted to DVDD, DOVDD = 1.8V, 8M@96MHz, all ISP on, DVP out I DD-A ma I DD-S 5 15 ma b I DD-DO active (operating) current ma I DD-P 1 5 ma internal DVDD, EVDD shorted to DVDD, DOVDD = 2.8V, 8M@576Mbps, 2-lane, all ISP on, MIPI out I DD-A 55 ma I DD-S 5 ma b I DD-DO active (operating) current 90 ma I DD-P 1 ma internal DVDD, EVDD shorted to DVDD, DOVDD = 1.8V, 8M@576Mbps, 2-lane, all ISP on, MIPI out I DD-A 55 ma I DD-S 5 ma b I DD-DO active (operating) current 85 ma I DD-P 1 ma I DD-SCCB µa standby current I DDS-PWDN µa proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

113 8-3 table 8-3 DC characteristics (-30 C < T A < 70 C) (continued) symbol parameter min typ max unit digital inputs (typical conditions: AVDD = 2.8V, DVDD = 1.5V, DOVDD = 1.8V) V IL input voltage LOW 0.54 V V IH input voltage HIGH 1.26 V C IN input capacitor 10 pf digital outputs (standard loading 25 pf, typical conditions: AVDD =2.8V, DVDD =1.5V, DOVDD=1.8V V OH output voltage HIGH 1.62 V V OL output voltage LOW 0.18 V serial interface inputs V c IL YSCL and YSDA V c V IH YSCL and YSDA V a. when internal regulator is bypassed b. including I DD-D c. based on V DD-DO = 1.8V PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

114 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 8.4 AC characteristics table 8-4 AC characteristics (T A = 25 C, V DD-A = 2.8V) symbol parameter min typ max unit ADC parameters B analog bandwidth 48 MHz DLE DC differential linearity error 0.5 LSB ILE DC integral linearity error 1 LSB settling time for hardware reset <1 ms settling time for software reset <1 ms settling time for resolution mode change <1 ms settling time for register setting <300 ms table 8-5 timing characteristics symbol parameter min typ max unit oscillator and clock input f OSC t r, t f frequency (YXVCLK) a clock input rise/fall time b F pclk, parallel port output pixel clock 48 d a. for input clock range 6~27MHz, the OV8810 can tolerate input clock jitter up to 500ps b. If PLL is bypassed, the delay from input clock to output clock is approximately 4~5ns c. if using the internal PLL d. typical PCLK is 48MHz when sensor output is smaller size (800x600 or below) e. maximum PCLK is 96MHz when sensor output is full speed MHz 5 (10 c ) 96 e ns MHz proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

115 8-5 figure 8-1 SCCB interface timing t F YSCL YSDA[IN] t SU:STA t AA YSDA[OUT] t HD:STA t HIGH t LOW t HD:DAT t SU:STO t DH table 8-6 SCCB interface timing specifications a symbol parameter min typ max unit f SCL clock frequency 400 b t LOW clock low period 1.3 µs t HIGH clock high period 0.6 µs t AA YSCL low to data out valid µs t BUF bus free time before new start 1.3 µs t HD:STA start condition hold time 0.6 µs t SU:STA start condition setup time 1.85 µs t HD:DAT data in hold time 0 µs t SU:DAT data in setup time 0.1 µs t SU:STO stop condition setup time 0.6 µs t R, t F SCCB rise/fall time 0.3 µs t DH data out hold time 0.05 µs t R t SU:DAT t BUF 8810_DS_8_1 KHz a. SCCB timing is based on 400KHz mode b. SCCB maximum speed is 400KHz when sensor mask input clock (XVCLK) is greater than or equal to 13MHz. When XVCLK is less than 13MHz, the maximum SCCB speed is less than 400KHz (approximately XVCLK/32.5) PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

116 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology figure 8-2 line/pixel output timing PCLK or MCLK YHREF YY[9:0] table 8-7 pixel timing specifications symbol parameter min typ max unit t p PCLK period ns t pr PCLK rising time 4 ns t pf PCLK falling time 2 ns t dphr PCLK negative edge to HREF rising edge 2.2 ns t dphf PCLK negative edge to HREF negative edge 1.8 ns t dpd PCLK negative edge to data output delay ns t su t hd data bus setup time a data bus hold time b t dphr t dpd t p invalid P 2047/1023 data P 0 P 1 P 2 P 2046/1022 P 2047/ ns 4 7 ns a. Test condition: PCLK = 96MHz, DOVDD, PVDD, AVDD, SVDD = 2.8V, DVDD is generated by internal regulator b. Driving capability was set to 2x (register 0x30B2[1:0] = 2'b01) for better signal quality and hence more accurate measurements t su t pr t hd t pf t dphf 8810_DS_8_2 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

117 8-7 figure 8-3 frame timing YVSYNC YHREF note 1 TFRAME = VSIZE + VBLANK note 2 TLINE = HSIZE + HBLANK VBLANK table 8-8 control parameter for standard resolution output H size V size H BLANK format (T P ) (T LINE ) H_BIN V_SKIP (T P ) V BLANK (T LINE ) maximum frame rate (fps) 3264 x :1 1: x :1 1: x :2 1: x :2 1: x :2 1: x :2 1: x :2 1: TLINE TFRAME HSIZE HBLANK HBLANK HBLANK DVP PCLK (MHz) VSIZE 8810_DS_8_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

118 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 8-9 VCM characteristics parameter a condition min typ max unit power AVDD, AGND V power on time 10 µs DC performance resolution 100 µa/lsb 10 bits differential non-linearity (DNL) guaranteed monotonic LSB relative accuracy (INL) ±1 LSB zero code error set all 10 bits low 0.2 ma output characteristics minimum output current 0.2 ma maximum output current 100 ma output power down current 4.5 ma output current settling time test code changed from 1/4 FS to 3/4 FS 200 µs a. AVDD = 2.6 ~ 3.1V, Rs = 3.3Ω, Vvcm = AVDD, temperature = -30 ~ 70C, VCM model as a R series with L where R = 26Ω and L = 680 uh proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

119 9-1 9 mechanical specifications 9.1 physical specifications figure 9-1 package specifications S2 J2 C1 C J1 S1 5 4 W X Y Z A B C D 3 BGA side (bumps up) side view 2 1 A B C D E F G H I D C3 C table 9-1 package dimensions (sheet 1 of 2) parameter symbol min typ max unit package body dimension x A µm package body dimension y B µm package height C µm ball height C µm package body thickness C µm thickness of glass surface to wafer C µm B center of BGA (die) = center of the package note A optical side (bumps down) A B C D E F G H I marking code: W: OVT product version X: year that part is assembled Y: month that part is assembled Z: wafer number ABCD: last four digits of lot number 8810_CSP_DS_9_1 ball diameter D µm total pin count N 67 (13 NC) PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

120 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology table 9-1 package dimensions (sheet 2 of 2) parameter symbol min typ max unit pin count x-axis N1 9 pin count y-axis N2 9 pins pitch x-axis J1 610 µm pins pitch y-axis J2 680 µm edge-to-pin center distance analog x S µm edge-to-pin center distance analog y S µm proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

121 IR reflow specifications figure 9-2 temperature ( C) table 9-2 condition -22 IR reflow ramp rate requirements reflow conditions average ramp-up rate (30 C to 217 C) exposure less than 3 C per second > 100 C between seconds > 150 C at least 210 seconds > 217 C at least 30 seconds (30 ~ 120 seconds) peak temperature 245 C cool-down rate (peak to 50 C) time from 30 C to 245 C Z1 Z2 Z3 Z4 Z5 Z6 Z7 end time (sec) less than 6 C per second no greater than 390 seconds note The OV8810 uses a lead-free package _CSP_DS_9_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

122 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

123 optical specifications 10.1 sensor array center figure 10-1 sensor array center 4614 µm A1 A2 A3 A4 A5 A6 A7 A8 A9 first pixel readout (-2637µm, 1923µm) note 3 array center (-330µm, 170µm) 3506 µm package center (0µm, 0µm) sensor array OV8810 top view note 1 this drawing is not to scale and is for reference only. note 2 as most optical assemblies invert and mirror the image, the chip is typically mounted with pins A1 to A9 oriented down on the PCB. note 3 due to our new OmniBSI technology, the readout of the sensor array starts from the top left corner. 8810_CSP_DS_10_ PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

124 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 10.2 lens chief ray angle (CRA) figure 10-2 chief ray angle( ) chief ray angle (CRA) image height (mm) table 10-1 CRA versus image height plot (sheet 1 of 2) field (%) image height (mm) CRA (degrees) CRA 8810_DS_10_ proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

125 10-3 table 10-1 CRA versus image height plot (sheet 2 of 2) field (%) image height (mm) CRA (degrees) PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

126 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology 10.3 spectrum response curve figure 10-3 output (mv / W.s) 3.00E E E E E+09 spectrum response curve 5.00E E E wavelength (nm) 8810_DS_10_3 R Gb Gr B proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

127 rev-1 revision history version initial release version under ordering information on page iii, changed ordering part number from OV08810-VL9A (color, lead-free) 67-pin CSP2 to OV08810-AL9A (color, lead-free) 67-pin CSP3 under mechancical specifications on page 9-1, extensively changed the drawing in figure 9-1 under mechanical specifications on page 9-1, changed min, typ, and max of package height (C), package body thickness (C2), cover glass thickness (C3), and airgap between cover glass and sensor (C4) version under applications on page iii, changed first bullet item from digital still camera to digital cameras under key specifications on page iii, changed lens chief ray angle from TBD to 27 non-linear (see Figure 10-2) in table 1-1 on pages 1-1 to 1-3, removed column for default I/O status in table 1-1 on page 1-1, changed description of pin A6, VREFN, from internal reference (connect to ground using 0.1 µf capacitor) to internal reference (requires a 0.1 µf capacitor between VREFN and AGND) in table 1-1 on page 1-1, changed description of pin B6, VREFH, from internal reference (connect to ground using 0.1 µf capacitor) to internal reference (requires a 0.1 µf capacitor between VREFH and AGND) in table 1-1 on page 1-3, changed description of pin H2, DVDD, from digital core logic power reference (connect to ground using 0.1 µf capacitor) (external supply: 1.35~1.65V, 1.5V typical) to digital core logic power reference (external supply: 1.35~1.65V, 1.5V typical) (requires a 0.1 µf capacitor between DVDD and DGND) in table 1-1 on page 1-3, changed description of pin I6, EVDD, from MIPI power (1.5V, should connect to DVDD) (connect to ground using 0.1 µf capacitor) to MIPI power (1.5V, should connect to DVDD) (requires a 0.1 µf capacitor between EVDD and DGND) in figure 2-3 on page 2-3, changed second box on first line from pll_multiplier x48 to pll_multiplier x40 in table 6-3 on page 6-3, changed description of register bit DVP_CTRL00[4] from: Bit[4]: vsync_gate 0: Gate dvp_pclk when VSYNC and pclk_gate_en is high 1: Do not gate dvp_pclk when VSYNC is high to: Bit[4]: vsync_gate 0: Do not gate dvp_pclk when VSYNC is high 1: Gate dvp_pclk when VSYNC and pclk_gate_en is high PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

128 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology in table 6-3 on page 6-3, changed description of register bit DVP_CTRL00[0] from: Bit[0]: vsync_pol 0: VSYNC = 1 is frame blanking time to: Bit[0]: Change polarity of VSYNC version under the features section, added QVGA: 120 fps under maximum image transfer rate under chapter 1, added figure 1-2: frame exposure mode control using sensor register settings under chapter 4, revised table 4-10 note from 0x30D0~0x30D4 for OmniVision and 0x30D5~0x30DF for customer changed to 0x30D0~0x30D3 for OmniVision and 0x30D4~0x30DF for customer version added major updates to the entire document version in key specifications section, updated the S/N ration from TBD to 35dB in key specifications section, updated the all power requirements in key specifications section, updated the dynamic range from TBD to 67dB in key specifications section, updated the sensitivity from TBD to 650mV/Lux-Sec in key specifications section, updated maximum exposure interval from TBD to 2482 Tline in chapter 2, updated table 2-1 format and frame rate (1/4 full size and 1/16 full size) in chapter 2, added figure 2-2 system clock control diagram in chapter 2, updated figure 2-3 and figure 2-4 in chapter 2, added section 2.9 power down (PWDN) in chapter 3, added figure 3-2 and 3-3, 3-4, 3-5 in chapter 4, updated figure 4-2 in chapter 4, removed section 4.4 digital zoom in chapter 4, updated section auto gain control (AGC) in chapter 5, removed register 0x3347 from table 5-1 in chapter 5, added in table 5-1 register 0x33E4 in chapter 5, revised the text for section 5.4 AWB in chapter 5, updated registers 0x3324~0x3328 in chapter 5, removed section 5.5 HDR in chapter 5, added register 0x3329 to the WBC section 5.5 in chapter 5, updated register 0x30F8 in section 5.6 in chapter 5, updated register 0x331C~0x331F in section 5.7 proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

129 rev-3 in chapter 5, removed section 5.9 anti-shake in chapter 6, added DVP control registers section introduction text in chapter DVP control registers updated 0x3100 and 0x3101 in chapter 6, updated register 0x300E in chapter 7, updated the following registers: (0x3000, 0x3001, 0x3006, 0x3008~0x3009, 0x3086, 0x30A5, 0x30B2, 0x30E, 0x30F7, 0x30FA, 0x3100, 0x310, 0x3302, 0x3303, 0x330E, 0x330F, 0x3310, 0x3315, 0x3316, 0x3317, 0x3318, 0x3319, 0x331A, 0x331B, 0x3329, 0x33E4, 0x3701~0x370F) in chapter 8, updated all tables and figures in chapter 8, added figure 8-1 and 8-2, added table 8-5, 8-6 updated table 9-1, changed pad sizes from 150 x 70 and 70 x 150 to 150 x 67 and 67 x 150 version in chapter 3, updated table 3-1 Bit[3:0] in chapter 6, updated figure 6-1 version in table 8-2, changed max values for active (operating) current for internal DVDD, EVDD shorted to DVDD, DOVDD=2.8V, 8M@96MHz, all ISP on, DVP out from "TBD" to "80", "15", "165", and "5" as well as typ value for I DD-DO from "120" to "110" in table 8-2, changed max values for active (operating) current for internal DVDD, EVDD shorted to DVDD, DOVDD=1.8V, 8M@96MHz, all ISP on, DVP out from "TBD" to "80", "15", "150", and "5" in table 8-2, added units, "ma", for active (operating) current for internal DVDD, EVDD shorted to DVDD, DOVDD=2.8V, 8M@576Mbps, 2-lane, all ISP on, MIPI out in table 8-2, added units, "ma", for active (operating) current for internal DVDD, EVDD shorted to DVDD, DOVDD=1.8V, 8M@576Mbps, 2-lane, all ISP on, MIPI out added footnote b to I DD-DO, "indluding I DD-D " in table 8-2, changed typ values for standby current (I DD-SCCB ) from "500" to "450" in table 8-2, changed typ values for standby current (I DD-PWDN ) from "90" to "50" in table 8-3, changed max value for serial interface inputs, YSCL and YSDA (V IH ), from "2.3" to "3.0" PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

130 OV8810 color CMOS 8 megapixel (3264 x 2448) image sensor with OmniBSI technology proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.42

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