SYNCHRONISATION OF THE LHC BETATRON COUPLING AND PHASE ADVANCE MEASUREMENT SYSTEM

Similar documents
Synchronization of single-channel stepper motor drivers reduces noise and interference

ECMA st Edition / June Near Field Communication Wired Interface (NFC-WI)

Chapter 2 Introduction: From Phase-Locked Loop to Costas Loop

EXPERIMENT #9 FIBER OPTIC COMMUNICATIONS LINK

P. Bruschi: Project guidelines PSM Project guidelines.

Communications II Lecture 7: Performance of digital modulation

ECMA-373. Near Field Communication Wired Interface (NFC-WI) 2 nd Edition / June Reference number ECMA-123:2009

FROM ANALOG TO DIGITAL

EXPERIMENT #4 AM MODULATOR AND POWER AMPLIFIER

Proceedings of International Conference on Mechanical, Electrical and Medical Intelligent System 2017

Pattern compensation in SOA-based gates. Article (peer-reviewed)

Pulse Train Controlled PCCM Buck-Boost Converter Ming Qina, Fangfang Lib

LECTURE 1 CMOS PHASE LOCKED LOOPS

Communication Systems. Department of Electronics and Electrical Engineering

Universal microprocessor-based ON/OFF and P programmable controller MS8122A MS8122B

4 20mA Interface-IC AM462 for industrial µ-processor applications

Memorandum on Impulse Winding Tester

Lecture 5: DC-DC Conversion

Programmable DC Electronic Loads 8600 Series

MEASUREMENTS OF VARYING VOLTAGES

ECE3204 Microelectronics II Bitar / McNeill. ECE 3204 / Term D-2017 Problem Set 7

Analog Circuits EC / EE / IN. For

Industrial, High Repetition Rate Picosecond Laser

Programmable DC Electronic Loads 8600 Series

Programmable DC Electronic Load 8600 Series

Investigation and Simulation Model Results of High Density Wireless Power Harvesting and Transfer Method

Signal Characteristics

Demodulation Based Testing of Off Chip Driver Performance

EE 40 Final Project Basic Circuit

Synchronization of the bit-clock in the receiver

Development of Temporary Ground Wire Detection Device

Table of Contents. 3.0 SMPS Topologies. For Further Research. 3.1 Basic Components. 3.2 Buck (Step Down) 3.3 Boost (Step Up) 3.4 Inverter (Buck/Boost)

Optical phase locked loop for transparent inter-satellite communications

ECE ANALOG COMMUNICATIONS - INVESTIGATION 7 INTRODUCTION TO AMPLITUDE MODULATION - PART II

UNIT IV DIGITAL MODULATION SCHEME

RITEC, Inc. 60 Alhambra Rd., Suite 5 Warwick, RI (401) FAX (401) Powerful Ultrasonic Research Tool. A Modular Approach

The ramp is normally enabled but can be selectively disabled by suitable wiring to an external switch.

BOUNCER CIRCUIT FOR A 120 MW/370 KV SOLID STATE MODULATOR

ANALOG AND DIGITAL SIGNAL PROCESSING LABORATORY EXPERIMENTS : CHAPTER 3

Automatic Power Factor Control Using Pic Microcontroller

Generating Polar Modulation with R&S SMU200A

Obsolete Product(s) - Obsolete Product(s)

Solution of ECE 342 Test 2 S12

ELR 9000 Series. Electronic DC Loads with Energy Recovery. 3.5 kw to 10.5 kw THE POWER TEST EXPERTS.

4.5 Biasing in BJT Amplifier Circuits

EE 330 Lecture 24. Amplification with Transistor Circuits Small Signal Modelling

Investigation of Novel Ultrasonic Positioning Method Installed in Sensor Network

f t 2cos 2 Modulator Figure 21: DSB-SC modulation.

Chapter 2 Summary: Continuous-Wave Modulation. Belkacem Derras

Phase-Shifting Control of Double Pulse in Harmonic Elimination Wei Peng1, a*, Junhong Zhang1, Jianxin gao1, b, Guangyi Li1, c

An Improved Zero-Voltage-Transition Technique in a Single-Phase Active Power Factor Correction Circuit

Lecture 11. Digital Transmission Fundamentals

State Space Modeling, Simulation and Comparative Analysis of a conceptualised Electrical Control Signal Transmission Cable for ROVs

A New Electronic Timer. P.L. Nonn and J.C. Sprott. February 1968 PLP 179. Plasma Studies. University of Wisconsin

Study on the Wide Gap Dielectric Barrier Discharge Device Gaofeng Wang

EE201 Circuit Theory I Fall

Power losses in pulsed voltage source inverters/rectifiers with sinusoidal currents

Wrap Up. Fourier Transform Sampling, Modulation, Filtering Noise and the Digital Abstraction Binary signaling model and Shannon Capacity

Power Amplifier EEA-PAM-5**-A-32 for Proportional Control Valves Contents The following power amplifier models are covered in this catalog

PI90LV9637. LVDS High-Speed Differential Line Receivers. Features. Description. Applications PI90LV9637

THE OSCILLOSCOPE AND NOISE. Objectives:

Installation and User Manual

How to Shorten First Order Unit Testing Time. Piotr Mróz 1

Installation and Operating Instructions for ROBA -brake-checker Typ

Lecture #7: Discrete-time Signals and Sampling

10. The Series Resistor and Inductor Circuit

A Bidirectional Three-Phase Push-Pull Converter With Dual Asymmetrical PWM Method

Multiple Load-Source Integration in a Multilevel Modular Capacitor Clamped DC-DC Converter Featuring Fault Tolerant Capability

AN303 APPLICATION NOTE

Accurate Tunable-Gain 1/x Circuit Using Capacitor Charging Scheme

Control circuit for a Self-Oscillating Power Supply (SOPS) TDA8385

A-LEVEL Electronics. ELEC4 Programmable Control Systems Mark scheme June Version: 1.0 Final

Optical Short Pulse Generation and Measurement Based on Fiber Polarization Effects

A1 K. 12V rms. 230V rms. 2 Full Wave Rectifier. Fig. 2.1: FWR with Transformer. Fig. 2.2: Transformer. Aim: To Design and setup a full wave rectifier.

Technology Trends & Issues in High-Speed Digital Systems

Microwave Transistor Oscillator Design

Examination Mobile & Wireless Networking ( ) April 12,

VIPer12ADIP / VIPer12AS

ISSCC 2007 / SESSION 29 / ANALOG AND POWER MANAGEMENT TECHNIQUES / 29.8

Electronic Instrumentation

The design of an improved matched filter in DSSS-GMSK system

Dimensions. Transmitter Receiver ø2.6. Electrical connection. Transmitter +UB 0 V. Emitter selection. = Light on = Dark on

Simulation Series Termination

Architectures for Resource Reservation Modules for Optical Burst Switching Core Nodes *

Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS

MX629. DELTA MODULATION CODEC meets Mil-Std DATA BULLETIN. Military Communications Multiplexers, Switches, & Phones

Design of Power Factor Correction Circuit Using AP1662

TEA2019 CURRENT MODE SWITCHING POWER SUPPLY CONTROL CIRCUIT DIRECT DRIVE OF THE EXTERNAL SWITCHING TRANSISTOR POSITIVE AND NEGATIVE OUTPUT CUR-

Receiver Architectures

Solid-state Multi-functional Timer

Dimensions. Transmitter Receiver ø2.6. Electrical connection. Transmitter +UB 0 V. Emitter selection. = Light on = Dark on

Communication Systems. Communication Systems

Active Filters - 1. Active Filters - 2

A New Voltage Sag and Swell Compensator Switched by Hysteresis Voltage Control Method

MODEL: M6NXF1. POWER INPUT DC Power R: 24 V DC

Dimensions. Model Number. Electrical connection emitter. Features. Electrical connection receiver. Product information. Indicators/operating means


Electrical connection

Estimating Transfer Functions with SigLab

COMBITRON Program Schedule

Transcription:

Proceedings of IBIC214, Monerey, CA, USA MOP4 SYNCHONISATION OF THE BETATON COUPLING AN PHASE AANCE MEASUEMENT SYSTEM J. Olexa, M. Gasior, CEN, Geneva, Swizerland Absrac The new iode Obi and OScillaion (OOS) sysem will provide posiion readings wih submicromere resoluion and a he same ime will be able o perform measuremens of local bearon coupling and phase advance wih micromere exciaion. The oscillaion sub-sysem employs gain-conrolled F amplifiers, shared wih he orbi sysem, and followed by dedicaed diode deecors o demodulae he oscillaion ino he khz frequency range, subsequenly digiized by muli-channel 24-bi ACs. The digial are processed in each fron-end wih an FPGA and he resuls of reduced hroughpu are sen using an Eherne proocol o a common concenraor, ogeher wih he orbi daa. The phase advance calculaion beween muliple Beam Posiion Moniors (s) requires ha all OOS fron-ends have a common phase reference. This paper presens mehods used o generae such a reference and o mainain a sable synchronous sampling on all sysem fron-ends. The performance of he OOS prooype synchronisaion is presened based upon laboraory measuremens. INTOUCTION The OOS sysem has been primarily designed and opimised for from he posiion moniors (s) embedded ino he jaws of he new collimaors [1]. The sysem will provide orbi readings used for he auomaic posiioning of he collimaor jaws symmerically around he, which will reduce he ime needed o se-up he collimaors and poenially improve he collimaion efficiency. The iode Obi (O) sysem will be complemened by iode OScillaion () sub-sysem opimised for he oscillaion. The par will provide daa ha can be used for he measuremen of local bearon coupling and he phase advance beween he s wih micromere exciaion. The simpliciy of he OOS sysem and is already proven sub-micromere orbi resoluion [2] made i a good candidae o complemen he sandard sysem. This sysem was designed for bunch-by-bunch rajecory measuremens and is limied o an orbi resoluion a he micromere level. The OOS sysem will herefore be insalled on all s close o he ineracion poins, where a beer orbi resoluion will help in opimising he collision process. Elecrode of hese s will be passively spli and sen o boh sysems. This way he sandard sysem will provide bunch-by-bunch rajecories while he OOS will measure precisely orbis. In addiion, he par of he OOS phase signal O O O O phase signal SP and Conrol iming Figure 1: Block diagram of a OOS fron-end. Abbreviaions: SC synchronisaion circuis, O diode orbi, diode oscillaion, serial peripheral inerface link. sysem will be capable of providing oscillaion daa wih micromere exciaion for bearon coupling and phase advance measuremens. OOS SYSTEM The OOS fron-ends will be buil as 1U 19 modules disribued around he. Each fron-end is foreseen o process from four pairs. Typically i will be up-sream and down-sream s of wo collimaors or horizonal and verical s of wo sripline s [2]. The block diagram of one OOS fron-end is depiced in in Fig. 1. The channels of each pair provide wo low frequency orbi (O) proporional o he volages, which are produced by compensaed diode deecors [2], and one oscillaion signal (), resuling from he difference of he oscillaion demodulaed by diode peak deecors. All hree are low-pass filered and are digiized by a 24-bi AC a he rae of he revoluion frequency (f rev ) of abou 11.2 khz. The subsequen digial signal (SP) of he samples is implemened in an FPGA. The same FPGA provides he sysem conrol and iming as well as he Eherne communicaion and daa ransmission o a common OOS concenraor. The OOS daa ransmission uses he same Eherne proocol and he 25 Hz frame rae as he sandard sysem. The oal OOS daa hroughpu is abou 4 KB/s per fron-end. 24-bi AC 24-bi AC SC SC iming Eherne 139

MOP4 Proceedings of IBIC214, Monerey, CA, USA In general, each can have slighly differen revoluion frequency and herefore he has wo neworks disribuing he synchronous iming (BST). Since each OOS fron-end is foreseen o process simulaneously from boh s, he digialisaion is done wih wo ACs. As seen in Fig. 1, he ACs are independenly ed wih he obained from dedicaed synchronisaion circuis (SC) blocks, each using an individual iming, which can come from eiher of he iming neworks. The AC seleced for he OOS sysem is of Σ/ archiecure o obain he 24-bi resoluion and excellen lineariy of he conversion. The AC has been chosen for is very good performance for boh C and AC, required for he O and sysems, respecively. In addiion each AC accommodaes 8 simulaneously sampled channels, fiing well o he OOS archiecure. The sub-sysem is based on synchronous demodulaion of he oscillaion [3] resuled from micromere exciaion a a consan frequency f exc, ypically chosen close o he bearon frequency f β, which for he is in he range 3.1 3.6 khz for boh horizonal and verical planes. The oscillaion phase advance is measured wih respec o a local oscillaor (LO) signal having exacly he same f exc frequency as he exciaion. This LO f exc signal is generaed wih a direc digial synhesizer (S) [3] synchronised o a revoluion frequency iming derived from he BST and referred o as iming revoluion frequency, f revt. While he frequency of his signal is guaraneed o be he same in each OOS fron-end, i is no he case for is phase. The phase of f revt in a paricular OOS fron-end depends on is locaion around he and he delay of he BST opical fibre link. Therefore, he f revt signal phase mus be aligned o he same bunch in each fronend, which will be done wih a single bunch circulaing in he machine. If he iming disribuion does no change, in general his alignmen needs o be performed once. This paper describes he circuiry and algorihms ha will allow a reliable phase synchronisaion of he iming f revt derived from he BST, wih he focus on he synchronisaion circuis accommodaed in SC block in Fig. 1. The required accuracy of he phase advance measuremens obained from he daa is in he order of.1º, corresponding o some 8 ns a 3.6 khz, he highes frequency a which he phase advance measuremens will be ypically done. The synchronisaion beween he OOS fron-ends should preferably be much beer, in he order of 8 ns, equivalen o abou.3º a f rev. The described synchronisaion was designed wih he aim of achieving a leas his accuracy. SYNCHONIZATION CICUITS A diagram of he synchronisaion circuis is shown Fig. 2. Is firs block, a Beam Synchronous Timing receiver (BSTrx), decodes he iming, disribued over fibre opics links from a single iming source. The block provides he bunch frequency f F (abou 4.1 MHz) 14 iming BSTrx f F f revt f FPGA LTG PL f revb f reva OOS P P 512 f reva f Y AC MCLK Y Figure 2: OOS synchronisaion circuis. BSTrx synchronous iming receiver, LTG local iming generaor, PL programmable delay line, P differenial phase deecor, MCLK maser, Y daa ready signal. AC + hreshold conrol COMP - FPGA holdoff Figure 3: Block diagram of he Local Timing Generaor (LTG). which is muliplied by a facor of four in an FPGA block o produce he FPGA global f FPGA (abou 16 MHz). The BSTrx block delivers also he earlier inroduced iming revoluion frequency signal f revt, whose phase can be shifed by a Programmable elay Line (PL) o mach he phase of he revoluion frequency reference f revb, which is derived from he. The PL provides he aligned revoluion frequency reference f reva, used as a phase reference for he synchronising he AC sampling signalled by he daaready (Y). The produce a low-jier AC maser (MCLK), whose frequency is 512 imes higher han f reva, ha is abou 5.8 MHz. The is opimised for low jier and is based on a classical archiecure wih a charge-pump phase deecor and a volage conrolled oscillaor (CO) buil as an LC generaor uned wih a varicap diode. The reference f revb is provided by a Local Timing Generaor (LTG), synchronised by he produced by a passive combinaion of he processed, as skeched in Fig. 1. The phase of he iming f revt and f revb is compared in a differenial phase deecor (P). This precise phase deecor is designed in such a way ha is oupu volage read by one dedicaed AC channel has a maximum when he boh inpu are phase-aligned. uring he phase alignmen procedure he delay of he PL is adjused o obain a maximum volage from he P. in 1 in 2 in 3 in 4 in 5 in 6 in 7 hold-off ime conrol o SP f revb

Proceedings of IBIC214, Monerey, CA, USA MOP4 This way he phase-mach condiion does no depend on he inpu offse volage of he AC, which would oherwise cause an imporan error. Local Timing Generaor The phase of he revoluion frequency reference f revt obained from he iming sysem in each OOS fron-end is foreseen o be synchronised wih he wih jus one bunch circulaing in he machine. However, he Local Timing Generaor (LTG), schemaically shown in Fig. 3, is designed o provide a revoluion frequency reference f revb synchronised o he same bunch regardless of he acual bunch configuraion. The LTG employs an asymmery in he bunch rain and locks o he firs bunch following he larges gap in he bunch rain. In he case of he physics he larges gap consiues he so called abor gap, a 3 µs period wih no bunches, corresponding o he riseime of he dump kicker. The operaion of he LTG is based upon bunch derived from he. The are convered ino shor logic by a comparaor and sreched in ime by he following flip-flop. Once he LTG is already locked, he firs bunch afer he larges gap riggers he flip-flop generaing a shor pulse before being auo-rese. The same bunch sars he couner in he holdoff block, reseing also is oupu, which in urn disables he oupu flip-flop. The flip-flop ges enabled afer he holdoff couner reaches he ime falling already in he following bunch gap. The LTG locks o he firs bunch afer he larges gap when he holdoff ime is se as T holdoff T T ΔT (1) rev larges gap 1 where T rev = f rev is he revoluion period of abou 88.9 µs, T larges gap is he ime of he larges gap in he bunch rain and T is a small inerval, ypically a few ns. The operaion of he comparaor can be opimised by changing is hreshold volage hrough a dedicaed AC. Programmable elay Line The phase of he iming revoluion frequency reference f revt can be shifed wih he resoluion much beer han one FPGA using he Programmable elay Line (PL), whose block diagram is shown in Fig. 4. The PL is buil from wo pars: a raw delay, delaying he f revt reference by a programmable number of f F cycles (25 ns) and a fine delay. The fine delay, which can be programmed in 1 ps seps, employs he feaure of an FPGA block, producing a delayed version of he f F iming, which s he raw delay block. ifferenial Phase eecor Since he phase measuremen a he.1 level canno be done wih he FPGA logic, he measuremen is performed wih a specially designed ifferenial Phase eecor (P) buil from discree componens and shown schemaically in Fig. 5, ogeher wih simplified waveforms in he key nodes of he circui. Such a phase deecor delivers a C volage wih he maximum value f revt f F Synch fine delay conrol ff elay raw delay conrol Figure 4: Programmable elay Line (PL). Abbreviaions: Sync synchronisaion circui. in 1 in 2 a 1 a 2 τ b 1 b 2 a b PS NO Figure 5: Block diagram of he ifferenial Phase eecor (P) and simplified waveforms in is key nodes. LP low pass filer. when he rising edges of he a boh P inpus coincide and he volage is digiized by one channel of he OOS AC. The of boh P inpus wo flip-flops producing wo wih 5 % duy cycle, which conserve he delay τ beween he wo inpu. The flip-flops drive he inpus of an O gae, followed by wo XO gaes, working in a buffer and an inverer configuraion, guaranying an equal delay for boh, O and NO oupus. If boh inpu have he same phase (i.e. τ = ), hen he O and NO have equal 5 % duy cycles, which are convered by idenical passive low pass (LP) filers ino volages of exacly equal ampliude. The LP oupu are subraced by a differenial amplifier, whose oupu volage, shifed by he AC reference volage ( ref ), is digiized by one channel of he AC. The differenial amplifier wih he gain of wo is buil as a classical insrumenaion amplifier wih wo op-amps. LP NO c 1 d 1 c 2 d 2 LP O O NO O f reva P e ref c d,e P 141

MOP4 Proceedings of IBIC214, Monerey, CA, USA For τ he O duy cycle increases and NO decreases, resuling in a decrease of he P oupu volage. In general, he P oupu volage P is P ref PS (2) T where PS 3.3 is he power supply of he CMOS XO gaes, defining he oupu high level. PS volage influences he P gain bu i is no he case for τ =, where he P operaion is he mos imporan. In addiion, PS can be measured by one AC channel, which is swiched by an muliplexer beween key nodes of he OOS circuis. Please noe ha according o (2) he phase difference of.1 changes he P oupu volage only by some 9 µ. The P configuraion is he only one found by he auhors which was able o resolve such small phase changes. LABOATOY MEASUEMENTS The OOS synchronisaion was esed in a laboraory wih locally generaed and his paper presens some measuremens of he mos imporan blocks. The funcionaliy of he local iming generaor was esed wih simulaed wih an arbirary waveform generaor in condiions represenaive of s. One such measuremen is shown in Fig. 6, presening he LTG holdoff oupu (op race in blue) riggered upon he firs pulse afer a larger gap in he pulse rain (boom race in magena). The LTG capabiliy of locking o any asymmery in he bunch rain allows permanen monioring of he synchronisaion beween he iming f revt reference and he. The performance of he differenial phase deecor is summarised on he plos in Fig. 7. In he firs measuremen he phase of he P inpu was changed in 2 ps seps. The seps, wih he size seleced for good plo readabiliy, were produced using he programmable delay line, proving is good operaion. The samples of he P oupu were averaged over 4 ms and 1 s inervals, corresponding o he sandard applied o OOS orbi samples. This way he P signal is processed and ransmied along wih oher OOS samples. In he second measuremen he phase of he P inpu was kep consan for some 7 minues. I can be seen ha increasing he sample averaging by a facor of 25, from 4 ms o 1 s, only reduces he peak-peak noise by roughly a facor of 2. This indicaes ha he P oupu noise is dominaed by low frequency conen, which did no average ou well over 1 s periods. The peak-peak noise seen on he races in Fig. 7 is of he order of he 2 ps seps, which corresponds o.8º a f rev. This resoluion is by far sufficien for synchronising he OOS unis, wih he goal of.1º. Please noe ha he phase noise of 2 ps pp corresponds o some 7 µ pp read by he AC a he oupu of he P. 142 rev Figure 6: Laboraory esing of he local iming generaor (LTG). Shown are he inpu and holdoff oupu waveforms in magena and blue, respecively. Figure 7: esponse of he differenial phase deecor upon 2 ps delay seps (in cyan and blue) and he deecor 7 minue sabiliy (in red). The jier of he AC maser was measured o be abou 5 ps MS. Is good qualiy resuled in he sampling jier of abou 3 ps MS, as measured on he daa ready. CONCLUSIONS AN OUTLOOK The iming and synchronizaion circuis are an imporan par of he OOS sysem, paricularly so for he phase advance measuremen sub-sysem. For such measuremens all OOS fron-ends need a common f reva reference wih he phase adjused o he same bunch of he circulaing. However, for he bearon coupling measuremens he phase of he f reva reference in each he sysem fron-ends is no imporan and for he orbi measuremens even is frequency does no maer. For he phase advance measuremens he revoluion frequency reference f revt derived from he iming sysem needs o be aligned o he same bunch. As each filling always sars from an injecion of a low inensiy pilo bunch, his bunch can be used for he

Proceedings of IBIC214, Monerey, CA, USA MOP4 iming alignmen or is verificaion. In addiion, he presened local iming generaor is capable of deriving he revoluion frequency reference from he in pracically all configuraions. This reference can be used for a coninuous monioring of he phase of he adjused iming reference f reva by comparing he wo using he differenial phase deecor, whose oupu is digiized in parallel o all oher OOS channels. The presened differenial phase deecor allows measuremens wih a resoluion in he order of.1º while he programmable delay line allows a fine adjusmen of he iming f rev reference in 1 ps seps. Boh values are by far sufficien for achieving he synchronisaion beween he OOS unis a he.1º level. Afer he resar in 215 he embedded s of he 18 new collimaors will operae wih he OOS sysem. In addiion, OOS fron-ends will be insalled on seleced s close o he experimens, operaing in parallel o he sandard elecronics. This firs OOS operaional insallaion, conaining a few ens of fron-ends, will allow is sysemaic esing and opimisaion of is hree measuremen modes: orbi, local coupling and phase advance. The phase advance will be a real es bed for he performance of he presened OOS synchronisaion. EFEENCES [1] C. Boccard e al., Embedded collimaor posiion moniors, Proceedings of IPAC 211, Hamburg, Germany, CEN-BE-211-23. [2] M. Gasior e al., elecronics based on compensaed diode deecors resuls from developmen sysems, Proceedings of BIW 212, Newpor News, A, USA, CEN-ATS-212-247. [3] J. Olexa e al., Prooype sysem for phase advance measuremens of small oscillaions, Proceedings of MAEW 213, Pardubice, Czech epublic, CEN-ATS-213-38. 143