1 The Differential Amplifier Asst. Prof. MONTREE SRPRUCHYANUN, D. Eng. Dept. of Teacher Training in Electrical Engineering, Faculty of Technical Education King Mongkut s nstitute of Technology North Bangkok http://www.te.kmitnb.ac.th/msn mts@kmitnb.ac.th 1 BJT Differential Pair Differential pair circuits are one of the most widely used circuit building blocks. The input stage of every op amp is a differential amplifier Basic Characteristics Two matched transistors with emitters shorted together and connected to a current source Devices must always be in active mode Amplifies the difference between the two input voltages, but there is also a common mode amplification in the nonideal case α/2 α/2 -α /2 -α /2 /2 /2 v CM v CM - 0.7 Let s first qualitatively understand how this circuit works. NOTE: This qualitative analysis also applies for MOSFET differential pair circuits 224510 Advanced communication circuit design 2
2 Case 1 Assume the inputs are shorted together to a common voltage, v CM, called the common mode voltage equal currents flow through Q 1 and Q 2 emitter voltages equal and at v CM -0.7 in order for the devices to be in active mode collector currents are equal and so collector voltages are also equal for equal load resistors difference between collector voltages = 0 -α /2 α/2 Q 1 Q 2 /2 /2 α/2 -α /2 What happens when we vary v CM? As long as devices are in active mode, equal currents flow through Q 1 and Q 2 Note: current through Q 1 and Q 2 always add up to, current through the current source So, collector voltages do not change and difference is still zero. Differential pair circuits thus reject common mode signals v CM v CM - 0.7 224510 Advanced communication circuit design 3 Case 2 & 3 Q 2 base grounded and Q 1 base at +1 V All current flows through Q 1 No current flows through Q 2 Emitter voltage at 0.3V and Q 2 s EBJ not FB v C1 = -α v C2 = -α +1V α 0 Q 1 Q 2 0-1V 0 α -α Q 1 Q 2 0 Q 2 base grounded and Q 1 base at -1 V All current flows through Q 2 No current flows through Q 1 Emitter voltage at -0.7V and Q 1 s EBJ not FB 0.3V -0.7V v C2 = -α v C1 = 224510 Advanced communication circuit design 4
3 Case 4 Apply a small signal v i Causes a small positive Δ to flow in Q 1 Requires small negative Δ in Q 2 since E1 + E2 = Can be used as a linear amplifier for small signals (Δ is a function of v i ) Differential pair responds to differences in the input voltage Can entirely steer current from one side of the diff pair to the other with a relatively small voltage Let s now take a quantitative look at the large-signal operation of the differential pair 224510 Advanced communication circuit design 5 BJT Diff Pair Large-Signal Operation First look at the emitter currents when the emitters are tied together Some manipulations can lead to the following equations and there is the constraint: Given the exponential relationship, small differences in v B1,2 can cause all of the current to flow through one side 224510 Advanced communication circuit design 6
4 Notice v B1 -v B2 ~= 4V T enough to switch all of current from one side to the other For small-signal analysis, we are interested in the region we can approximate to be linear small-signal condition: v B1 -v B2 < V T /2 224510 Advanced communication circuit design 7 BJT Diff Pair Small-Signal Operation Look at the small-signal operation: small differential signal v d is applied multiply top and bottom by expand the exponential and keep the first two terms 224510 Advanced communication circuit design 8
5 Differential Voltage Gain For small differential input signals, v d << 2V T, the collector currents are We can now find the differential gain to be 224510 Advanced communication circuit design 9 BJT Diff Pair Differential Half Circuit We can break apart the differential pair circuit into two half circuits which then looks like two common emitter circuits driven by +v d /2 and v d /2 Virtual Ground 224510 Advanced communication circuit design 10
6 Small-Signal Model of Diff Half Circuit We can then analyze the small-signal operation with the half circuit, but must remember parameters r π,g m, and r o are biased at / 2 input signal to the differential half circuit is v d /2 v d /2 r π v π g m v π r o v c1 voltage gain of the differential amplifier (output taken differentially) is equal to the voltage gain of the half circuit 224510 Advanced communication circuit design 11 Common-Mode Gain When we drive the differential pair with a common-mode signal, v CM, the incremental resistance of the bias current effects circuit operation and results in some gain (assumed to be 0 when R was infinite) 224510 Advanced communication circuit design 12
7 Common Mode Rejection Ratio f the output is taken differentially, the output is zero since both sides move together. However, if taken single-endedly, the common-mode gain is finite f we look at the differential gain on one side (single-ended), we get Then, the common rejection ratio (CMRR) will be which is often expressed in db 224510 Advanced communication circuit design 13 CM and Differential Gain Equation nput signals to a differential pair usually consists of two components: common mode (v CM ) and differential(v d ) Thus, the differential output signal will be in general 224510 Advanced communication circuit design 14
8 MOS Diff Pair The same basic analysis can be applied to a MOS differential pair and the differential input voltage is With some algebra 224510 Advanced communication circuit design 15 We get full switching of the current when 224510 Advanced communication circuit design 16
9 Another Way to Analyze MOS Differential Pairs Let s investigate another technique for analyzing the MOS differential pair For the differential pair circuit on the left (driven by two independent signals), compute the output using superposition Start with V in1, set V in2 =0 and first solve for X w.r.t. V in1 Reduces to a degenerated common-source amp neglecting channel-length modulation and bodyeffect, R S = 1/g m2 so V in1 V in1 V out1 V out1 X Y V out2 X Y V out2 M 1 M 2 V in2 V in1 V out1 V in1 V out1 X Y V out2 X R S R S 224510 Advanced communication circuit design 17 Cont d Now, solve for Y w.r.t. V in1 Replace circuit within box with a Thevenin equivalent M 1 is a source follower with V T =V in1 R T =1/g m1 The circuit reduces to a common-gate amplifier where V out1 X Y V out2 M 1 M 2 V in1 So, overall (assuming g m1 = g m2 ) by symmetry Y V out2 R T V T 224510 Advanced communication circuit design 18
10 Differential Pair with MOS loads Can use load resistors or MOS devices as loads Diode-connected nmos loads = 1/g m load resistance Load resistance looking into the source Diode-connected pmos loads = 1/g m load resistance Load resistance looking into diode connected drain pmos current source loads = r o load resistance Has higher gain than diode-connected loads pmos current mirror Differential input and single-ended output 224510 Advanced communication circuit design 19 Differential Pair with MOS Loads V b V out V out V in V in Consider the above two MOS loads used in place of resistors Left: a diode connected pmos has an effective resistance of 1/g mp Right: pmos devices in saturation have effective resistance of r op 224510 Advanced communication circuit design 20
11 Active-Loaded CMOS Differential Amplifier A commonly used amplifier topology in CMOS technologies Output is taken single-endedly for a differential input with a v id /2 at the gate of M1, i 1 flows M3 M4 i 1 i 1 is also mirrored through the M3-M4 current mirror a v id /2 at the gate of M2 causes i 2 to also flow through M2 i 1 i 2 v o M1 M2 v id Given that D = / 2 (nominally) The voltage at the output then is given by 224510 Advanced communication circuit design 21 Differential Amp with Linearized Gain Use source generation to make the gain linear with respect to the differential input and independent of g m Can build in two ways 224510 Advanced communication circuit design 22
12 Assuming a virtual ground at node X, we can draw the following small-signal half circuit. v id v π g m v π r o v ο i s R S v S Assume r o is very large (simplifies the math) 224510 Advanced communication circuit design 23 Offsets in MOS Differential Pair There are 3 main sources of offset that affect the performance of MOS differential pair circuits Mismatch in load resistors Mismatch in W/L of differential pair devices Mismatch in V th of differential pair devices Let s investigate each individually 224510 Advanced communication circuit design 24
13 Resistor Mismatch For the differential pair circuit shown, consider the case where Load resistors are mismatched by Δ 1 2 V O All other device parameters are perfectly matched With both inputs grounded, 1 = 2 = /2, but V O is not zero due to differences in the voltages across the load resistors 1 2 t is common to find the input-referred offset which is calculated as since A d = g m 224510 Advanced communication circuit design 25 W/L Mismatch Now consider what happens when device sizes W/L are mismatched for the two differential pair MOS devices M1 and M2 This mismatch causes mismatch in the currents that flow through M1 and M2 This mismatch results in V O So in the input referred offset is 224510 Advanced communication circuit design 26
14 V t Mismatch Lastly, consider mismatches in the threshold voltage Again, currents 1 and 2 will differ according to the following saturation current equation For small ΔV t << 2(V GS -V th ) Again, using V OS =V O /A d (A d = g m and V O =2Δ ) we get 224510 Advanced communication circuit design 27 Mismatch Summary The 3 sources of mismatch can be combined into one equation: arising from V t,, and W/L mismatches Notice that offsets due to Δ and ΔW/L are functions of the overdrive voltage V GS V t 224510 Advanced communication circuit design 28