International Global Navigation Satellite Systems Society IGNSS Symposium 2013 Outrigger Gold Coast, Qld Australia 16-18 July, 2013 Monolithic Integrated RF Front ends for Multi-GNSS receivers K. J. Parkinson (1) E. Glennon (2) Nagaraj C. Shivaramaiah (3) Andrew G. Dempster (4) Chris Rizos (5) School of Surveying and Spatial Information Systems, University of New South Wales, Sydney, 2052, Australia Email for corresponding author: k.parkinson@unsw.edu.au ABSTRACT The continuing expansion of available GNSS signals is an increasing challenge for receiver designers. New signals with expanded bandwidths are demanding greater sampling rates that require careful design of the receiver RF section to maximise performance tradeoffs. A high level of integration is required to preserve signal path integrity and minimise noise while keeping power consumption to a minimum. The design of the frequency plan and the choice of IF bandwidth are critical to overall receiver performance. This paper describes the development of the monolithic RF front end chips used in the new Namuru multi- GNSS receivers at UNSW. Analysis of the system requirements and architecture design are discussed including the LNA, Mixer, IF Amplifier through to the A/D converter. The re-configurable design provides frequency plan and signal selection flexibility using an integrated synthesiser and programmable bandwidth filter. The design challenges of the new front end chips are discussed including features aimed at delivering greater performance and flexibility. KEYWORDS: Front end, RF, GNSS.
1 INTRODUCTION For the past several years we have been made increasingly aware of new proposed GNSS signals that will quadruple the number of available satellite navigation systems in the near future. These new systems include the modernisation of the United States GPS (NAVSTAR), Russia s revamped GLONASS, Europe s GALILEO system, and China s planned COMPASS system (W. De_Wilde, et al., 2007; G. X. Gao, et al., 2007). Regional Navigation Satellite Systems for augmentation are also planned from both Japan (Japan Aerospace Exploration Agncy, 2010) and India (K. N. Suryanarayana Rao and S. Pal, 2004). This will expand the available signals beyond the legacy GPS L1 at 1575.42MHz with significant opportunities to improve GNSS receiver performance. In some cases the receiver may only use an optimal subset of available signals, while in others any number of signals may be used. In the past, non-military GNSS users have been restricted to the use of the L1 frequency, the largest users being in the area of consumer electronics products like mobile phones and vehicle navigation units etc. High performance precise positioning is not generally required in these applications, although some may add dual frequency capability in future where power consumption is not a great concern. 2 ADVANTAGES OF MULTI-GNSS RECEIVERS It is likely that several clear benefits will be gained through the use of more than one GNSS system in a receiver. 2.1 Use of Multiple Frequencies The current method of modelling the L1 signal propagation through the ionosphere is to use the signal path specific data transmitted by each GNSS satellite. The U.S. military and allies have enjoyed the exclusive benefit of using a dual frequency approach to solve this problem from the outset of NAVSTAR GPS. This is achieved through the use of the encrypted L2 signal at 1227.6 MHz. Using new civilian signals from multiple systems, the dual frequency dispersive delay technique can be exploited to more accurately estimate ionosphere propagation delay (M. S. Grewal, et al., 2001). 2.2 Reduction of Signal Blockage When operating in urban canyons and under wooded areas, some satellites are inevitably blocked or the signal is severely attenuated. Because the GNSS function relies heavily upon Line Of Sight (LOS) signals, performance quickly degrades under these conditions. With a greater number of satellites to choose from this problem could be reduced by dynamically selecting alternative more visible satellites. 2.3 Use of Carrier Phase
Rapid and reliable resolution of ambiguities in carrier phase measurements is required for high-accuracy differential positioning which requires dual, and ideally triple, frequency measurements. Because of the improved modulation schemes combined with the use of more than one frequency, coherent integration of the signal carrier for longer periods will allow better phase tracking at lower signal thresholds leading to improved performance. Low noise carrier phase measurement is critical for rapid ambiguity resolution and superior GNSS performance. 2.4 Increased Integrity and robustness Improved modulation schemes proposed in the new GNSS systems are aimed at decreasing the possibility of acquiring the wrong signals because of a greater isolation between the modulation codes across multiple systems. This will lead to more robust performance overall when multiple signals are used. 2.5 Multi-path mitigation Multipath signals remain a constant source of GNSS errors that cannot be easily removed (M. S. Braasch, 1996). Similar to the above description, the enhanced modulation schemes in the new signals will deliver wider bandwidth leading to better multi-path mitigation as explained in (E. D. Kaplan and C. J. Hegarty, 2006). 2.6 Anti-jamming and security Frequency diversity will become available with the extra signals. Use of this procedure leads to better integrity by allowing the receiver to shift to an alternate frequency at times when in-band radio frequency interference (RFI) such as jamming may occur (P. Misra and P. Enge, 2001). 3 RECEIVER ARCHITECTURE 3.1 Overview GNSS relies on a sensitive receiver capable of capturing very weak signals (of approximately -140dB) from four or more satellites in order to obtain a threedimensional position on the earth in real time. Code Division Multiple Access (CDMA) signals arrive at the earth's surface from the satellites at very low levels, typically 10-20 db below the atmospheric noise. In a typical GNSS receiver (Figure 1), a low-noise Radio Frequency (RF) down-converter Application Specific Integrated Circuit (ASIC) captures these signals, amplifies, filters, and quantises them (converts to digital bits). The information is then passed through a base-band signal processing chain ASIC, operating at a lower frequency, to recover the usable data from the background noise and finally to determine the user position using software algorithms.
Figure 1. Typical GPS receiver architecture. 3.2 RF Down-converter ASIC The RF ASIC (Chip) commonly employs a heterodyne down-conversion technique to translate the GNSS signal to lower Intermediate Frequencies (IF) using mixing techniques where lower Q filters can be more effectively applied to achieve the required selectivity. In the interest of minimising costs, many existing L1 heterodyne architectures use a single down-conversion following a Low Noise Amplifier (LNA) to a low IF frequency giving the benefit of lower cost, lower power consumption and easier IF filter design. A typical heterodyne GNSS RF down-converter is shown in (Figure 2). Figure 2. RF Down-converter.
The frequency translation used in the mixing process generates two frequencies located symmetrically above and below the Voltage Controlled Oscillator (VCO) frequency. These are known as image frequencies and both are converted to the same IF centre to become the signal of interest. Only one of these signals is required and is normally selected by the use of a Band Pass Filter (BPF) following the mixer. A pre-filter BPF is also often used before the mixer as shown in (Error! Reference source not found.) to select the desired GNSS signal and to help reject out-of-band interference. 4 DESIGN CHALLENGES The design of a GNSS RF down-converter chip for access to multiple frequencies and expanded bandwidth presents a number of challenges. 4.1 Related RF Parameters While only a fraction of the electronics in a GNSS receiver is dedicated to the task of the RF down-converter chip, it nevertheless remains critical to overall performance. RF down-conversion techniques used in GNSS receivers have thus far been heavily borrowed from similar architectures in communications systems (K. Feher, 1995; A. Goldsmith, 2005). While some of these can be relaxed for general communications applications, a number of inter-related RF down-converter parameters as shown in (Table 1) are critical to GNSS receiver performance. Compromises in these areas have often been made in mass market down-converter chips to save costs where better performance is not required. Table 1. GNSS Down-converter parameters. Paramater Affected performance Noise figure System sensitivity & Signal-to-noise ratio Frequency plan Image rejection & Interference rejection IF Topology Noise, Imgage rejection & Intermodulation distortion LNA type Signal-to-noise ratio & Intermodulation distortion Mixer type VCO leakage, Signal-to-noise ratio & Intermodulation distortion VCO leakage Local interference & Intermodulation distortion IF bandwidth Image rejection, Selectivity & Interference rejection VCO Phase noise Signal-to-noise ratio Intermodulation Signal-to-noise ratio & Dynamic range Dynamic range Sensitivity & Interference tolerance Power consumption Signal-to-noise ratio & Dynamic range Cross modulation Signal-to-noise ratio & Dynamic range Linearity Signal-to-noise ratio & Interference tolerance 4.2 VCO Phase noise
Low VCO phase noise is essential to avoid increasing receiver system noise by generating unwanted inter-modulation products from the mixer in the heterodyne downconversion process. The 3 rd order products between the signal and the VCO appear within a range of 3 times the bandwidth while the 5 th order products appear within 5 times etc. In cases where the down-conversion ends at a low IF, products fall more easily into the filter pass-band and downwardly affect the GNSS measurements. This is often ignored when measurements such as carrier phase are not required. As bandwidth increases it becomes a challenge to minimise VCO phase noise and the follow on effects of intermodulation products on GNSS measurements. 4.3 Additional bandwidth The legacy L1 GPS signal occupies a 2 MHz bandwidth around a centre frequency of 1575.42 MHz. The bandwidth required to cope with the new signals will expand by a factor of up to 25 times to reach 50 MHz. This is a challenge while maintaining optimal weak signal performance in a GNSS receiver because one of the largest contributors to poor performance is introduced receiver noise, which adversely affects the overall signalto-noise measurement. This is downwardly affected as bandwidth is increased which is a typical communications problem (J. F. DeRose, 1999). 4.4 Additional frequencies As the number of frequencies expand and the bandwidth requirements increase, the filter requirements become more demanding. In any communications application it is desirable to maintain the minimum possible bandwidth without compromising the level of available signal power, thus maintaining the best possible Signal to Noise Ratio (SNR) (A. Goldsmith, 2005). However, it is undesirable to trade off SNR for the flexibility of bandwidth that spans all frequencies of interest (L1 to L5). In most cases these demands can be met through the use of multiple filters in the down-conversion signal path, providing that the group delay across the pass band can be kept to a minimum to avoid impacting the quality of carrier phase measurements (D. K. Shaeffer, et al., 1998). 5 RF CHIP DESIGN The goal of the chip design is to integrate the RF down-conversion functions as much as possible onto a single chip with the flexibility to select different frequencies and bandwidths. As a first step two different chips have been designed using the heterodyne architecture described. Both chip designs have been kept fully differential to gain the benefits of immunity to power supply noise and reduced distortion with the absence of even order harmonics (B. Razavi, 2001). Both chips are fabricated in 0.13um RFCMOS on a single die and bonded out to an industry standard Quad Flatpack with No pins (QFN) package. 5.1 Single Frequency The single frequency chip is designed using a single down-conversion architecture to
receive one GNSS band and is used as a step towards a dual frequency chip. It contains features required to extend GNSS down-conversion to greater bandwidths while allowing access to all proposed GNSS signals. An overview of the chip is shown in (Figure 3). MIXER IF RF IN 2 Bit A/D MAG SIGN LNA IF AMP AGC /2 vco Synthesiser and PLL REF INPUT SPI Control Figure 3. Single channel wide band GNSS RF Front end. SPI The chip allows IF bandwidths of 4MHz and 24MHz through the use of an integrated complex elliptical filter following the mixer. The AGC range is almost 60dB with a 2 bit ADC delivering sign and mag outputs. The overall gain is ~75dB with a system noise figure of 3.9dB. The final IF frequency is either 4MHz or 12MHz sampled at 32.736MHz. 5.2 Dual Frequency The dual frequency chip is designed using a double down-conversion architecture to receive two GNSS bands while combing many of the features of the single band chip. It also contains features required to extend GNSS down-conversion to greater bandwidths while allowing access to all proposed GNSS signals. An overview of the chip is shown in (Figure 4)
MIXER MIXER IF RF IN 3 Bit A/D LNA AGC /N Power Control vco /N PD BUF SPI Control REF INPUT SPI /N /N IF RF IN 3 Bit A/D LNA MIXER MIXER AGC Figure 4. Dual Channel GNSS RF Front end. The chip provides a fixed IF bandwidth of 32MHz through the use of integrated complex elliptical filters following the mixers. The AGC range is almost 60dB with a 3 bit ADC delivering sign and mag outputs. The overall gain is ~75dB with a system noise figure of 6.9dB. The final IF frequency is 16MHz sampled at 32MHz. 5.3 RF Section The aim of the RF amplifier (LNA) and mixer shown is to amplify the incoming signal to minimise the noise contributions of the down stream stages without degrading the system linearity. The amplifier is constructed using a differential pair of transistors combined with a cascode pair to improve input/output isolation. Inductors in each source element compensate for the largely capacitive input impedance and improve linearity. An external matching network in the form of a small inductor is required to couple an external Surface Acoustic Wave (SAW) input filter or LNA to the nominal 100 ohm balanced input impedance. The external inductor is minimised by making use of the inductive nature of the bond out wire and the QFN package. The frequency mixer, which follows directly after the amplifier, adapts a commonly used active Gilbert Cell architecture (T. H. Lee, 2004). The Gilbert core of the mixer is obtained from the switching stage which is optimised for linearity and noise performance while the output stage is built using a resistive output amplifier.
5.4 Phase Locked Loop (PLL) The PLL section includes a VCO, a low pass filter, a Phase Frequency Detector (PFD) and a flexible pre-scaler. The VCO is built using a cross-coupled negative-gm architecture with a matrix of switched elements to allow precise tuning of the VCO across a range of frequencies. A dual modulus pre-scaler is fed to a high speed divider from the VCO followed by a standard CMOS cell based divider chain. The PFD uses a typical dual flip-flop design with a divide by 2 pre-scaler on the incoming reference. This allows for some flexibility of reference frequency choice but the nominal choice of reference is 16.368MHz from a good quality TCXO of +/-1ppm/ o C. In the single frequency chip the VCO runs at twice the injection frequency which eliminates the leakage of the VCO signal into the mixer that can translate into self mixing products resulting in a DC offset. The downside is that the VCO consumes more power. In the dual frequency chip the VCO runs at half that of the single frequency chip to reduce power consumption. In this case the mixer injection delivers a much greater first IF frequency of 150MHz which reduces the risk of VCO mixer leakage by having a much greater frequency offset. The VCO injects on the low side of both mixers and relaxes power consumption. 5.5 IF Section Non-saturating differential IF amplifier stages have been used to minimise cross talk noise and power supply sensitivity. Switched tuning capacitors are used to select the bandwidth in the single conversion chip. The capacitors are also switched to allow trimming adjustments of the filter corner frequencies. The Variable Gain Amplifier (VGA) is built using four stages of differential amplifiers each with three steps of gain giving an overall control range of 60dB. This is followed by a fixed gain output stage leading to the Analog to Digital Converter (ADC). The overall system gain is about 75dB. The integrated ADC uses a pipelined six stage architecture with a latched output buffer. The ADC sample rate is programmable allowing for the use of IF under sampling techniques. In each case the raw IF signal before the ADC is brought out from the chip on separate pins. 5.6 Digital section The standard digital Serial Peripheral Interface (SPI) bus is used to externally load a set of registers to control the operation of the chip. Features including band selection, filter parameters, pre-scaler settings and PLL parameters are all programmable via this bus. All of this logic is built in standard CMOS cells. 6 RESULTS
Both chips have been used to fabricate a test GNSS receiver on a multi-layer FR4 printed circuit board. The associated TCXO, power supply and supporting digital chips have been included on the receiver. 6.1 Single frequency chip The test results for the single frequency RF down-converter are shown in (Table 2). The measurements show acceptable performance. Table 2. Single frequency test results. Parameter L5/E5a L2 L1 Frequency 1176.45 MHz 1227.6 MHz 1575.42 MHz NF 3.9dB 4dB 7dB Gain 75dB 74dB 75dB VSWR In 1.5:1 1.45:1 1.52:1 Power 0.6W 0.6W 0.6W IP3-17dB -17.5dB -18dB PN 100KHz -107dB/Hz -110dB/Hz -117dB/Hz 6.2 Dual frequency chip The test results for the single frequency RF down-converter are shown in (Table 3). As expected, power consumption is greater with the extra circuitry operating. VCO phase noise is also not as good as low the single channel chip due to the VCO operating without the divider before injecting into the mixer. Table 3. Dual frequency test results. Parameter L5/E5a L2 L1 Frequency 1176.45 MHz 1227.6 MHz 1575.42 MHz NF 6.9dB 6.8dB 7dB Gain 75dB 74dB 75dB VSWR In 1.5:1 1.5:1 1.5:1 Power 1W 1W 1W IP3-17dB -17.5dB -18dB PN 100KHz -94dB/Hz -95dB/Hz -97dB/Hz 7 CONCLUSIONS In this paper, the development of the monolithic RF front end chips used in multi-gnss receivers at UNSW has been described. Analysis of the system requirements and architecture design has been presented. The development of two RF front end chips has
been described including the LNA, Mixer, IF Amplifier through to the A/D converter. The re-configurable designs allow a flexible frequency plan for signal selection using an integrated synthesiser and programmable bandwidth filter. The design challenges of the new front end chips have been discussed including features aimed at delivering greater flexibility. While the results show the noise figure of the dual channel chip to be greater than the single channel chip, this can be explained by the fact that the overall power consumption is greater leading to increased system noise. The resulting noise figure is still within acceptable bounds although there are areas that can be improved and will be investigated further. ACKNOWLEDGEMENTS This work is supported by the GARADA project entitled SAR Formation Flying at the Australian Centre for Space Engineering Research (ACSER), partially funded by the DSTO Biarri project and the Satellite Navigation and Positioning Laboratory (SNAP) at the University of New South Wales (UNSW). REFERENCES Braasch, M.S. (1996) Multipath Effects. in Parkinson, B.W. and Spilker, J.J. eds. Global Positioning System: Theory and Applications, Vol 1 American Institute of Aeronautics and Astronautics, Washington DC. De_Wilde, W., Boon, F., Sleewaegen, J.-M. and Wilms, F. (2007) More Compas Points Inside GNSS, July August Derose, J.F. (1999) The Wirless Data Handbook. John Wiley & Sons. Feher, K. (1995) Wireless Digital Communication: Modulation & Spread Spectrum Applications. Prentice-Hall. Gao, G.X., Chen, A., Lo, S., De_Lorenzo, D. and Enge, P. (2007) GNSS over China Inside GNSS (July/August) Goldsmith, A. (2005) Wireless Communications. Cambridge University Press, New York. Grewal, M.S., Weill, L.R. and Andrews, A.P. (2001) Global Positionaling Systems, Inertial Navigation, and Integration. John Wiley & Sons Inc, New York. Japan Aerospace Exploration Agncy.(2010) IS-QZSS_1.2 Kaplan, E.D. and Hegarty, C.J. (2006) Understanding GPS Principles and Applications. Artech House Inc. Lee, T.H. (2004) The Design of CMOS Radio-frequency Integrated Circuits. Cambridcge
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