ACPL-M7L Single-channel High Speed MBd CMOS optocoupler with Glitch-Free Power-Up Feature Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxe denotes a lead-free product Description The ACPL-M7L (single-channel) is MBd CMOS optocouplers in SOIC- package. The optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of ACPL-M7L are high speed LEDs and CMOS detector ICs. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. Component Image Anode Cathode SHIELD A.uF bypass capacitor must be connected between pins 4 and 6. LED OFF ON ACPL-M7L TRUTH TABLE, OUTPUT H L 6 4 Vdd Vo Gnd Features +.V and + V CMOS compatibility 2ns max. pulse width distortion ns max. propagation delay 4ns max. propagation delay skew High speed: MBd min kv/µs minimum common mode rejection 4 to C temperature range Glitch-Free Power-UP Feature Safety and regulatory approvals: - UL recognized: 7 V rms for min. per UL 77 - CSA component acceptance Notice # - IEC/EN/DIN EN 6747-- approved Option 6 Applications Digital field bus isolation: - RS48, RS22, CANbus Multiplexed data transmission Computer peripheral interface Microprocessor system interface DC/DC converter Servo Motor CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information ACPL-M7L will be UL Recognized with 7 Vrms for minute per UL77. Part number ACPL-M7L Option RoHS Compliant -E Package Surface Mount Tape& Reel X IEC/EN/DIN EN 6747-- Quantity per tube -E X X per reel SO- -6E X X per tube -6E X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-M7L-E to order product of Small Outline SO- package in Tape and Reel packaging in RoHS compliant. Example 2: ACPL-M7L-E to order product of Small Outline SO- package in tube packaging and in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Dimensions ACPL-M7L (JEDEC MO- Package) LAND PATTERN RECOMMENDATION Device Part Number 4.4 ±. (.7 ±.4) Lead Free NNNN Z YYWW EEE Test Rating Code 7. ±.2 (.276 ±.8) Date Code. (.) 4.9 (.7).27 (.).64 (.2) 8.26 (.2) Pin Dot.6 ±.* (.42 ±.4) Lot ID.4 ±. (.6 ±.2) 2.4 (.).8 (.7) 2. ±. (.98 ±.4).2 ±.2 (.4 ±.4). ±.2 (.6 ±.).27 (.) BSC.7 (.28) MIN 7 MAX. Dimensions in millimeters (inches). Note: Foating Lead Protrusion is. mm (6 mils) max. MAX. LEAD COPLANARITY =.2 (.4) 2 * Maximum Mold flash on each side is. mm (.6).
Regulatory Information The ACPL-M7L has been approved by the following organizations: UL Recognized under UL 77, component recognition program, File E6. CSA IEC/EN/DIN EN 6747-- Insulation and Safety Related Specifications Approved under CSA Component Acceptance Notice #, File CA8824. Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(I) mm Measured from input terminals to output terminals, shortest distance through air. L(I2) mm Measured from input terminals to output terminals, shortest distance path along body..8 mm Insulation thickness between emitter and detector; also known as distance through insulation. CTI 7 Volts DIN IEC 2/VDE Part Isolation Group IIIa Material Group (DIN VDE, /89, Table ) All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. IEC/EN/DIN EN 6747-- Insulation Related Characteristics (Option 6) Description Symbol option 6 Units Installation classification per DIN VDE /.89, Table for rated mains voltage V rms for rated mains voltage V rms Climatic Classification //2 Pollution Degree (DIN VDE /.89) 2 Maximum Working Insulation Voltage V IORM 67 V PEAK I-IV I-III Input to Output Test Voltage, Method b V IORM x.87 = V PR, % Production Test with t m = sec, Partial Discharge < pc Input to Output Test Voltage, Method a V IORM x.6 = V PR, Type and Sample Test, t m = sec, Partial Discharge < pc Highest Allowable Overvoltage (Transient Overvoltage, t ini = 6 sec) V PR 6 V PEAK V PR 97 V PEAK V IOTM 6 V PEAK Safety Limiting Values (Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure.) Case Temperature Input Current Output Power T s I s, INPUT Ps,OUTPUT Insulation Resistance at T S, V = V R IO 9 Ω 6 C ma mw
Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T S +2 C Ambient Operating Temperature T A 4 + C Supply Voltages V DD 6. Volts Output Voltage. V DD +. Volts Average Forward Input Current I F -. ma Average Output Current I o -. ma Lead Solder Temperature 26 C for sec.,.6 mm below seating plane Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature T A 4 + C Supply Voltages V DD 4.. V..6 V Input Current (ON) I F 4 8 ma Forward Input Voltage (OFF) V F(OFF).8 V Supply Voltage Slew Rate [] S R. V/ms Electrical Specifications Over recommended temperature (T A = 4 C to + C),.V V DD.6V and 4. V V DD. V. All typical specifications are at T A =+2 C, V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Input Forward Voltage V F...8 V I F = 6mA Input Reverse Breakdown Voltage BV R. V I R = µa Logic High Output Voltage H V DD - V DD -. V I F =, I O = -4 ma, V DD =.V V DD - V DD -.2 V I F =, I O = -4 ma, V DD =V Logic Low Output Voltage L.2.8 V I F = 6mA, I O = 4mA, V DD =.V..8 V I F = 6mA, I O = 4mA, V DD =V Input Threshold Current I TH ma I OL = 2 µa Logic Low Output Supply Current I DDL 4. 6. ma I F = 6 ma Logic High Output Supply Current I DDH 4 6 ma I F = 4
Switching Specifications Over recommended temperature (T A = 4 C to + C),.V V DD.6V and 4. V V DD. V. All typical specifications are at T A =+2 C, V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time t PHL 2 ns I F = 6mA, C L = pf to Logic Low Output [2] CMOS Signal Levels Propagation Delay Time t PLH 2 ns I F = 6mA, C L = pf, to Logic High Output [2] CMOS Signal Levels Pulse Width t PW 66.7 ns Pulse Width Distortion [] PWD 4 2 ns I F = 6mA, C L = pf, CMOS Signal Levels Propagation Delay Skew [4] t PSK 4 ns I F = 6mA, C L = pf CMOS Signal Levels Output Rise Time (% 9%) Output Fall Time (9% - %) t R. ns I F = 6mA, C L = pf CMOS Signal Levels t F. ns I F = 6mA, C L = pf CMOS Signal Levels Common Mode Transient CMH kv/µs V CM = V, T A = 2 C, Immunity at Logic High Output [] I F = ma (Figure 8) kv/µs Using Avago s Application Circuit (Figure ) Common Mode Transient CML kv/µs V CM = V, T A = 2 C, Immunity at Logic Low Output [6] I F = 6 ma (Figure 8) kv/µs Using Avago s Application Circuit (Figure ) Package Characteristics All Typical at T A = 2 C. Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Insulation I I-O. µa 4% RH, t = s V I-O = kv DC, T A = 2 C Input-Output Momentary Withstand Voltage V ISO 7 Vrms RH %, t = min., T A = 2 C Input-Output Resistance R I-O 2 W V I-O = V dc Input-Output Capacitance C I-O.6 pf f = MHz, T A = 2 C Notes:. Slew rate of supply voltage ramping is recommended to ensure no glitch more than V to appear at the output pin. 2. t PHL propagation delay is measured from the % V DD level on the rising edge of the input pulse to the % V DD level of the falling edge of the signal. t PLH propagation delay is measured from the % V DD level on the falling edge of the input pulse to the % V DD level of the rising edge of the signal.. PWD is defined as t PHL - t PLH. 4. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions.. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 6. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
I F -FORWARD CURRENT-mA. IF VF T A =2 C I th -INPUT THRESHOLD CURRENT-mA.6.4.2..8.6.4.2 I ol =2uA V.V..2..4..6 V F -FORWARD VOLTAGE-V. -4-2 2 4 6 8 2 T A -TEMPERATURE- o C Figure. Typical input diode forward characteristic. Figure 2. Typical input threshold current vs. temperature. I DDH -LOGIC HIGH OUTPUT SUPPLY CURRENT -ma 6 4 2 V DD =V V DD =.V -4-2 2 4 6 8 T A -TEMPERATURE- o C IDDL-LOGIC LOW OUTPUT SUPPLY CURRENT-mA 6 4 2 V DD =.V V DD =.V -4-2 2 4 6 8 T A -TEMPERATURE- o C Figure. Typical logic high O/P supply current vs. temperature. Figure 4. Typical logic low O/P supply current vs. temperature. tp PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION ns 2 2 T PLH T PHL PWD V DD =V Ta=2 C 4 6 7 8 I F PULSE INPUT CURRENT ma tp PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION ns 2 2 T PHL T PLH PWD V DD =.V Ta=2 C 4 6 7 8 I F PULSE INPUT CURRENT ma Figure. Typical switching speed vs. pulse input current at V supply voltage. Figure 6. Typical switching speed vs. pulse input current at.v supply voltage. 6
.8.7 VF - FORWARD VOLTAGE - C.6..4..2. - 4-2 2 4 6 8 T A - TEMPERATURE - o C I in Gnd 2 XXX YWW C =. uf to.uf 4 C V DD2 Gnd2 Figure 7. Typical V F vs. temperature. Figure 8. Recommended printed circuit board layout Application Information Bypassing and PC Board Layout The ACPL-M7L optocoupler is extremely easy to use. ACPL-M7L provides CMOS logic output due to the highspeed CMOS IC technology used. The external components required for proper operation are the input limiting resistor and the output bypass capacitor. Capacitor values should be between. µf and. µf. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 2 mm. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). I F % DATA 2. V, CMOS INPUTS CLOCK t PSK I F % DATA OUTPUTS t PSK 2. V, CMOS CLOCK t PSK Figure 9. Propagation delay and skew waveform Figure. Parallel data transmission example 7
Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often PWD determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 2-% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS22, RS422, T-, etc.). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and power supply ranges. + V in - GND R drv = Ω C peak R limit SHIELD. µf V DD2 Figure. Connection of peaking capacitor (Cpeak) in parallel of the input limiting resistor (Rlimit) to improve speed performance GND 2 2 2 tphl tplh tplh tphl PWD With peaking cap Without peaking cap -4-2 2 4 6 8 (i) V DD =V, C peak =pf, R limit =Ω 4 2 2 tplh tplh tphl tphl With peaking cap Without peaking cap PWD -4-2 2 4 6 8 (ii) V DD =.V, C peak =pf, R limit =2Ω Figure 2. Improvement of tp and PWD with added pf peaking capacitor in parallel of input limiting resistor. 8
Powering Sequence V DD needs to achieve a minimum level of V before powering up the output connecting component. Input Limiting Resistors ACPL-M7L is direct current driven (Figure 8), and thus eliminate the need for input power supply. To limit the amount of current flowing through the LED, it is recommended that a ohm resistor is connected in series with anode of LED (i.e. Pin for ACPL-M7L) at V input signal. At.V input signal, it is recommended to connect 2Ω resistor in series with anode of LED. The recommended limiting resistors is based on the assumption that the driver output impedence is Ω (as shown in Figure ). Speed Improvement A peaking capacitor can be placed across the input current limit resistor (Figure ) to achieve enhanced speed performance. The value of the peaking cap is dependent to the rise and fall time of the input signal and supply voltages and LED input driving current (I f ). Figure 2 shows significant improvement of propagation delay and pulse with distortion with added peak capacitor at driving current of 6mA for both.v and V power supply. Common Mode Rejection for ACPL-M7L Figure shows the recommended drive circuit for the ACPL-M7L for optimal common-mode rejection performance. Two LED-current setting resistors are used instead of one. This is to balance the common mode impedance at LED anode and cathode. Common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely cause current to be injected into the LED (bad if the LED is meant to be off). Figure4 shows the parasitic capacitances which exists between LED anode/cathode and output ground (C LA and C LC ). Also shown in Figure 4 on the input side is an AC-equivalent circuit. Table indicates the directions of I LP and I LN flow depending on the direction of the common-mode transient. For transients occurring when the LED is on, common-mode rejection (CM L, since the output is in the low state) depends upon the amount of LED current drive (I F ). For conditions where I F is close to the switching threshold (I TH ), CM L also depends on the extent which I LP and I LN balance each other. In other words, any condition where commonmode transients cause a momentary decrease in I F (i.e. when dv CM /dt> and I FP > I FN, referring to Table ) will cause common-mode failure for transients which are fast enough. Likewise for common-mode transients which occur when the LED is off (i.e. CM H, since the output is high ), if an imbalance between I LP and I LN results in a transient I F equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below 2V (which constitutes a CM H failure). By using the recommended circuit in Figure, good CMR can be achieved. The resistors recommended in Figure include both the output impedence of the logic driver circuit and the external limiting resistor. The balanced I LED - setting resistors help equalize the common mode voltage change at anode and cathode to reduce the amount by which I LED is modulated from transient coupling through C LA and C LC. Table. Effects of Common Mode Pulse Direction on Transient I LED If dv CM /dt Is: then I LP Flows: and I LN Flows: positive (>) negative (<) away from LED anode through C LA toward LED anode through C LA If I LP < I LN, LED I F Current Is Momentarily: If I LP > I LN, LED I F Current Is Momentarily: away from LED increased decreased cathode through C LC toward LED decreased increased cathode through C LC 9
CMR with Other Drive Circuits CMR performance with drive circuits other than that shown in Figure may be enhanced by following these guidelines:. Use of drive circuits where current is shunted from the LED in the LED off state (as shown in Figures and 6). This is beneficial for good CM H. 2. Use of typical I FH = 6mA per datasheet recommendation Using any one of the drive circuits in Figures -7 with I F = 6 ma will result in a typical CMR of kv/μs for ACPL- M7L, as long as the PC board layout practices are followed. Figure shows a circuit which can be used with any totem-pole-output TTL/LSTTL/HCMOS logic gate. The buffer PNP transistor allows the circuit to be used with logic devices which have low current-sinking capability. It also helps maintain the driving-gate power-supply current at a constant level to minimize ground shifting for other devices connected to the input-supply ground. When using an open-collector TTL or open-drain CMOS logic gate, the circuit in Figure 6 may be used. When using a CMOS gate to drive the optocoupler, the circuit shown in Figure 7, where the resistor is recommended to connect to the anode of the LED, may be used. V DD /2R total R total = Ω-for V DD =.V = 8Ω-for V DD =V V DD2 /2R total.µf 74LS4 OR ANY TOTEM- POLE OUTPUT LOGIC GATE GND SHIELD GND 2 Figure. Recommended drive circuit for ACPL-M7L for high-cmr V DD ACPL-M7L ½ R total ½ R total I LP C LA.µF V DD2 pf 74L4 (ANY TTL/CMOS GATE) 2N96 (ANY PNP) Ω LED I LN C LC SHIELD GND 2 Figure 4. AC equivalent of ACPL-M7L Figure. TTL interface circuit for the ACPl-M7L families.
V DD ACPL-M7L V DD ACPL-M7L Ω 74HC (OR ANY OPEN-COLLECTOR /OPEN-DRAIN LOGIC GATE) LED 74HC4 (OR ANY TOTEM-POLE OUTPUT LOGIC GATE) Ω LED Figure 6. TTL open-collector/open drain gate drive circuit for ACPL-M7L families. Figure 7. CMOS gate drive circuit for ACPL-M7L families. V CM R limit A B I F SHIELD.µF V CM V V DD GND2 SWITCH AT A: I = ma F SWITCH AT B: I = 6 ma F V CM (PEAK) (min.) (max.) CM H CM L Pulse Gen. + - Figure 8. Test circuit for common mode transient immunity and typical waveforms. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2-24 Avago Technologies. All rights reserved. AV2-96EN - July 9, 24