Chapter 6 DIFFERENT TYPES OF LOGIC GATES

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Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Lesson 9 CMOS gates Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Outline CMOS (n-channel based MOSFETs based circuit) CMOS Features Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3

p and n channel MOSFET complementary pairs When n-channel is ON, the p-channel is OFF and when n-channel is OFF, the p- channel is ON. It means the d.c. (steady state) current dissipation between the supply ends is very small as the series resistance is always very high. Current will flow only during the transitions from 0 to 1 or 1 to 0. Power will dissipate only during the transitions from 0 to 1 or 1 to 0. Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4

p and n channel MOSFET complementary pairs Since at an instant one of the MOSFET in the pair is ON and has low resistance, the switching speed at charging and discharging is rapid and turn ON delay and turn OFF delay are nearly same Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5

p and n channel MOSFET complementary pairs This feature makes it possible to fabricate large or very large or very-very large-scale integrated circuits (LSI or VLSI or VVLSI) using the CMOS pairs Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6

p-channel depletion mode active resistor and n-channel MOS as logic driver An enhancement mode p-channel acts as pull up and n-channel enhancement mode MOSFET act as a logic driver (pull down) Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7

Drain Gate G D V + DD I DS A D A F S S V + DD V - SS CMOS Inverter p-channel Depletion mode as active resistor and n-channel enhancement mode output stage MOSFET in series Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8

Drain Gate G D B F D A + B A.B S V + DD A V SS CMOS NOR two p channel Depletion mode as active resistors and two enhancement mode MOSFETs in parallel Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9 S

Drain Gate G D B F D A, B A +B S V + DD A V SS CMOS NAND two p channel Depletion mode as active resistors and two enhancement mode MOSFETs in Series Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10 S

n-channel enhancement mode ON state (Input Logic State 1 Output 0) When V GS >V T GS, a channel is formed between drain and source I D increases and linearly varies with V DS MOSFET ON state. Further, when the V GS increases, the slope of change in I D is steeper and steeper with respect to V DS. Channel resistance decreases steeply with (V GS - V T GS ). MOSFET is said to be in ON state. Channel width is constant is function of (V GS -V T ). GS Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11

Two enhancement mode MOSFETS in parallel Two enhancement-mode n-channel MOSFETs TA and TB are the logic drivers in parallel. These give an output Vo at F through a common point connected to drains of TA and TB. If both TA and TB are off, the output equals, supply voltage VDD. If any one is ON, the output at F equals the VSS (the supply GND) Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12

Two enhancement mode MOSFETS in parallel Each enhancement-mode n-channel MOSFETs TA and TB are in seires with p channel deletion mode MOSFET functioning as active resistor. Hence, total current in each pair is negligible Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 13

Two enhancement mode MOSFETS in Series Two enhancement mode n-channel MOSFETs T and T are in series. A B These give an output V at F through o the upper CMOS drain of T, which B also connects the CMOS MOSFET pull up. If both TA and T are off, the B output equals, supply voltage V. If DD any one is ON, the output at F equals the V (the supply GND). SS Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14

Output at F Property of a NAND is that its output is 0 when all the inputs are 1. When two enhancement mode MOSFETs are placed in series, the circuit functions as NAND Property of a NOR is that its output is 1 when all the inputs are 0. When two enhancement mode MOSFETs are placed in parallel, the circuit functions as NOR Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 15

CMOS Outline CMOS Features Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 16

CMOS Voltage Levels Supply V DD = 5V operating version or 3 to 16V operating version and V SS = 0V V OL (Voltage Output at logic 0 ) = (1/3) V DD and I OL = 0 V OH (Voltage Output at logic 1 ) = V DD and I OH = 1 ma (4000B series) Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 17

CMOS Voltage Levels V IL (Voltage Input at logic 0 ) = V SS = 0V V IH (Voltage Input at logic 1 ) = (2/3) V DD V TH (Threshold Voltage) = (1/2) V DD Noise Margin at 0 and 1 = ~[(1/3) V DD -(1/2) V DD ]. Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 18

Power Dissipation When n-channel is ON, the p- channel is OFF and when n-channel is OFF, the p-channel is ON. It means the d.c. (steady state) current dissipation between the supply ends is very small as the series resistance is always very high. Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 19

Power Dissipation Current will flow only during the transitions from 0 to 1 or 1 to 0. Power will dissipate only during the transitions from 0 to 1 or 1 to 0. Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 20

Power Dissipation Therefore, unlike like TTL and NMOS, the CMOS logic gates dissipates very little power compared to NMOSs and TTLs and dissipate power only at the transitions of logic states, not in d.c. state Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 21

Fan out Numbers of logic gates at the next stage(s) that can be loaded are very high due to high input impedance between the gates and the channels at the logic drivers. There are only capacitive driving loads. Steady state d.c. power dissipation is extremely small. Impedance between gate and source is capacitive. Current flows at the transitions only Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 22

Propagation Delay 20 ns in a typical VLSI Let gate-source capacitance = C nf [nf means nanofarad.] If m = 40, the total capacitance being all T j in parallel = 40C.. Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 23

Propagation Delay Resistance is very high between gate and source in both logic 0 and logic 1 states but the charging and discharging occurs from the input logic gate rapidly in both 0 to 1 and 1 to 0 transitions. Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 24

Propagation Delay Since at an instant one of the MOSFET in the pair is ON and has low resistance, the switching speed at charging and discharging is rapid and turn ON delay and turn OFF delay are nearly same Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 25

Summary Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 26

We learnt CMOS inverter circuit CMOS NOR circuit CMOS NAND circuit Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 27

A depletion mode p- MOSFET functions as active pull up resistor from supply An enhancement mode n- MOSFET functions as logic state driver Inverter uses one CMOS pair at an input Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 28

CMOS gate has each input connection to a gate of a CMOS pair Two input NOR has two CMOS pairs in parallel Two input NAND has has two CMOS pairs in series Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 29

Summary Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 30

End of Lesson 8 CMOS gates Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 31

THANK YOU Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 32

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