STL100N10F7 N-channel 100 V, 0.0062 Ω typ., 19 A, STripFET VII DeepGATE Power MOSFET in a PowerFLAT 5x6 package Features Datasheet - production data Order code V DSS R DS(on) max I D P TOT 1 2 STL100N10F7 100 V 0.0073 Ω 19 A 5 W 3 4 PowerFLAT 5x6 Ultra low on-resistance 100% avalanche tested Applications Switching applications Figure 1. Internal schematic diagram D(5, 6, 7, 8) 8 7 6 5 Description This device is an N-channel Power MOSFET developed using the 7 th generation of STripFET DeepGATE technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest R DS(on) in all packages. G(4) 1 2 3 4 S(1, 2, 3) Top View AM15540v2 Table 1. Device summary Order code Marking Package Packaging STL100N10F7 100N10F7 PowerFLAT 5x6 Tape and reel July 2013 DocID023656 Rev 4 1/16 This is information on a product in full production. www.st.com 16
Contents STL100N10F7 Contents 1 Electrical ratings............................................ 3 2 Electrical characteristics..................................... 4 2.1 Electrical characteristics (curves)........................... 6 3 Test circuits.............................................. 8 4 Package mechanical data..................................... 9 5 Packaging mechanical data.................................. 13 6 Revision history........................................... 15 2/16 DocID023656 Rev 4
STL100N10F7 Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V DS Drain-source voltage 100 V V GS Gate-source voltage ± 20 V I (1) D Drain current (continuous) at T C = 25 C 80 A I (1) D Drain current (continuous) at T C = 100 C 70 A (2) I D Drain current (continuous) at T pcb = 25 C 19 A (2) I D Drain current (continuous) at T pcb =100 C 13 A I (2)(3) DM Drain current (pulsed) 76 A (1) P TOT Total dissipation at T C = 25 C 100 W (2) P TOT Total dissipation at T pcb = 25 C 5 W T J T stg Operating junction temperature Storage temperature 1. This value is rated according to R thj-c. 2. This value is rated according to R thj-pcb. 3. Pulse width limited by safe operating area. -55 to 175 C Table 3. Thermal resistance Symbol Parameter Value Unit R thj-case Thermal resistance junction-case 1.56 C/W (1) R thj-pcb Thermal resistance junction-pcb 31 C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec Table 4. Avalanche data Symbol Parameter Value Unit E AS Single pulse avalanche energy (T J = 25 C, L = 3.5 mh, I AS = 15 A, V DD = 50 V, V GS = 10 V) 400 mj DocID023656 Rev 4 3/16
Electrical characteristics STL100N10F7 2 Electrical characteristics (T CASE =25 C unless otherwise specified) Table 5. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS I GSS Drain-source breakdown voltage (V GS = 0) Zero gate voltage drain current (V GS = 0) Gate body leakage current (V DS = 0) I D = 250 µa 100 V V DS = 100 V V DS = 100 V; T C =125 C 1 100 µa µa V GS = +20 V 100 na V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa 2 4 V Static drain-source on- R DS(on) V resistance GS = 10 V, I D = 19 A 0.0062 0.0073 Ω Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance - 4369 5680 pf C oss Output capacitance V DS =50 V, f=1 MHz, - 823 1070 pf C rss V GS =0 Reverse transfer capacitance - 36 47 pf Q g Total gate charge V DD =50 V, I D = 19 A - 61 80 nc Q gs Gate-source charge V GS =10 V - 26 nc Q gd Gate-drain charge Figure 14-13 nc Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time - 27 - ns t V DD =50 V, I D = 19 A, r Rise time - 40 - ns R G =4.7 Ω, V GS = 10 V t d(off) Turn-off delay time Figure 13-46 - ns t f Fall time - 15 - ns 4/16 DocID023656 Rev 4
STL100N10F7 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min Typ. Max Unit I SD Source-drain current - 19 A I (1) SDM Source-drain current (pulsed) - 76 A V (2) SD Forward on voltage I SD = 38 A, V GS =0-1.2 V t rr Reverse recovery time I SD = 19 A, - 77 ns Q rr Reverse recovery charge di/dt = 100 A/µs, - 146 nc I RRM Reverse recovery current V DD =80 V, T j =150 C - 4 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% DocID023656 Rev 4 5/16
Electrical characteristics STL100N10F7 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance ID (A) 100 10 Operation in this area is Limited by max RDS(on) AM15617v1 1 0.1 Tj=175 C Tc=25 C Single pulse 0.01 0.1 1 10 VDS(V) 10ms 100ms 1s -pcb Figure 4. Output characteristics Figure 5. Transfer characteristics ID (A) V GS =10 V AM15623v1 ID (A) AM15618v1 300 300 VDS= 5 V 250 V GS =9 V 250 200 V GS =8 V 200 150 V GS = 7 V 150 100 50 VGS= 6 V VGS= 5 V 100 50 0 0 1 2 3 4 VDS(V) Figure 6. Gate charge vs gate-source voltage 0 2 4 6 8 10 VGS(V) Figure 7. Static drain-source on-resistance VGS (V) 12 10 8 6 VDD=50V ID=100A AM15624v1 RDS(on) (mω) 12 10 8 6 VGS=10V AM15621v1 4 4 2 2 0 0 20 40 60 Qg(nC) 0 0 20 40 60 80 100 ID(A) 6/16 DocID023656 Rev 4
STL100N10F7 Electrical characteristics Figure 8. Capacitance variations Figure 9. Normalized B VDSS vs temperature C (pf) AM15625v1 VDS (norm) AM15619v1 5000 1.04 ID = 1mA 4000 Ciss 1.02 3000 1 2000 0.98 1000 Coss 0 0 20 Crss 40 60 80 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature VGS(th) (norm) 0.95 0.9 0.85 0.8 1 ID = 250 µa 0.75 0.7 0.65 0.6-55 -30-5 20 45 70 95 120 TJ( C) AM15622v1 0.96 0.94-55 -30-5 20 45 70 95 120 TJ( C) Figure 11. Normalized on-resistance vs temperature RDS(on) (norm) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 ID=50 A 0.5-50 -25 0 25 50 75 100 TJ( C) AM06484v2 Figure 12. Source-drain diode forward characteristics VSD (V) 1.1 TJ=-50 C AM15620v1 1 0.9 0.8 TJ=25 C 0.7 TJ=150 C 0.6 0.5 0 20 40 60 80 100 ISD(A) DocID023656 Rev 4 7/16
Test circuits STL100N10F7 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD VGS VD RG RL D.U.T. 2200 μf 3.3 μf VDD Vi=20V=VGMAX 2200 μf 12V IG=CONST 2.7kΩ 47kΩ 100Ω 100nF D.U.T. 1kΩ VG PW 47kΩ PW 1kΩ AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load switching and diode recovery times Figure 16. Unclamped inductive load test circuit G 25 Ω D S A D.U.T. B A FAST DIODE B A B D L=100μH 3.3 1000 μf μf VDD VD ID L 2200 μf 3.3 μf VDD G RG S Vi D.U.T. AM01470v1 Pw AM01471v1 Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform V(BR)DSS ton toff VD tdon tr tdoff tf ID IDM 0 90% 10% VDS 10% 90% VDD VDD VGS 90% AM01472v1 0 10% AM01473v1 8/16 DocID023656 Rev 4
STL100N10F7 Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DocID023656 Rev 4 9/16
Package mechanical data STL100N10F7 Table 9. PowerFLAT 5x6 type S-R mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.11 4.31 E2 3.50 3.70 e 1.27 L 0.60 0.80 K 1.275 1.575 10/16 DocID023656 Rev 4
STL100N10F7 Package mechanical data Figure 19. PowerFLAT 5x6 type S-R drawing 5 8 Bottom View Pin 1 identification 4 1 Side View 8 5 Pin 1 identification. 1 4 Top View 8231817_Rev.F_Ribbon type S-R DocID023656 Rev 4 11/16
Package mechanical data STL100N10F7 Figure 20. PowerFLAT 5x6 recommended footprint (dimensions in mm) Footprint 12/16 DocID023656 Rev 4
REF.R0.50 STL100N10F7 Packaging mechanical data 5 Packaging mechanical data Figure 21. PowerFLAT 5x6 tape (a) T (0.30 ±0.05) Do Ø1.55±0.05 Y P 2 2.0±0.1 (I) P 0 4.0±0.1 (II) E1 1.75±0.1 C L Bo (5.30±0.1) D1 Ø1.5 MIN. REF 0.20 F(5.50±0.1)(III) W(12.00±0.3) Y Ko (1.20±0.1) P1(8.00±0.1) Ao(6.30±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ± 0.20. (III) Measured from centerline of sprocket hole to centerline of pocket. Base and bulk quantity 3000 pcs 8234350_Tape_rev_C Pin 1 identification Figure 22. PowerFLAT 5x6 package orientation in carrier tape. a. All dimensions are in millimeters. DocID023656 Rev 4 13/16
Packaging mechanical data STL100N10F7 Figure 23. PowerFLAT 5x6 reel R0.60 PART NO. 1.90 2.50 W3 11.9/15.4 W2 18.4 (max) R25.00 4.00 ØN 178(±2.0) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES A 330 (+0/-4.0) 2.50 77 ESD LOGO 06 PS ØA W1 12.4 (+2/-0) 128 R1.10 Ø21.2 2.20 13.00 All dimensions are in millimeters CORE DETAIL 8234350_Reel_rev_C 14/16 DocID023656 Rev 4
STL100N10F7 Revision history 6 Revision history Table 10. Document revision history Date Revision Changes 05-Oct-2012 1 First release. 19-Feb-2013 2 21-Feb-2013 3 31-Jul-2013 4 Document status chaged from preliminary to production data Inserted: Section 2.1: Electrical characteristics (curves) Updated: Section 4: Package mechanical data Added: Section 5: Packaging mechanical data Minor text changes Updated Table 8: Source drain diode and Figure 5: Transfer characteristics. Updated I D values in test conditions respectively in Table 6: Dynamic and Table 7: Switching times. Modified: Figure 13, 14, 15 and 16 Minor text changes DocID023656 Rev 4 15/16
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