9-987; Rev ; 9/3 5MHz, Triple, -Channel Video General Description The is a triple, wideband, -channel, noninverting gain-of-two video amplifier with input multiplexing, capable of driving up to two back-terminated video loads. The features current-mode feedback amplifiers configured for a gain of two (+6dB) with a -3dB large-signal bandwidth of MHz. The device has low (.%/.4 ) differential gain and phase errors, and operates from ±5V supplies. The is ideal for use in broadcast and graphics video systems because of the low pf input capacitance, channel-to-channel switching time of only 5ns, and wide 6MHz, large-signal.db bandwidth. Highimpedance output disabling allows the to be incorporated into large switching arrays with minimal interaction with the source. Specified over the -4 C to +85 C extended temperature range, the is available in 4-pin SO and TSSOP packages. Applications Video Source Selection (Multiplexing) Picture in Picture (PIP) Insertion Crosspoint Expansion Coaxial Cable Drivers Supports VGA to UXGA (6 x ) Resolution Enterprise Class (Blade) Servers Keyboard-Video-Mouse (KVM) Features Excellent Video Specifications: 75MHz Small-Signal.dB Gain Flatness 6MHz Large-Signal.dB Gain Flatness.%/.4 Differential Gain/Phase Error VGA to UXGA Resolution High Speed: MHz VP-P -3dB Bandwidth V/µs Slew Rate 5ns Settling Time to.% Internal Gain of V/V Compensates for Output Back Termination Fast Switching: 5ns Channel-Switching Time 6mVP-P Switching Transient Drives Two Back-Terminated Video Loads High-Impedance Output Disable Ordering Information PART TEMP RANGE PIN-PACKAGE ESD -4 C to +85 C 4 SO EUD -4 C to +85 C 4 TSSOP Typical Operating Circuit Pin Configuration TOP VIEW VIDEO SOURCE VIDEO SOURCE R G B R G B INA INA IN3A INB INB IN3B TRIPLE : MUX x x x OUT OUT OUT3 R G B INA INA IN3A GND INB INB IN3B 3 4 5 6 7 4 3 9 8 OUT V CC OUT V EE OUT3 SO/TSSOP Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at -888-69-464, or visit Maxim s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (V CC to GND)...+6V Negative Supply Voltage (V EE to GND)...-6V Amplifier Input Voltage (IN )...(V EE -.3V) to (V CC +.3V) Digital Input Voltage (, )...-.3V to (V CC +.3V) Output Short Circuit to GND (Note )...Continuous Output Short Circuit to V CC or V EE...5s Note : Continuous power-dissipation rating must also be observed. Continuous Power Dissipation (T A = +7 C) 4-Pin TSSOP (derate 9.mW/ C above +7 C)...77mW 4-Pin SO (derate 8.3mW/ C above +7 C)...667mW Operating Temperature Range...-4 C to +85 C Storage Temperature Range...-65 C to +5 C Junction Temperature...+5 C Lead Temperature (soldering, s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V CC = 5V, V EE = -5V, V IN = V, R L = 5Ω to GND, T A = -4 C to +85 C. Typical values are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage Range V CC +4.5 +5. +5.5 Inferred from the PSRR test V EE -4.5-5. -5.5 = GND 3 39 Positive Supply Current I CC = 5V 7 4 V ma = GND 8 36 Negative Supply Current I EE = 5V 5 ma Input Voltage Range V IN Inferred from voltage gain ±.5 ±.75 V T A = +5 C ± ±6 Input Offset Voltage V OS T A = -4 C to +85 C ± Input Offset-Voltage Matching V OS Channel to channel ± ± mv Voltage Gain A V = ±.5V.9.. V/V Input Offset-Voltage Temperature Coefficient TCV OS µv/ C T A = +5 C ± ± Input Bias Current I B T A = -4 C to +85 C ±8 V Channel on 4 kω Input Resistance R IN = -.5V to IN +.5V Channel off MΩ DC Output Resistance R OUT mω Disabled Output Resistance R OUT(d) = 5V, = -.5V to +.5V (Note 3).6 kω DC Power-Supply Rejection Ratio PSRR V CC = +4.5V to +5.5V, V EE = -4.5V to -5.5V 6 86 db Output Voltage Swing ±.5 ±3.5 V Output Short-Circuit Current I SC ±43 ma LOGIC CHARACTERISTICS (, ) Logic-Low Threshold V IL.8 V Logic-High Threshold V IH. V Logic-Low Input Current I IL V IL = V -4 - µa Logic-High Input Current I IH V IH = +5.5V, V CC = +5.5V 35 6 µa mv µa
AC ELECTRICAL CHARACTERISTICS (V CC = 5V, V EE = -5V, V IN = V, R IN = 75Ω to GND, R L = 5Ω to GND, T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AMPLIFIER CHARACTERISTICS Small-Signal -3dB Bandwidth BW SS V IN = mv P-P 5 MHz Small-Signal Bandwidth for ±.db Gain Flatness BW LS(.) V IN = mv P-P 75 MHz Large-Signal -3dB Bandwidth BW LS V IN = V P-P MHz Large-Signal Bandwidth for ±.db Gain Flatness BW LS(.) V IN = V P-P 6 MHz Slew Rate SR V IN = V P-P V/µs Settling Time to.% t S V IN = V P-P 5 ns Differential Gain Error DG 5-step modulated staircase (Note 4). % Differential Phase Error DP 5-step modulated staircase (Note 4).4 degrees Delay Between Channels t D V IN = V P-P, t R = ps. ns Channel-to-Channel Crosstalk X TALK V IN = ±V P-P, f = Hz -6 db Crosstalk V IN = ±V P-P, f = Hz -8 db Output Impedance Z OUT f = Hz Ω Total Harmonic Distortion THD = V P-P, f = Hz 64 dbc Off-Isolation A ISO = V P-P, f = Hz, R S = 75Ω -83 db Output Capacitance C OUT Channel on or off 3 pf Input Capacitance C IN Channel on or off pf Input-Voltage Noise Density e n f = khz 6.5 nv/ Hz Input-Current Noise Density i n f = khz 6.5 pa/ Hz SWITCHING CHARACTERISTICS Channel-Switching Time t SW (Notes 5, 6) 5 ns Enable Delay Time t PDE (Notes 5, 7) ns Disable Delay Time t PDD (Notes 5, 7) 5 ns Switching Transient V TRAN (Note 8) 6 mv P-P Note : Limits are % production tested at T A = +5 C. Limits over the operating temperature range are guaranteed by design. Note 3: Disabled output resistance includes the internal feedback network. Note 4: Input test signal is NTSC composite with 5-step staircase, of 4 IRE per step, modulated with 3.58MHz color subcarrier. Note 5: See the Timing Diagram (Figure ). Note 6: Channel-switching time specified for switching between input channels; does not include signal rise/fall times for switching between channels with different input voltages. Note 7: Output enable/disable delay times do not include amplifier output slewing times. Note 8: Switching transient measured while switching between two grounded channels. 3
Typical Operating Characteristics (V CC = +5V, V EE = -5V, R L = 5Ω to GND, T A = +5 C, unless otherwise noted.) GAIN (db) 3 - - -3-4 -5-6 -7 SMALL-SIGNAL FREQUCY RESPONSE V IN = mv P-P A V = +V/V toc G GAIN (db).3.. -. -. -.3 -.4 -.5 -.6 -.7 SMALL-SIGNAL GAIN FLATNESS V IN = mv P-P A V = +V/V toc G GAIN (db) 3 - - -3-4 -5-6 -7 LARGE-SIGNAL FREQUCY RESPONSE A V = +V/V = 4V P-P = V P-P toc3 G GAIN (db).3.. -. -. -.3 -.4 -.5 -.6 -.7 LARGE-SIGNAL GAIN FLATNESS A V = +V/V = 4V P-P = V P-P toc4 G CHANNEL-TO-CHANNEL GAIN MATCHING (db).5.4.3.. -. -. -.3 -.4 -.5 CHANNEL-TO-CHANNEL GAIN MATCHING = V P-P toc5 DIFFERTIAL GAIN (%) DIFFERTIAL PHASE (DEG).. -. -... -. -. DIFFERTIAL GAIN AND PHASE st nd 3rd 4th 5th 6th st nd 3rd 4th 5th 6th toc6 PSRR (db) - -5-3 -35-4 -45-5 -55-6 -65 k POWER-SUPPLY REJECTION RATIO PSRR- PSRR+ toc7 OFF-ISOLATION (db) - -4-6 -8 - - OFF-ISOLATION toc8 G CROSSTALK (db) - - -3-4 -5-6 -7-8 k CHANNEL-TO-CHANNEL CROSSTALK toc9 G 4
Typical Operating Characteristics (continued) (V CC = +5V, V EE = -5V, R L = 5Ω to GND, T A = +5 C, unless otherwise noted.) CROSSTALK (db) - -4-6 -8 - CROSSTALK toc OUTPUT IMPEDANCE (Ω). OUTPUT IMPEDANCE toc THD (dbc) - -3-4 -5-6 -7-8 TOTAL HARMONIC DISTORTION = V P-P toc - k G. k G -9 LARGE-SIGNAL PULSE RESPONSE toc3 SMALL-SIGNAL PULSE RESPONSE toc4 LARGE-SIGNAL PULSE RESPONSE (C LOAD = pf) toc5 V IN 5mV/div V V IN 5mV/div V V IN 5mV/div V V/div V mv/div V V/div V ns/div ns/div ns/div SMALL-SIGNAL PULSE RESPONSE (C LOAD = pf) toc6 ABLE RESPONSE TIME toc7 SWITCHING TRANSIT toc8 V IN 5mV/div.5V/div.5V/div V V V mv/div V V/div V mv/div V ns/div ns/div ns/div 5
Typical Operating Characteristics (continued) (V CC = +5V, V EE = -5V, R L = 5Ω to GND, T A = +5 C, unless otherwise noted.) SUPPLY CURRT (ma) 35 34 33 3 3 3 9 8 7 6 SUPPLY CURRT vs. TEMPERATURE 5-5 -5 5 5 75 toc9 INPUT BIAS CURRT (µa) 5. 4.5 4. 3.5 3..5..5..5 INPUT BIAS CURRT vs. TEMPERATURE -5-5 5 5 75 toc POSITIVE OUTPUT SWING (V) 5. 4.5 4. 3.5 3. POSITIVE OUTPUT SWING vs. TEMPERATURE.5-5 -5 5 5 75 toc NEGATIVE OUTPUT SWING (V) -.5-3. -3.5-4. -4.5 NEGATIVE OUTPUT SWING vs. TEMPERATURE R LOAD = 5Ω R LOAD = 5Ω NO LOAD toc VOS (mv) 4 3 - - INPUT OFFSET VOLTAGE vs. TEMPERATURE toc3-3 -5. -5-5 5 5 75-4 -5-5 5 5 75 OUTPUT SHORT-CIRCUIT CURRT (ma) 6 55 5 45 4 35 3 OUTPUT SHORT-CIRCUIT CURRT vs. TEMPERATURE SOURCING AND SINKING 5-5 -5 5 5 75 toc4 GAIN (db) 3 - - -3-4 -5-6 -7 SMALL-SIGNAL BANDWIDTH V IN = mv P-P A V = +V/V pf 5pF 5pF pf toc5 G 6
Pin Description PIN NAME FUNCTION INA Amplifier Channel A Input INA Amplifier Channel A Input 3 IN3A Amplifier 3 Channel A Input 4 GND Power Supply, Analog and Digital Ground. Connect GND to ground plane for best RF performance. 5 INB Amplifier Channel B Input 6 INB Amplifier Channel B Input 7 IN3B Amplifier 3 Channel B Input 8 Output Enable Logic Input. Drive low or leave open for normal operation. Pull high to disconnect amplifier output (output is high impedance when disabled). is internally pulled to GND through a 7kΩ resistor. 9 OUT3 Amplifier Output 3 V EE Negative Power-Supply Voltage. Bypass V EE to GND with a.µf capacitor. OUT Amplifier Output V CC Positive Power-Supply Voltage. Bypass V CC to GND with a.µf capacitor. 3 OUT Amplifier Output 4 Channel-Select Input. Drive low or leave open to select channel A for all amplifiers. Pull high to select channel B for all amplifiers. is internally pulled to GND through a 7kΩ resistor. Detailed Description The combines three : multiplexers with +V/V (+6dB) closed-loop gain (A VCL ) amplifiers. This low-power, high-speed device operates from ±5V supplies, while driving up to two back-terminated video loads with very low distortion. Differential gain and phase errors are.%/.4 for the. The input multiplexers feature fast 5ns channelswitching times and small switching transients. The multiplexers also feature high input resistance and constant input capacitance, so overall input impedance can be set by external input-terminating resistors. Drive high to place the amplifier outputs in a highimpedance state, and minimize the supply current. This function allows use of multiple mux/amps in parallel to form large switching arrays. The features an input, which selects either channel A or B. Drive low to select channel A or drive high to select channel B. Channel A is automatically selected if is left unconnected. Table. Input Control Logic AMPLIFIER INPUT FUNCTION IN_A Channel A Selected IN_B Channel B Selected Table. Output Control Logic AMPLIFIER OUTPUT FUNCTION On Outputs Enabled Off Truth Tables Outputs High Impedance Applications Information Disable Mode Drive high to place the in disable mode. Placing the device in disable mode reduces the quiescent current to 7mA (V CC ) and 5mA (V EE ) and places the amplifier outputs into a high-impedance state, typi- 7
cally.6kω. Parallel multiple devices to construct larger switch matrices by connecting the outputs of several devices together and disabling all but one of the paralleled amplifiers outputs. Two internal 8Ω thin-film resistors set the to a fixed gain of +. Consider the impedance of the internal feedback resistors when operating multiple s in large multiplexer applications. Drive low for normal operation. has internal pulldown circuitry. The is enabled when is unconnected. Video Line Driver The is well suited to drive short coaxial transmission lines when the cable is terminated at both ends (Figure ) where the fixed gain of + compensates for the loss in the back termination. Cable frequency response may cause variations in the flatness of the signal. Input Voltage Range The guaranteed input voltage range is ±.5V. Exceeding this value can cause unpredictable results, including output clipping, excessive input current, and switching delays. Multiplexer The input multiplexer (mux) is controlled by a 3.3V TTL/CMOS-compatible control input (see the Truth Tables). Input capacitance is a constant, low pf and input resistance is 7kΩ to GND for all input channels, regardless of whether or not the channel is selected. All logic levels ( and ) default low if left unconnected. Layout and Power-Supply Bypassing The has an extremely high bandwidth and requires careful board layout. For best performance, use constant-impedance microstrip or stripline techniques. To realize the full AC performance of these high-speed amplifiers, pay careful attention to power-supply bypassing and board layout. The PC board should have at least two layers: a signal and power layer on one side, and a large, low-impedance ground plane on the other side. The ground plane should be as free of voids as possible. With multilayer boards, locate the ground plane on an internal layer that incorporates no signal or power traces. Observe the following guidelines when designing the board regardless of whether or not a constant-impedance board is used. ) Do not use wire-wrap boards or breadboards. ) Do not use IC sockets; they increase parasitic capacitance and inductance. 3) Keep lines as short and as straight as possible. Do not make 9 turns; round all corners. 4) Observe high-frequency bypassing techniques to maintain the amplifier s accuracy and stability. 5) Use surface-mount components. They generally have shorter bodies and lower parasitic reactance, yielding better high-frequency performance than through-hole components. The bypass capacitors should include a.µf ceramic surface-mount capacitor between each supply pin and the ground plane, located as close to the package as 75Ω CABLE 75Ω CABLE R T 75Ω IN_A OUT_ R T 75Ω 75Ω CABLE R T 75Ω IN_B R T 75Ω Figure. Video Line Driver 8
possible. Optionally, place a µf tantalum capacitor at the power-supply pins points of entry to the PC board to ensure the integrity of incoming supplies. The power-supply trace should lead directly from the tantalum capacitor to the V CC and V EE pins. Use surface-mount resistors for input termination and output back termination. Place the termination resistors as close to the IC as possible. INA INB MUX Functional Diagram V CC OUT TO INA INB MUX TO OUT t SW t SW TO OUT CHANNEL A CHANNEL B CHANNEL A IN3A IN3B MUX3 TO OUT3 t PDD t PDE OUT HIGH IMPEDANCE GND V EE Figure. Switching Timing Diagram TRANSISTOR COUNT: 87 PROCESS: Bipolar Chip Information 9
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) N E H INCHES MILLIMETERS DIM MIN MAX MIN MAX A.53.69.35.75 A.4...5 B.4.9.35.49 C.7..9.5 e.5 BSC.7 BSC E.5.57 3.8 4. H.8.44 5.8 6. L.6.5.4.7 SOICN.EPS TOP VIEW VARIATIONS: DIM D D D INCHES MILLIMETERS MIN MAX MIN MAX N MS.89.97 4.8 5. 8 AA.337.344 8.55 8.75 4 AB.386.394 9.8. 6 AC D A C e B A FRONT VIEW L SIDE VIEW -8 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE,.5" SOIC APPROVAL DOCUMT CONTROL NO. REV. -4 B
Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) TSSOP4.4mm.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 3 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.