40MHz, 32-hannel Serial to Parallel onverter with Push-Pull Outputs Features HMOS technology 5.0 logic and 12 supply rail Output voltage up to +200 Low power level shifting Source/sink current minimum 50m 40MHz equivalent data rate Latched data outputs Forward and reverse shifting options (IR pin) hip select Polarity function General escription The is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color plasma displays. The device has 4 parallel -bit shift registers permitting data rates four times the speed of one. The data is clocked in simultaneously on all four data inputs with a single clock. ata is shifted in on a low to high transition of the clock. The latches and control logic perform the output enable function. The IR pin causes clockwise (W) shifting of the data when connected to 1, and counterclockwise (W) shifting when connected to LGN. Operation of the shift register is not affected by the LE (latch enable) input. Transfer of data from the shift registers to the latches occurs when the LE input is high. ata is stored in the latches when LE is low. The current source on the logic inputs provides active pull up when the input pins are open. al lock iagram OUT LK OUT IR LE L S POL Q1 Q Q1 Q L 1 1 1 1 OUT Q1 Q L OUT Q1 Q L
Ordering Information / vailability Part Number Package Option Packing Pin onfiguration 64 PG-G 64-Lead PQFP (3-sided) 66/tray -G denotes a lead (Pb)-free / RoHS compliant package bsolute Maximum Ratings Parameter alue Supply voltage, -0.5 to +14 Supply voltage, 2-0.5 to +14 Supply voltage, PP -0.5 to +225 Logic input levels -2.0 to + 2.0 ontinuous total power dissipation 1 Operating temperature range Storage temperature range 1200mW -40 to +5-65 to +150 bsolute Maximum Ratings are those values beyond which damage to the device may occur. al operation under these conditions is not implied. ontinuous operation of the device at the absolute rating level may affect device reliability. ll voltages are referenced to device ground. Notes: 1. For operation above 25 ambient derate linearly to maximum operating temperature at 20mW/. Product Marking 1 64-Lead PQFP (3-sided) (top view) Top Marking PG LLLLLLLLLL YYWW L = Lot Number YY = Year Sealed WW = Week Sealed = ountry of Origin = ssembler I = Green Packaging Package may or may not include the following marks: Si or 64-Lead PQFP (3-sided) Typical Thermal Resistance Package 64-Lead PQFP θ ja 41 O /W Recommended Operating onditions Sym Parameter Min Max Units Logic supply voltage 4.5 2 2 12 supply voltage 10. 13.2 PP High voltage supply voltage 50 200 High-level input voltage -0.5 Low-level input voltage 0 0.5 f LK lock frequency = 5.0-10 MHz = 12-5 MHz T Operating temperature range -40 +5 I O llowable pulsed current through output diodes 1-500 m I GN(PP) llowable pulsed PP or HGN current 1-16 PP(SLEW) Slew rate of PP - 340 /µs Notes: 1. The current pulse width = 500ns, duty cycle = 5%. 2
Electrical haracteristics (Over operating supply voltages and temperature, unless otherwise noted, = 5.0, 2 = 12, PP = 200 and T j = 25 ) Sym Parameter Min Max Units onditions I 1 supply current - 5.0 m f LK = 10MHz I 2 2 supply current - 20 m 2 = 13.2, f LK = 10MHz I PP High voltage supply current - 2.0 m ll outputs high or low I 1Q Quiescent supply current - 100 µ ll input = I 2Q Quiescent 2 supply current - 100 µ ll input = High-level output Low-level output 15 - I O = -50m ata OUT -1 - I O = -100µ - 20 I O = +50m ata OUT - 1.0 I O = +100µ I IH High-level logic input current - 1.0 µ IN = I IL Low-level logic input current - -10 µ IN = 0 GG HGN to LGN voltage difference -1.0 1.0 --- Electrical haracteristics (Logic signal inputs and data inputs have t r, t f 5ns. = 5.0 or 12, 2 = 12, PP = 200 and T j = 25 ) Sym Parameter Min Max Units onditions f LK lock frequency = 5.0-10 = 12-5.0 MHz t WL, t WH lock width high or low 40 - ns --- t SU ata set-up time before clock rises 20 - ns --- t H ata hold time after clock rises 20 - ns --- t ON, t OFF Time from latch enable to - 275 ns L t WLE LE pulse width 25 - ns --- t LE elay time clock to LE low to high 50 - ns --- t SLE LE set-up time before clock rises 20 - ns --- t LF, t LN L or S low to high to - 250 ns --- t OF, t ON lock to - 275 ns --- t LH t HL elay time clock to data low to high elay time clock to data high to low = 5.0-250 = 12-100 = 5.0-250 = 12-100 ns ns Per register, L L L 3
Input and Output Equivalent ircuits 2 1 1 PP INPUT T OUT LGN Logic Inputs LGN Logic ata Output HGN High oltage Outputs Switching Waveforms ata Input ata alid LK t SU t H t f t r t WL t WH t LH ata Output t HL LE t LE t WLE t SLE t OF t OFF t ON t ON L, L, L, L, or S t LF t LN 4
Table Inputs LK LE IR L L L L S POL ll O/P High X X X X X X X X X X X L L H H H H ll O/P Low X X X X X X X X X X X L H L L L L Outputs Low Normal Polarity Outputs Inverted Transparent Mode X X X X X X X L X X X X H L * * * X X X X X X X H H H H H H No Inversion X X X X X X X H H H H H L Inversion H L L L H X H H H H H H H L L L ata Stored X X X X X L X H H H H H H Stored data W X X X X H H H H H H H X N N+1 N N+1 N N+1 N N+1 W X X X X H L H H H H H X N N-1 N N-1 N N-1 N N-1 Notes: H = High level, L = Low level, X = Irrelevant, = Low to high transition. * = ependent on previous stage s state before the last LK for last LE high. = L, L and L will have similar effect on their respective output. Power-up sequence: 1. GN (H, L) 2. 3. 2 4. PP 5. Logic Input Signals To power down reverse the sequence above. 5
Pin 1 HGN 17 5 33 S 49 4 2 PP 1 5 34 OUT 50 4 3 19 PP 35 51 3 4 20 HGN 36 52 3 5 21 HGN 37 OUT 53 3 6 22 2 3 LK 54 3 7 7 23 L 39 L 55 2 7 24 L 40 L 56 2 9 7 25 LE 41 1 57 2 10 7 26 OUT 42 LGN 5 2 11 6 27 43 N/ 59 1 12 6 2 44 HGN 60 1 13 6 29 OUT 45 HGN 61 1 14 6 30 POL 46 PP 62 1 15 5 31 LGN 47 4 63 PP 16 5 32 IR 4 4 64 HGN 6
64-Lead PQFP (3-Sided) Package Outline (PG) 20.00x14.00mm body, 3.40mm height (max), 0.0mm pitch, 3.90mm footprint L3 64 1 Note 1 (Index rea 1/4 x E1/4) E1 E Note 2 1 b e θ1 Top iew iew 2 1 Side iew Seating Plane L L1 L2 θ iew Gauge Plane Seating Plane Note: 1. Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. The leads on this side are trimmed. Symbol 1 2 b 1 E E1 e L L1 L2 L3 θ θ1 imension (mm) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http:///packaging.html.) does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. ircuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 2013 ll rights reserved. Unauthorized use or reproduction is prohibited. MIN 2.0 0.25 2.55 0.30 22.25 19.0 17.65 13.0 0.73 0 O 5 O NOM - - 2.0-22.50 20.00 17.90 14.00 0.0 1.95 0.25 0.55 0. S REF S REF 3.5 O - MX 3.40 0.50 3.05 0.45 22.75 20.20 1.15 14.20 1.03 7 O 16 O rawings not to scale. Supertex oc. #: SP-64PQFPPG, ersion 0012. 7 1235 ordeaux rive, Sunnyvale, 9409 Tel: 40-222-