High Speed, 200V, Full H-Bridge MOSFET Driver
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1 High Speed, 2V, Full H-Bridge MOSFET MD72 Features HVCMOS technology for high performance All N-MOSFET full-bridge driver Designed for 2V bridge supply voltage Up to.mhz operation frequency Greater than 9% efficiency Designed for low total harmonic distortion Single voltage drive power supply +2V Smart logic voltage threshold Resistor programmable OCP threshold UVP function built-in Accurate and adjustable dead time 32-Lead QFN package General Description The Supertex MD72 is a high voltage, high speed, full-bridge driver. It is ideal for Class-D audio amplifier applications and other high frequency PWM driver applications, such as motor driving. This highvoltage and high-speed driver can also be used for other applications: as a piezo-electric transducer driver; as a MOSFET driver in a switched mode power supply; or as a two channel driver for half-bridge power stages. The new IC topology is designed to drive dual N-MOSFETs as power switches for both the high side and low side. It consists of controller logic circuits, level translators, and a bootstrap floating powered gate driver and over current protection circuits without using current sensing resistors. The thresholds of the OCP for the high and low side are resistor-programmable. Applications Class-D audio amplifier High frequency PWM motor control High frequency switching power supply Ultrasound transducer drivers High voltage waveform generator Typical Application Circuit +2V The power MOSFET top drain can be connected to up to +2V while the bottom N-channel MOSFET source is grounded. They are designed to provide 3.A peak driving current with well-matched output impedence and propagation delay on the high and low sides, as well as from device-to-device. The EN pin serves a dual purpose: the logic high level is used to compute the threshold voltage level of inputs; and the logic low level disables the outputs. The package is low inductance and thermally enhanced. R +2V AVDD VDD VDD2 RP D D BS G GS S R4 C M D3 L +.8 or 5.V Logic EN INA INB OPF GND Logic UVP OTP OCP CTV Monitor V REF G2 GS2 S2 D, D3 S - 4 D3 GS - 4 RP3 BS3 G3 GS3 S3 R5 M2 +2V +2V D2 R8 R6 C2 M3 D4 D5 L2 C3 C4 VSS RDT RP2 G4 GS4 S4 R7 M4 D6 R3 R2 MD72
2 Ordering Information Package Option Device 32-Lead QFN 7.x7.mm body.mm height (max).65 pitch MD72 MD72K6-G -G indicates package is RoHS compliant ( Green ) Absolute Maximum Ratings Parameter Value Pin Configuration 32, (BS-S), (BS3-S3) supply voltage -.5V to 5V V PP, high voltage supply V to +22V EN, IN A, IN B logic input voltage -.5V to 7.5V OPF, open drain output voltage Junction operating temperature range -.5V to 5V -4 C to +25 C Storage temperature -65 C to 5 C Thermal resistance (θ JA )* 29.3 O C/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * oz, 4-layer, 4x3 PCB Product Marking MD72K6 LLLLLLLLL YYWW AAA CCC 32-Lead QFN (K6) (top view) L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = Green Packaging Package may or may not include the following marks: Si or 32-Lead QFN (K6) DC Electrical Characteristics (Over operating conditions, unless otherwise specified. = 2V, V PP = 2V, RDT = 33kΩ, T A = 25 C) Positive drive supply voltage V --- V PP High supply voltage V --- V EN EN input voltage range V --- V PT Input positive threshold % Percent of V EN voltage V NT Input negative threshold % Percent of V EN voltage V HY Input threshold hysteresis % Percent of V EN voltage I DDQ quiescent current, EN = ma --- I DDEN average current - 6. ma INA = INB = I DD average current at 5KHz ma INA = INB = 5KHz, G~4 to S~4 with four pf load capacitors R IN Input logic impedance to GND kω --- C IN Logic input capacitance - 5. pf --- Gate Outputs R HSC Sourcing output resistance Ω I DS = ma R HSK Sinking output resistance Ω I DS = ma R LSC Sourcing output resistance Ω I DS = ma R LSK Sinking output resistance Ω I DS = ma 2
3 Under Voltage and Over Current / Temperature Protection (Over operating conditions, unless otherwise specified. = 2V, V PP = 2V, RDT = 33kΩ, T A = to 7 C) V OL_OPF OPF flag output low voltage -.5. V OPF = low, I PULL_UP =.ma V PULL_UP Open drain pull-up voltage V I OPF =.ma I OPF Maximum OPF sinking current -. - ma OPF load limit V UVT rising threshold V --- V UVH UV hysteresis V --- I RP, I RP3 High-side current reference µa --- I RP2 Low-side current reference µa --- V GS-4 Gate sense voltage threshold V Reference to S-4 T OTP Over-temperature threshold 95 2 O C If over temperature, OPF low and M~4 off T OTH Over-temperature hysteresis O C --- AC Electrical Characteristics (Over operating conditions, unless otherwise specified. = 2V, V PP = 2V, RDT = 33kΩ, T A = to 7 C, f S = 5kHz ) f S Switch frequency - -. MHz --- t dr Switch on delay + dead time - 58 ns When t dt = min, See Switch Timing Diagram t df Switch off delay time - 4 ns See Switch Timing Diagram t r Output rise time - 2 ns With.nF load, t f Output fall time - 2 ns see Switch Timing Diagram t dm Dead time matching, channel to channel - ±5. - RDT = 5kΩ ns - ± - RDT = 33kΩ Δt dtr Dead time adjustable range 5-5 ns RDT = 5kΩ to 33kΩ Δt dta Dead time accuracy - ± ±2 % 5ns to 5ns THD Total Harmonic Distortion % Time jitter contribution, f J = Hz, f S = 5KHz, f A =.KHz t EN Enable ready time ns See Enable Ready Timing Diagram t PWR_UP Power-up time µs See Timing Diagram Logic Table Logic Input Power MOSFET Output EN INA INB A Bridge Output B Bridge Output L L L H H L H H X X Hi-Z Hi-Z 3
4 OCP Threshold vs RP, 2, 3 8 Dead Time vs RDT OCP Threshold (V) Dead Time (ns) RP,2,3 (KΩ) RDT (KΩ) Logic V PT/NT / V EN Curve Enable Ready Timing Diagram V PT/NT V PT EN 2..5 V NT t EN. INA and INB Logic Signals Valid.5.6V V EN Switch Timing Diagram Adjustable Delay Time Diagram INA or INB t df t df G or G3 t dt t dt 9% 9% 9% % % % G2 or G4 G or G3 t r t f 4
5 Pin Description Pin # Name Function GND Logic signal ground. 2 AVDD Logic AVDD voltage supply (+2V). Not connected to VDD or VDD2 internally. 3 INA Input logic control of the half-bridge A output. 4 EN Chip power enable, EN = Hi chip enabled, EN = Lo disabled, EN resets the OPF flag latch. 5 INB Input logic control of the half-bridge B output. 6 OPF Open drain output of over/under voltage, over current or temperature flag, Active = Low. 7 VSS Return of voltage supply. 8 NC Not connected. 9 RDT Dead time program resistor. S4 Low side MOSFET source. G4 Low side MOSFET gate. 2 GS4 Low side MOSFET gate voltage sense. 3 VDD2 4 NC Not connected. Positive voltage supply (+2V). Both VDD and VDD2 must be connected to the same positive supply voltage. 5 S3 High side MOSFET source. 6 G3 High side MOSFET gate. 7 GS3 High side MOSFET gate voltage sense. 8 BS3 High side boost external capacitor. 9 D3 High side MOSFET drain. 2 RP3 High side program resistor OCP threshold for MOSFET M3. 2 RP High side program resistor OCP threshold for MOSFET M. 22 D High side MOSFET drain. 23 BS High side boost external capacitor. 24 GS High side MOSFET gate voltage sense. 25 G High side MOSFET gate. 26 S High side MOSFET source. 27 NC Not connected. 28 VDD Positive voltage supply (+2V). Both VDD and VDD2 must be connected to the same positive supply voltage. 29 GS2 Low side MOSFET gate voltage sense. 3 G2 Low side MOSFET gate. 3 S2 Low side MOSFET source. 32 RP2 Low side program resistor OCP threshold for MOSFET M2 and M4. Note: The thermal pad must be connected to VSS externally. 5
6 32-Lead QFN Package Outline (K6) 7.x7.mm body,.mm height (max),.65mm pitch 32 D D2 32 Note (Index Area D/2 x E/2) Note (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View θ Note 3 A A Side View A3 Seating Plane L Note 2 View B L Notes: A Pin identifier must be located in the index area indicated. The Pin identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Depending on the method of manufacturing, a maximum of.5mm pullback (L) may be present. The inner tip of the lead may be either rounded or square. Dimension (mm) Symbol A A A3 b D D2 E E2 e L L θ MIN * * O NOM REF BSC MAX * * O JEDEC Registration MO-22, Variation VKKC-2, Issue K, June 26 * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-32QFNK67X7P65, Version C49 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http// 29 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-MD72 A Bordeaux Drive, Sunnyvale, CA 9489 Tel:
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