High Speed, 200V, Full H-Bridge MOSFET Driver

Transcription

1 High Speed, 2V, Full H-Bridge MOSFET Features HVCMOS technology for high performance All N-MOSFET full-bridge driver Designed for 2V bridge supply voltage Up to.mhz operation frequency Greater than 9% efficiency Designed for low total harmonic distortion Single voltage drive power supply +2V Smart logic voltage threshold Resistor programmable OCP threshold UVP function built-in Accurate and adjustable dead time 32-Lead QFN package Applications Class-D audio amplifier High frequency PWM motor control High frequency switching power supply Ultrasound transducer drivers High voltage waveform generator Typical Application Circuit General Description The Supertex is a high voltage, high speed, full-bridge driver. It is ideal for Class-D audio amplifier applications and other high frequency PWM driver applications, such as motor driving. This highvoltage and high-speed driver can also be used for other applications: as a piezo-electric transducer driver; as a MOSFET driver in a switched mode power supply; or as a two channel driver for half-bridge power stages. The new IC topology is designed to drive dual N-MOSFETs as power switches for both the high side and low side. It consists of controller logic circuits, level translators, and a bootstrap floating powered gate driver and over current protection circuits without using current sensing resistors. The thresholds of the OCP for the high and low side are resistor-programmable. The power MOSFET top drain can be connected to up to +2V while the bottom N-channel MOSFET source is grounded. They are designed to provide 3.A peak driving current with well-matched output impendence and propagation delay on the high and low sides, as well as from device-to-device. The EN pin serves a dual purpose: the logic high level is used to compute the threshold voltage level of inputs; and the logic low level disables the outputs. The IC is in a low inductance and thermally enhanced package. +2V +2V R A 2 RP D BS G GS S R4 C D M D3 L +.8 or 5.V Logic EN INA INB OPF GND Logic UVP OTP OCP CTV Monitor V REF G2 GS2 S2 D, D3 S - 4 D3 GS - 4 RP3 BS3 G3 GS3 S3 R5 M2 +2V +2V D2 R8 R6 C2 M3 D4 D5 L2 C3 C4 V SS RDT RP2 G4 GS4 S4 R7 M4 D6 R3 R2

2 Ordering Information Device Package Option 32-Lead QFN, 7x7mm body,.mm height (max.),.65 pitch -G indicates package is RoHS compliant ( Green ) K6-G Absolute Maximum Ratings Parameter, (BS-S), (BS3-S3) supply voltage Value -.5V to 5V V PP, high voltage supply V to +22V EN, IN A, IN B logic input voltage -.5V to 7.5V OPF, open drain output voltage Junction operating temperature range -.5V to 5V -4 C to +25 C Storage temperature -65 C to 5 C Thermal resistance (θ JA )* 29.3 O C/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * oz, 4-layer, 4x3 PCB Pin Configuration 32 Product Marking K6 L L L L L L L L L YYWW AAA CCC 32-Lead QFN (K6) (top view) L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = Green Packaging 32-Lead QFN (K6) DC Electrical Characteristics (Over operating conditions, unless otherwise specified. = 2V, V PP = 2V, T A = 25 C) Positive drive supply voltage V --- V PP High supply voltage V --- V EN EN input voltage range.8-5. V --- V PT Input positive threshold % Percent of V EN voltage V NT Input negative threshold % Percent of V EN voltage V HY Input threshold hysteresis % Percent of V EN voltage I DDQ quiescent current, EN= µa --- I DDEN average current ma INA = INB = (measured) I DD average current at 5KHz ma INA = INB = 5KHz, G~4 to S~4 with four pf load capacitors R IN Input logic impedance to GND kω --- C IN Logic input capacitance - 5. pf --- Gate Outputs R HSC Sourcing output resistance Ω I DS =.A R HSK Sinking output resistance Ω I DS =.A R LSC Sourcing output resistance Ω I DS =.A R LSK Sinking output resistance Ω I DS =.A 2

3 Under Voltage and Over Current / Temperature Protection (Over operating conditions, unless otherwise specified. = 2V, V PP = 2V, T A = to 7 C) V OL_OPF OPF flag output low voltage - -. V OPF = low, I PULL_UP =.ma V PULL_UP Open drain pull-up voltage V I OPF =.ma I OPF OPF sinking current limit -..5 ma --- V UVT rising threshold V --- V UVH UV hysteresis V --- I RP, I RP3 High-side current reference µa --- I RP2 Low-side current reference µa --- V GS-4 Gate sense voltage threshold V Reference to S-4 T OTP Over-temperature threshold 95 2 O C If over temperature, OPF low and M~4 off T OTH Over-temperature hysteresis O C --- AC Electrical Characteristics (Over operating conditions, unless otherwise specified. = 2V, V PP = 2V, T A = to 7 C) f S Switch frequency - -. MHz --- t dr Switch on delay + dead time ns When t dt = min t df Switch off delay time ns See timing diagram t r Output rise time ns With.nF load t f Output fall time ns With.nF load t dm Dead time matching - - ±5 ns Channel to channel Δt dtr Dead time adjustable range 5-5 ns RDT =.kω to 2kΩ Δt dta Dead time accuracy - ±5. ± % 5ns to 5ns THD Total Harmonic Distortion % Time jitter contribution, f J = Hz, f S = 5KHz, f A =.KHz t EN Enable ready time ns See timing diagram t PWR_UP Power-up time µs See timing diagram Logic Table Logic Input Power MOSFET Output EN INA INB A Bridge Output B Bridge Output L L L H H L H H X X Hi-Z Hi-Z 3

4 OCP Threshold vs RP, 2, Dead Time vs RDT OCP Threshold (V) RP,2,3 (K) Dead Time (ns) RDT (K) Logic V PT/NT / V EN Curve V PT/NT V PT 2..5 V NT..5.6V V EN Switch Timing Diagram Adjustable Delay Time Diagram INA or INB tdr tdf G or G3 tdt tdt 9% 9% 9% % % % G or G3 tr tf G2 or G4 4

5 Pin Description Pin # Name Function GND Logic signal ground. 2 AVDD Logic AVDD voltage supply (+2V). Not connected to VDD or VDD2 internally. 3 INA Input logic control of the half-bridge A output. 4 EN Chip power enable, EN = Hi chip enabled, EN = Lo disabled, EN resets the OPF flag latch. 5 INB Input logic control of the half-bridge B output. 6 OPF Open drain output of over/under voltage, over current or temperature flag, Active = Low. 7 VSS Return of voltage supply. 8 NC Not connected. 9 RDT Dead time program resistor. S4 Low side MOSFET source. G4 Low side MOSFET gate. 2 GS4 Low side MOSFET gate voltage sense. 3 VDD2 Positive voltage supply (+2V). May not connected to VDD internally. 4 NC Not connected. 5 S3 High side MOSFET source. 6 G3 High side MOSFET gate. 7 GS3 High side MOSFET gate voltage sense. 8 BS3 High side boost external capacitor. 9 D3 High side MOSFET drain. 2 RP High side program resistor OCP threshold for MOSFET M. 2 RP3 High side program resistor OCP threshold for MOSFET M3. 22 D High side MOSFET drain. 23 BS High side boost external capacitor. 24 GS High side MOSFET gate voltage sense. 25 G High side MOSFET gate. 26 S High side MOSFET source. 27 NC Not connected. 28 VDD Positive voltage supply (+2V). May not connected to VDD2 internally. 29 GS2 Low side MOSFET gate voltage sense. 3 G2 Low side MOSFET gate. 3 S2 Low side MOSFET source. 32 RP2 Low side program resistor OCP threshold for MOSFET M2 and M4. Note: The thermal pad must be connected to VSS externally. 5

6 32-Lead QFN Package Outline (K6) 7x7mm body,.mm height (max),.65mm pitch 32 D D2 32 Note (Index Area D/2 x E/2) Note (Index Area D/2 x E/2) e E E2 b View B Top View Bottom View θ Note 3 A A Side View A3 Seating Plane L Note 2 View B L Notes:. Details of Pin identifier are optional, but must be located within the indicated area. The Pin identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of.5mm pullback (L) may be present. 3. The inner tip of the lead may be either rounded or square. Dimension (mm) Symbol A A A3 b D D2 E E2 e L L θ MIN * *.45*. O.2.65 NOM * *.55* - - REF BSC MAX * *.65*.5 4 O JEDEC Registration MO-22, Variation VKKC-, Issue K, June 26 * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings not to scale. Supertex Doc. #: DSPD-32QFNK67X7P65, Version A688 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to Doc.# DSFP- NR6258 6