Four-Channel, High Speed, ±65V 750mA Ultrasound Pulser. General Description C2 C3 C4 VSUB. P-Driver. N-Driver. RGND 1 of 4 Channels GREF VNF HV738

Transcription

1 Supertex inc. HV738 Four-Channel, High Speed, ±65V 750mA Ultrasound Pulser Features HVCMOS technology for high performance High density integration ultrasound transmitter 0 to ±65V output voltage ±750mA source and sink current in Pulse mode ±110mA source and sink current in CW mode Up to 20MHz operating frequency Matched delay times 1.2 to 5.0V CMOS logic interface Built-in output drain bleed resistors Application Portable medical ultrasound imaging Piezoelectric transducer drivers NDT ultrasound transmission Pulse waveform generator General Description The Supertex HV738 is a four-channel, monolithic, high voltage, high speed pulse generator. It is designed for portable medical ultrasound applications. This high voltage and high speed integrated circuit can also be used for piezoelectric, capacitive or MEMS sensing in ultrasonic nondestructive detection and sonar ranger applications. The HV738 consists of a controller logic interface circuit, level translators, MOSFET gate drivers and high power P-channel and N-channel MOSFETs as the output stage for each channel. The output stages of each channel are designed to provide peak output currents over ±1.1A for pulsing, when in mode 4, with up to ±65 volt swings. When in mode 1, all the output stages drop the peak current to ±140mA for low-voltage CW mode operation to decrease the power consumption of the IC. The P and N type of power FETs gate drivers are supplied by two floating 8.0VDC power supplies referenced to VPP and VNN. This direct coupling topology of the gate drivers not only eliminates two high voltage capacitors per channel, but also makes the PCB layout easier. Typical Application Circuit +1.5 to 2.5V +8.0V +65V VPP -8.0V 0 to +65V C1 C2 C3 C4 C5 VLL VDD VSUB VPF VPP OTP EN EN_PWR SUB RGND MC to 2.5V Logic MC1 PIN1 Level Translator P-Driver R P1 D1 TXP1 TXN1 HV OUT 1 NIN1 Level Translator N-Driver R N1 D2 X1 RGND 1 of 4 Channels GREF VSS HV738 VNF C7 +8V VNN C6 0 to -65V

2 Ordering Information Device 48-Lead QFN 7.00x7.00mm body 1.00mm height (max) 0.50mm pitch HV738 -G indicates package is RoHS compliant ( Green ) HV738K6-G Absolute Maximum Ratings Parameter V SS, Power supply reference Value, Positive logic supply -0.5V to +7V, Positive logic and level translator supply -0.5V to +14V ( - ) Positive floating gate drive supply -0.5V to +14V ( - ) Negative gate floating drive supply -0.5V to +14V ( - ) Differential high voltage supply +140V, High voltage positive supply -0.5V to +70V, High voltage negative supply +0.5V to -70V OTP, Over Temperature Protection output -0.5V to +7V All logic input PIN X, NIN X and EN voltages -0.5V to +7V (V SUB - V SS ) Substrate to V SS voltage difference +140V ( TXP X ) to TXP X voltage difference +140V (V SUB - TXP X ) Substrate to TXP X voltage difference +140V (TXN X - ) TXN X to voltage difference +140V Operating temperature -40 C to 125 C Storage temperature -65 C to 150 C Thermal resistance, θ JA Thermal resistance, θ JC (Junction to thermal pad) 0V 29 C/W 0.5 C/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configuration Package Marking 1 48 HV738K6 LLLLLLLLL YYWW AAA CCC 48-Lead QFN (top view) L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = Green Packaging Package may or may not include the following marks: Si or 48-Lead QFN Power-Up Sequence Step Description 1 V SUB 2 with logic signal low 3 4 ( - ) and ( ) 5 and 6 Logic control signals Power-Down Sequence Step Description 1 All logic signals go to low 2 and 3 ( - ) and ( ) V SUB 2

3 Operating Supply Voltages and Current (4 Channel Active) (Operating conditions, unless otherwise specified, V SS = 0V, = +2.5V, = +8V, - = +8V, - = -8V, =+65V, = -65V, T A = 25 C) Logic voltage reference V --- Internal voltage supply V --- Positive gate driver supply ( -10) ( -8.0) ( -7.5) V Negative gate drive supply ( +7.5) ( +8.0) ( +10) V Floating driver voltage supplies. V SUB IC substrate voltage +65 V Must be the most positive potential of the IC. Positive HV supply V --- Negative HV supply V --- SR MAX Slew rate limit of, V/μs Built-in slew rate detection protection. I LL Current EN = Low μa --- I DDQ Current EN = Low μa --- I DDEN Current EN = High ma f = 0MHz I DDEN Current MODE = ma I DDENCW Current MODE = ma I PPQ Current EN = Low μa f = 0MHz I PPEN Current MODE = ma I PPENCW Current MODE = ma I NNQ Current EN = Low μa f = 0MHz I NNEN Current MODE = ma I NNENCW Current MODE = ma I PFQ Current EN = Low μa f = 0MHz I PFEN Current MODE = ma I PFENCW Current MODE = ma I NFQ Current EN = Low μa f = 0MHz I NFEN Current MODE = ma I NFENCW Current MODE = ma Under Voltage and Over Temperature Protection V PULL_UP Open drain pull-up voltage V --- V UVDD threshold V --- V UVLL threshold V --- V UVVF, threshold V --- V OL_OTP OTP flag output low voltage V I OTP Max. open drain output current T OTP Over temperature threshold T HYS OTP output reset hysteresis ma --- C = 2.5V, OTP = Active, I PULL_UP = 1.0mA. If over temperature occurred, OTP low and all TX outputs will be HiZ. 3

4 DC Electrical Characteristics (Operating conditions, unless otherwise specified, V SS = 0V, = +2.5V, = +8V, - = +8V, - = -8V, = +65V, = -65V,T A = 25 C) Output P-Channel MOSFET, TXP (Mode 4) I OUT Output saturation current A --- R ON Channel resistance Ω I SD = 100mA C OSS Output capacitance - 50* - pf V DS = 25V, f = 1.0MHz Output N-Channel MOSFET, TXN (Mode 4) I OUT Output saturation current A --- R ON Channel resistance Ω I SD = 100mA C OSS Output capacitance - 20* - pf V DS = 25V, f = 1.0MHz MOSFET Drain Bleed Resistor R P/N1~4 Output bleed resistance kω --- P RO Bleed resistors power limit mw --- Logic Inputs V IH Input logic high voltage ( -0.4) - V --- V IL Input logic low voltage V --- I IH Input logic high current μa --- I IL Input logic low current μa --- C IN Input logic capacitance * pf --- AC Electrical Characteristics (Operating conditions, unless otherwise specified, V SS = 0V, = +2.5V, = +8V, - = +8V, - = -8V, = +65V, = -65V, T A = 25 C) t r Output rise time ns t f Output fall time ns f OUT Output frequency range MHz HD2 Second harmonic distortion - -35* - db t EN Enable time μs t DIS Disable time μs 330pF//2.5kΩ load 100Ω resistor load t dr Delay time on inputs rise ns 7.5Ω resistor load t df Delay time on inputs fall ns (see timing diagram) Δt DELAY Delay time matching - ±3.0 - ns P to N, channel to channel t dm Delay on mode change μs 100Ω resistor load t j Delay jitter on rise or fall - 13* - ps / = ±25V, input t r to HV OUT t r or t f, with 330pF//2.5kΩ load * Guaranteed by design. 4

5 Switch AC Test Timing Diagram NINx PINx t dr 90% t df Output 10% 0 t 10% r t r 90% V SUB OTP EN EN_PWR SUB RGND MC0 MC1 PIN1 Level Translator P-Driver R P1 TXP1 TXN1 NIN1 Level Translator N-Driver R N1 R2 R1 1of n Channels RGND G REF V SS PINx NINx t dfp t drp I OUT t drn t dfn TXPx 0A TXNx 0A I OUT 5

6 Truth Table (All Modes) Logic Inputs Output Pin Description Pin # Name Function 1 VDD Positive internal voltage supply (+8.0V). 2 VSS Power supply return (0V). 3 PIN1 Input logic control of high voltage output P-FET of channel 1, Hi = on, Low = off. 4 NIN1 Input logic control of high voltage output N-FET of channel 1, Hi = on, Low = off. 5 PIN2 Input logic control of high voltage output P-FET of channel 2, Hi = on, Low = off. 6 NIN2 Input logic control of high voltage output N-FET of channel 2, Hi = on, Low = off. 7 PIN3 Input logic control of high voltage output P-FET of channel 3, Hi = on, Low = off. 8 NIN3 Input logic control of high voltage output N-FET of channel 3, Hi = on, Low = off. 9 PIN4 Input logic control of high voltage output P-FET of channel 4, Hi = on, Low = off. 10 NIN4 Input logic control of high voltage output N-FET of channel 4, Hi = on, Low = off. 11 VSS Power supply return (0V). 12 VDD Positive internal voltage supply (+8.0V). 13 OTP Over temperature protection output, open N-FET drain, active low if IC temperature >110 C. 14 MC1 15 MC0 16 EN PIN X NIN X TXP X TXN X OFF OFF ON OFF OFF ON ON ON 0 X X OFF OFF Not allowed, may damage IC. Drive Mode Control Table Mode MC1 MC Notes: 1. / = +/-65V, = ( ) = ( ) = +8.0V 2. I SC is current into 1.0Ω to GND 3. R ON calculated from V OUT into 100Ω load Thermal Pad (VSUB) Output current mode control pins, see Drive Mode Control Table. Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to VSUB, the most positive potential of the IC externally. 17 VPF P-FET drive floating power supply, ( - ) = +8.0V. I SC (A) R ONP (Ω) R ONR (Ω) 6

7 Pin Description (cont.) Pin # Name Function VPP Positive high voltage power supply (+65V) VNN VNF Negative high voltage power supply (-65V). N-FET drive floating power supply, ( - ) = +8.0V. 25 Thermal Pad (VSUB) Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to VSUB, the most positive potential of the IC externally. 26 RGND Bleed resistors common return ground. (Both pins must be used) 27 TXN4 Output N-FET drain (open drain output) for channel TXP4 Output P-FET drain (open drain output) for channel TXN3 Output N-FET drain (open drain output) for channel TXP3 Output P-FET drain (open drain output) for channel TXN2 Output N-FET drain (open drain output) for channel TXP2 Output P-FET drain (open drain output) for channel TXN1 Output N-FET drain (open drain output) for channel TXP1 Output P-FET drain (open drain output) for channel RGND Bleed resistors common return ground. (Both pins must be used) 36 Thermal Pad (VSUB) Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to VSU B, the most positive potential of the IC externally. 37 VNF N-FET drive floating power supply, ( - ) = +8.0V VNN Negative high voltage power supply (-65V) VPP VPF Positive high voltage power supply (+65V). P-FET drive floating power supply, ( - ) = +8.0V. 45 Thermal Pad (VSUB) Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to VSUB, the most positive potential of the IC externally. 46 EN Chip power enable Hi = on, Low = off. 47 GREF Logic Low reference, logic ground (0V). 48 VLL Logic Hi voltage reference input (+2.5V). 7

8 48-Lead QFN Package Outline (K6) 7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch 48 D D2 48 Note 1 (Index Area D/2 x E/2) 1 1 Note 1 (Index Area D/2 x E/2) e E E2 b Top View Bottom View View B θ Note 3 A A1 Side View A3 Seating Plane Note 2 L1 View B L Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol A A1 A3 b D D2 E E2 e L L1 θ MIN * * O Dimension NOM (mm) REF BSC - - MAX * * O JEDEC Registration MO-220, Variation VKKD-6, Issue K, June * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings are not to scale. Supertex Doc.#: DSPD-48QFNK67X7P050, Version C (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http// Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV738 C Supertex inc Bordeaux Drive, Sunnyvale, CA Tel: