DATASHEET EL8, EL8, EL8 MHz Rail-to-Rail Amplifiers FN7 Rev. The EL8, EL8, and EL8 represent rail-to-rail amplifiers with a -3dB bandwidth of MHz and slew rate of V/µs. Running off a very low supply current of ma per channel, the EL8, EL8, and EL8 also feature inputs that go to.v below the V S - rail. The EL8 and EL8 are dual channel amplifiers. The EL8 is a quad channel amplifier. The EL8 includes a fast-acting disable/power-down circuit. With a ns disable and a ns enable, the EL8 is ideal for multiplexing applications. The EL8, EL8, and EL8 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8 is available in a Ld MSOP package, the EL8 in an 8 Ld SO package, and the EL8 in a Ld SO and 6 Ld QSOP packages. All are specified for operation over the - C to +8 C temperature range. Features MHz -3dB bandwidth V/µs slew rate Low supply current = ma per channel Supplies from 3V to.v Rail-to-rail output Input to.v below V S - Fast ns disable (EL8 only) Low cost Pb-free available (RoHS compliant) Applications Video amplifiers Portable/hand-held products Communications devices Pinouts EL8 (8 LD SO) TOP VIEW EL8 ( LD MSOP) TOP VIEW OUTA 8 VS+ INA+ INA- 3 - + - + 7 6 INA- INA+ VS- OUTB INB- INB+ CEA VS- CEB 3 - + + - 9 8 7 OUTA VS+ OUTB INB+ 6 INB- EL8 ( LD SO) TOP VIEW EL8 (6 LD QSOP) TOP VIEW OUTA OUTD OUTA 6 OUTD INA- A D - + + - 3 IND- INA- - + + - IND- INA+ 3 IND+ INA+ 3 IND+ VS+ VS- VS+ 3 VS- INB+ INC+ INB+ INC+ INB- OUTB 6 7 - + + - B C 9 8 INC- OUTC INB- OUTB 6 7 - + + - INC- OUTC NC 8 9 NC FN7 Rev. Page of 6
Ordering Information PART NUMBER (See Note) PART MARKING PACKAGE (RoHS Compliant) PKG. DWG. # EL8IYZ (No longer available, recommended replacement: EL8ISZ) EL8IYZ-T7* (No longer available, recommended replacement: EL8ISZ-T7) EL8IYZ-T3* (No longer available, recommended replacement: EL8ISZ-T3) BAMAA Ld MSOP MDP3 BAMAA Ld MSOP MDP3 BAMAA Ld MSOP MDP3 EL8ISZ 8ISZ 8 Ld SO MDP7 EL8ISZ-T7* 8ISZ 8 Ld SO MDP7 EL8ISZ-T3* 8ISZ 8 Ld SO MDP7 EL8ISZ (No longer available or supported) EL8ISZ-T7* (No longer available or supported) EL8ISZ-T3* (No longer available or supported) EL8IUZ (No longer available or supported) EL8IUZ-T7* (No longer available or supported) EL8IUZ-T3* (No longer available or supported) 8ISZ Ld SO MDP7 8ISZ Ld SO MDP7 8ISZ Ld SO MDP7 8IUZ 6 Ld QSOP MDP 8IUZ 6 Ld QSOP MDP 8IUZ 6 Ld QSOP MDP *Please refer to TB37 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. FN7 Rev. Page of 6
Absolute Maximum Ratings (T A = C) Supply Voltage from V S + to V S -.........................V Input Voltage........................ V S + +.3V to V S - -.3V Differential Input Voltage................................V Continuous Output Current........................... ma Power Dissipation............................. See Curves Storage Temperature........................-6 C to + C Ambient Operating Temperature................- C to +8 C Operating Junction Temperature...................... + C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = V, V S - = GND, T A = C, V CM =.V, R L to.v, A V =, Unless Otherwise Specified PARAMETER DESCRIPTION CONDITIONS MIN (Note ) TYP MAX (Note ) UNIT INPUT CHARACTERISTICS V OS Offset Voltage -6 -.8 +6 mv TCV OS Offset Voltage Temperature Coefficient Measured from T MIN to T MAX 3 µv/ C IB Input Bias Current V IN = V -. -.6 µa I OS Input Offset Current V IN = V.. µa TCI OS Input Bias Current Temperature Coefficient Measured from T MIN to T MAX na/ C CMRR Common Mode Rejection Ratio V CM = -.V to +3.V (EL8,EL8) 7 9 db V CM = -.V to +3.V (EL8) 6 9 db CMIR Common Mode Input Range V S - -. V S + -. V R IN Input Resistance Common Mode 6 M C IN Input Capacitance. pf A VOL Open Loop Gain V OUT = +.V to +3.V, R L = k to GND 7 9 db V OUT = +.V to +3.V, R L = to GND 8 db OUTPUT CHARACTERISTICS R OUT Output Resistance A V = + 3 m V OP Positive Output Voltage Swing R L = k.8.9 V R L =.6.7 V V ON Negative Output Voltage Swing R L = mv R L = k 3 mv I OUT Linear Output Current 6 ma I SC (source) Short Circuit Current R L = 6 7 ma I SC (sink) Short Circuit Current R L = 3 ma POWER SUPPLY PSRR Power Supply Rejection Ratio V S + =.V to.v 7 db I S-ON Supply Current. ma I S-OFF Supply Current - Disabled per Amplifier EL8 only 9 µa ENABLE (EL8 ONLY) t EN Enable Time ns t DS Disable Time ns V IH-ENB ENABLE Pin Voltage for Power-up.8 V FN7 Rev. Page 3 of 6
Electrical Specifications V S + = V, V S - = GND, T A = C, V CM =.V, R L to.v, A V =, Unless Otherwise Specified (Continued) PARAMETER DESCRIPTION CONDITIONS MIN (Note ) TYP MAX (Note ) UNIT V IL-ENB ENABLE Pin Voltage for Shut-down V I IH-ENB ENABLE Pin Input Current High 8.6 µa I IL-ENB ENABLE Pin Input for Current Low. µa AC PERFORMANCE BW -3dB Bandwidth A V = +, R F =, C L =.pf MHz A V = -, R F = k, C L =.pf 9 MHz A V = +, R F = k, C L =.pf 9 MHz A V = +, R F = k, C L =.pf MHz BW ±.db Bandwidth A V = +, R F =, C L =.pf MHz Peak Peaking A V = +, R F = k, C L =.pf db GBWP Gain Bandwidth Product MHz PM Phase Margin R L = k, C L =.pf SR Slew Rate A V =, R L =, V OUT =.V to.v 6 V/µs t R Rise Time.V STEP, % - 8% 8 ns t F Fall Time.V STEP, % - 8% 7 ns OS Overshoot mv step % t PD Propagation Delay mv step ns t S.% Settling Time mv step ns dg Differential Gain A V = +, R F = k, R L =.3 % dp Differential Phase A V = +, R F = k, R L =. e N Input Noise Voltage f = khz nv/ Hz i N + Positive Input Noise Current f = khz pa/ Hz i N - Negative Input Noise Current f = khz.8 pa/ Hz e S Channel Separation f = khz 9 db NOTE:. Parts are % tested at + C. Over-temperature limits established by characterization and are not production tested. Pin Descriptions EL8 ( Ld SO) EL8 (8 Ld SO) EL8 ( Ld SO) EL8 (6 Ld QSOP) NAME FUNCTION, 3, 3,,, 3,,, IN+ Non-inverting input for each channel, CE Enable and disable input for each channel 3 3 VS- Negative power supply 6,, 6, 6, 9, 3, 6,, IN- Inverting input for each channel 7, 9, 7, 7, 8,, 7,, 6 OUT Amplifier output for each channel 8 8 VS+ Positive power supply FN7 Rev. Page of 6
Typical Performance Curves A V = C L =.pf V OP-P =mv A V = C L =.pf R L =33 GAIN (db) - - V OP-P =V V OP-P =V GAIN (db) - - R L = -6 K M M M G FIGURE. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS -6 K M M M G FIGURE. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS R LOAD NORMALIZED GAIN (db) - - C L =.pf A V = A V = A V = A V = NORMALIZED GAIN (db) - - C L =.pf R F =k A V =- A V =- A V =- -6 K M M M G FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS NON-INVERTING GAINS -6 K M M M G FIGURE. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS INVERTING GAINS C L =pf C L =6pF 3 C L =7pF 8 C L =3pF GAIN (db) - -3 A V = V OP-P =mv C L =pf C L =.pf - K M M M G GAIN (db) 6 C L =pf C L =.pf - - A V = R F =R G =k -6 K M M M G FIGURE. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS C L FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS C L FN7 Rev. Page of 6
Typical Performance Curves (Continued) 8 R F =R G =k R F =R G =k 7 R L = 3 GAIN (db) 6 R F =R G = GAIN (db) 3 - R L = 3 PHASE ( ) A V = C L =.pf K M M M G FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS R F AND R G - -9 - K K K M M M G FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY - 3 CMRR (db) -3 - -7-9 - K M M M BANDWIDTH (MHz) 9 7 3 A V = 9 7 C L =.pf A V = 3 3... V S (V) FIGURE 9. COMMON-MODE REJECTION RATIO vs FREQUENCY FIGURE. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE. IMPEDANCE ( ).. K K M M M PEAKING (db).. A V = C L =.pf 3 3... V S (V) FIGURE. OUTPUT IMPEDANCE vs FREQUENCY FIGURE. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE FN7 Rev. Page 6 of 6
Typical Performance Curves (Continued) PSRR (db) - -3 - -7-9 PSRR- PSRR+ DISTORTION (dbc) - - -6-7 -8 C L =.pf A V = HD@MHz HD@MHz HD3@MHz HD3@MHz HD@MHz HD3@MHz - K K K M M M FIGURE 3. POWER SUPPLY REJECTION RATIO vs FREQUENCY -9 3 V OP-P (V) FIGURE. HARMONIC DISTORTION vs OUTPUT VOLTAGE GAIN (db) - -3 - -7-9 A V = C L =.pf - K K K M M M G DISTORTION (dbc) -3 - - -6-7 -8-9 - V O =V P-P for A V = V O =V P-P for A V = HD@A V = HD3@A V = HD3@A V = HD@A V = FREQUENCY (MHz) FIGURE. DISABLED OUTPUT ISOLATION FREQUENCY RESPONSE FIGURE 6. HARMONIC DISTORTION vs FREQUENCY -6 K DISTORTION (dbc) -6-7 -7-8 -8 HD3@A V = HD3@A V = HD@A V = HD@A V = -9-9 V O =V P-P for A V = V O =V P-P for A V = - K K R LOAD ( ) VOLTAGE NOISE (nv/ Hz) CURRENT NOISE (pa/ Hz) e N I N + I N -. K K K M M FIGURE 7. HARMONIC DISTORTION vs LOAD RESISTANCE FIGURE 8. VOLTAGE AND CURRENT NOISE vs FREQUENCY FN7 Rev. Page 7 of 6
Typical Performance Curves (Continued) CHANNEL SEPARATION (db) - - -3 - - -6-7 -8-9 CH <=> CH - K M M M G FIGURE 9. CHANNEL SEPARATION vs FREQUENCY (EL8 AND EL8) CHANNEL SEPARATION (db) - - -3 - - -6-7 CH <=> CH CH3 <=> CH -8-9 CH <=> CH3, CH CH <=> CH3, CH - K M M M G FIGURE. CHANNEL SEPARATION vs FREQUENCY (EL8), A V =, to.v, A V =, to.v.. ns/div FIGURE. LARGE SIGNAL TRANSIENT RESPONSE µs/div FIGURE. OUTPUT SWING, A V =, to.v C L =.pf, A V =, to.v.6... ns/div FIGURE 3. SMALL SIGNAL TRANSIENT RESPONSE µs/div FIGURE. OUTPUT SWING FN7 Rev. Page 8 of 6
Typical Performance Curves (Continued) V S =±.V, A V =, V S =±.V, A V =, CH ENABLE INPUT CH ENABLE INPUT CH OUTPUT CH V OUT CH, CH,.V/DIV, M=ns CH, CH, V/DIV, M=ns FIGURE. DISABLED RESPONSE (EL8) FIGURE 6. ENABLED RESPONSE (EL8) POWER DISSIPATION (W) JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD...8.6...36W 99mW 893mW 87mW MSOP JA = C/W SO JA =88 C/W SO8 JA = C/W QSOP6 JA = C/W 7 8 AMBIENT TEMPERATURE ( C) FIGURE 7. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.9 833mW.8.7 6mW.6 633mW SO8. JA =6 C/W. 86mW.3. MSOP JA =6 C/W SO JA = C/W QSOP6 JA =8 C/W. 7 8 AMBIENT TEMPERATURE ( C) FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Simplified Schematic Diagram V S+ I I R 6 R 7 R 8 Q Q 6 V BIAS Q 7 R 3 R R IN+ Q Q IN- DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR OUT V BIAS Q 3 Q Q 8 R R R 9 V S- FN7 Rev. Page 9 of 6
Description of Operation and Application Information Product Description The EL8, EL8 and EL8 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. The amplifiers are internally compensated for closed loop gain of + of greater. Connected in voltage follower mode and driving a k load, they have a -3dB bandwidth of MHz. Driving a load, the bandwidth is about 3MHz while maintaining a V/us slew rate. The EL8 is available with a power down pin to reduce power to 3µA typically while the amplifier is disabled. Input, Output and Supply Voltage Range The EL8, EL8 and EL8 have been designed to operate with a single supply voltage from 3V to.v. Split supplies can also be used as long as their total voltage is within 3V to.v. The amplifiers have an input common mode voltage range from.v below the negative supply (V S - pin) to within.v of the positive supply (V S + pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The output of the EL8, EL8 and EL8 can swing rail to rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor k, the output swing is about.9v at a V supply. For the load resistor, the output swing is about.6v. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier s phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, R F has some maximum value that should not be exceeded for optimum performance. If a large value of R F must be used, a small capacitor in the few Pico farad range in parallel with R F can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. R F and R G appear in parallel with R L for gains other than +. As this combination gets smaller, the bandwidth falls off. Consequently, R F also has a minimum value that should not be exceeded for optimum performance. For gain of +, R F = is optimum. For the gains other than +, optimum response is obtained with R F between 3 to k. The EL8, EL8 and EL8 have a gain bandwidth product of MHz. For gains, its bandwidth can be predicted by the following equation: Gain BW = MHz Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of, because the change in output current with DC level. Special circuitry has been incorporated in the EL8, EL8 and EL8 to reduce the variation of the output impedance with the current output. This results in dg and dp specifications of.3% and., while driving at a gain of. Driving high impedance loads would give a similar or better dg and dp performance. Driving Capacitive Loads and Cables The EL8, EL8 and EL8 can drive pf loads in parallel with k with less than db of peaking at gain of +. If less peaking is desired in applications, a small series resistor (usually between to ) can be placed in series with the output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than, the gain resistor R G can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier s output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down The EL8 can be disabled and placed its output in a high impedance state. The turn off time for each channel is about ns and the turn on time is about ns. When disabled, the amplifier s supply current is reduced to 3µA typically, thereby effectively eliminating the power consumption. The amplifier s power down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to V S - pin. Letting the ENABLE pin float or applying a signal that is less than.8v above V S - will enable the amplifier. The amplifier will be disabled when the signal at ENABLE pin is V above V S -. Output Drive Capability The EL8, EL8 and EL8 do not have internal short circuit protection circuitry. They have a typical short circuit current of 7mA sourcing and ma sinking for the output is connected to half way between the rails with a resistor. If the output is shorted indefinitely, the power FN7 Rev. Page of 6
dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±ma. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL8, EL8 and EL8, it is possible to exceed the C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX T AMAX PD MAX = -------------------------------------------- JA Where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing: V OUTi PD MAX = V S I SMAX + V S V OUTi ---------------- R Li For sinking: PD MAX = V S I SMAX + V OUTi V S - I LOADi Where: V S = Total supply voltage I SMAX = Maximum quiescent supply current V OUTi = Maximum output voltage of the application for each channel R LOADi = Load resistance tied to ground for each channel I LOADi = Load current for each channel By setting the two PD MAX equations equal to each other, we can solve the output current and R LOADi to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - pin is connected to the ground plane, a single.7µf tantalum capacitor in parallel with a.µf ceramic capacitor from V S + to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the V S - pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier s inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Typical Applications VIDEO SYNC PULSE REMOVER Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure 9 shows a gain of connections. Figure 3 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. MULTIPLEXER Besides the normal power down usage, the ENABLE pin of the EL8 can be used for multiplexing applications. Figure 3 shows two channels with the outputs tied together, driving a back terminated 7 video load. A V P-P MHz sine wave is applied to Amp A and a V P-P MHz sine wave is applied to Amp B. Figure 3 shows the ENABLE signal and the resulting output waveform at V OUT. Observe the break-before-make operation of the multiplexing. Amp A is on and V IN is passed through to the output when the ENABLE signal is low and turns off in about ns when the ENABLE signal is high. About ns later, Amp B turns on and V IN is passed through to the output. The break-beforemake operation ensures that more than one amplifier isn t trying to drive the bus at the same time. V IN 7 K + - V K V S+ V S- 7 FIGURE 9. SYNC PULSE REMOVER 7 V OUT FN7 Rev. Page of 6
V IN V.V V V AC gain. C isolates the virtual ground potential. R T and R 3 are the termination resistors for the line. C, C and C 3 are selected big enough to minimize the droop of the luminance signal. V B MHz V P-P 7W V OUT M = µs/div FIGURE 3. VIDEO SIGNAL + - +.V -.V.V V V IN R T 7W C 7µF R K R G kw R K + - R F kw C µf C 3 7µF R 3 7W V OUT 7W FIGURE 33. V SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER K K 7W V OUT R F k A MHz + V P-P - 7W K +.V -.V K 7W V IN R T 7 C 7µF R K R G V - + V C 3 7µF R 3 7 V OUT 7 ENABLE R K C µf FIGURE 3. TWO TO ONE MULTIPLEXER ENABLE A M = ns/div FIGURE 3. ENABLE SIGNAL V -.V -.V -.V SINGLE SUPPLY VIDEO LINE DRIVER The EL8, EL8 and EL8 are wideband rail-to-rail output op amplifiers with large output current, excellent dg, dp, and low distortion that allow them to drive video signals in low supply applications. Figure 33 is the single supply noninverting video line driver configuration and Figure 3 is the inverting video ling driver configuration. The signal is AC coupled by C. R and R are used to level shift the input and output to provide the largest output swing. R F and R G set the B V V -V FIGURE 3. V SINGLE SUPPLY INVERTING VIDEO LINE DRIVER 3 A V = - A V = - - -3 - - K M M M M FIGURE 3. VIDEO LINE DRIVER FREQUENCY RESPONSE NORMALIZED GAIN (db) FN7 Rev. Page of 6
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN7. Updated Ordering Information table on page. Added Revision History and About Intersil sections. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN7 Rev. Page 3 of 6
Small Outline Package Family (SO) A D h X N (N/)+ E E PIN # I.D. MARK c A SEE DETAIL X B. M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE.. C. M C A B b A DETAIL X L ± MDP7 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (.3 ) SO SO SO8 SYMBOL SO-8 SO- (. ) (SOL-6) (SOL-) (SOL-) (SOL-8) TOLERANCE NOTES A.68.68.68.... MAX - A.6.6.6.7.7.7.7.3 - A.7.7.7.9.9.9.9. - b.7.7.7.7.7.7.7.3 - c.9.9.9..... - D.93.3.39.6..66.7., 3 E.36.36.36.6.6.6.6.8 - E....9.9.9.9., 3 e....... Basic - L....3.3.3.3.9 - L....6.6.6.6 Basic - h.3.3.3.... Reference - N 8 6 6 8 Reference - Rev. M /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M-99 FN7 Rev. Page of 6
Quarter Size Outline Plastic Packages Family (QSOP) A N D (N/)+ MDP QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP6 QSOP QSOP8 TOLERANCE NOTES E E PIN # I.D. MARK A.68.68.68 Max. - A.6.6.6 ±. - A.6.6.6 ±. - b... ±. - B. C A B (N/) c.8.8.8 ±. - D.93.3.39 ±., 3 E.36.36.36 ±.8 - C SEATING PLANE. C e.7 C A B b H E... ±., 3 e... Basic - L... ±.9 - L... Basic - N 6 8 Reference - c L SEE DETAIL "X" A Rev. F /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M-99. A GAUGE PLANE. A DETAIL X L ± FN7 Rev. Page of 6
Mini SO Package Family (MSOP). M C A B A D (N/)+ N MDP3 MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL MSOP8 MSOP TOLERANCE NOTES A.. Max. - A.. ±. - E E PIN # I.D. A.86.86 ±.9 - b.33.3 +.7/-.8 - c.8.8 ±. - B (N/) D 3. 3. ±., 3 E.9.9 ±. - E 3. 3. ±., 3 C e H e.6. Basic - L.. ±. - SEATING PLANE. C N LEADS c L b SEE DETAIL "X".8 M C A B A L.9.9 Basic - N 8 Reference - Rev. D /7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M-99. A GAUGE PLANE. A L DETAIL X 3 ±3 Copyright Intersil Americas LLC -. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7 Rev. Page 6 of 6