(TH1B-01 ) 10W Ultra-Broadband Power Amplifier Amin K. Ezzeddine and Ho. C. Huang AMCOM Communications, Inc 401 Professional Drive, Gaithersburg, MD 20879, USA Tel: 301-353-8400 Email: amin@amcomusa.com
Outline Introduction Two-Step Design Concept: - Step-1: 50-ohm unit-cell PA design - Step-2: Power combiner / impedance transformer design Measured results Conclusion
Introduction Broadband PA (f 2 / f 1 >/= 100) design is a major challenge Common approach is Traveling Wave Amplifier (TWA) This paper presents an alternative approach, which uses smaller semiconductor real estate, smaller PA size, and lower cost. This PA has several potential applications for broadband communications, Software radio, Broadband jammer, Instrumentations etc
Basic Design Concept The design concept uses a 2-step approach: Step-1: Design a unit-cell PA with optimal output 50Ω impedance, such that no matching is required. We use HIFET technique to maximize the output power. Step-2: Use broadband push-pull power combiner/ impedance transformer to power combine the unitcell PA, in low impedance environment, to achieve high power.
Output power of unit-cell FET Assuming a DC-to-RF power efficiency of 50% we have: P rf = 0.5 V dc x I dc (1) The optimal RF output impedance is proportional to: R opt = V dc / I dc (2) Substituting equation (2) into equation (1), we have: P rf = V dc2 / (2 R opt ) (3) Therefore, the device output power capability is proportional to the square of DC bias voltage and inversely proportional to the circuit impedance.
Step 1: Use HIFET to increase Vd and Tailor Zopt to be 50-ohm HIFET is an innovative power combining technique, connecting unit-cell FETs RF & DC in series, yet thermally in parallel DC bias voltage and Zopt are proportional to the number of unit cells. Output impedance could be tailored to be 50Ω Hence no output matching HIFET enjoys a bonus gain of 10 Log 10 (N) db. HIFET concept applies to all devices such as MESFET, CMOS, LDMOS, GaN, SiC etc.
1. 5 1 0. 5 0-0. 5-1 -1. 5 0 1 2 3 4 5 6 7 HIFET Voltage Waveforms* R 2 V out = 4V m 1.5 1 1.5 1 Z opt 0.5 C 3 R 1 3V m 0.5 0 0 1 2 3 4 5 6 7-0.5 0 0 1 2 3 4 5 6 7-0.5-1 C 2 1.5-1.5 1-1 R 1 2V m 0.5 0 0 1 2 3 4 5 6 7-1.5-0.5-1 C 1 1.5 1-1.5 R 1 V m 0.5 0 0 1 2 3 4 5 6 7-0.5-1 V in *Amin K. Ezzeddine and Ho C. Huang, The High-Voltage/High Power FET (HiVP), 2003 IEEE RFIC Symposium Digest, pp. 215-218, June 2. -1.5
I-V of a 3mm x 4 MESFET HIFET 0.8 0V 0.6 Current (A) 0.4 0.2-0.5V -1V -1.5V 0 0 10 20 30 40 Vdd (V) -2V -2.5V Doesn t it look like a GaN HEMT?
MMIC Block Diagram
MMIC Schematic
HIFET MMIC PA Design 1 st stage: 4 x 2mm; 2 nd stage: 2 x (4 x 2mm) Feedback resistors for: gain flatness, good input & output VSWR and stability Input series resistor and inter-stage series resistors for good gain flatness and stability Bias provided thru external chokes Large blocking capacitors for maximum bandwidth P out = (N. V ds ) 2 / 2 * Z out Stability & device thermal considerations
Output Matching Circuit Z opt = N (V ds -V knee ) / I ds We have 2 degrees of freedom: N & I ds (Device size) In this 2-stage MMIC PA: output stage is 2 x (4 x 2mm). Hence V ds = 5V, I ds = 0.36A, V knee = 0.5V Z opt = 4 (5-0.5) / 0.36 = 50 Ω No output matching is needed because the device output impedance is designed to be 50Ω Very small chip size: 2.30 x 2.27 mm
MMIC Process (WIN, PHEMT) 0.5µm gate length (Ti-W), double-recess Epitaxial and thin film Nichrome resistors Silicon Nitride capacitor and passivation I dss ~ 200 250mA/mm 4 mils substrate Via hole for source ground
MMIC Photo
Packaged MMIC & Test Fixture Package size 7 x 7 mm 10mils FR4 substrate
S21, S11 & S22 vs Frequency 30 Gain & Return Losses (db) 20 10 0-10 -20 Output RL Gain Input RL -30 0 1 2 3 4 Frequency (GHz)
Power and Efficiency vs Freq. (20V/ 650mA) 40 P3dB (dbm) & Efficiency (%) 35 30 25 20 P3dB P1dB Efficiency @ 3dB Efficiency @ 1dB 15 0 1 2 3 4 Frequency (GHz)
IP3 vs Frequency 60 50 40 IP3 (dbm) 30 20 10 0 0 1 2 3 4 Frequency (GHz)
Step 2 Broadband Power combiner / Impedance transformer
P α N 2 8-Way Combiner/Divider
2-Way Combiner/Impedance transformer (Back to Back)
Performance of 2 Broadband Baluns Back-to-Back 0 0-5 S21-1 -10-2 Return Loss (db) -15-20 -25-30 -35 S11 S22-3 -4-5 -6-7 Loss (db) -40-8 -45-9 -50 0 500 1000 1500 2000 2500-10 Frequency (MHz)
Schematic of 10W BB PA
Photo of 10W BB PA
Small Signal Gain, Return Loss vs Frequency (24V/2.9A) Gain & Return Losses (db) 35 30 25 20 15 10 5 0-5 -10-15 -20-25 Gain Output RL Input RL 0 1 2 3 4 5 Frequency (GHz)
Output Power, Gain vs Frequency 50 Power (dbm) & Efficiency (%) 40 30 20 10 P1dB Eff. 1dB P3dB Eff. 3dB 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (GHz)
IP3, IP5 versus Frequency IP3 & IP5 (dbm) 80 70 60 50 40 30 20 10 IP3 IP5 0 0 1 2 3 4 Frequency (GHz)
Conclusion We presented the approach to achieving ultra-broadband. High-power PA, as well as the measured state-of-the-art results. The basic approach is to develop a HIFET 50-ohm device (Unit-cell PA), then use push-pull combiner / impedance transformer to power combine the unit-cell PA s. The unit-cell MMIC PA has 3W P1dB from 20 to 3500MHz with 24dB gain and good linearity The power combined PA module has 10W P1dB from 20 to 3500MHz with 23dB gain and good linearity This design concept can be applied to GaN HEMT for very high power, and to CMOS to overcome low-voltage operation
Low Frequency Small Signal 30 Gain Gain & Return Losses (db) 20 10 0-10 -20 Input RL -30 Output RL 0 0.05 0.1 0.15 0.2 Frequency (GHz)