Version 2.0, 3 Jul 2009 F3 PWM conroller Off-Line SMPS Curren Conroller wih inegraed 500V Sarup Cell ( Lached and frequency jier ) Power Managemen Supply Never sop hinking.
F3 PWM conroller Revision Hisory: 2009-7-3 Daashee Previous Version: 0.4 Page Subjecs (major changes since las revision) 5, 7,12, 13, Typo error 6, 14, 16, 17, 21 Revise spike blanking ime o 25us For quesions on echnology, delivery and prices please conac he Infineon Technologies Offices in Germany or he Infineon Technologies Companies and Represenaives worldwide: see our webpage a hp:// www.infineon.com Ediion 2009-7-3 Published by Infineon Technologies AG, 81726 Munich, Germany, 2008 Infineon Technologies AG. All Righs Reserved. Legal disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac your neares Infineon Technologies Office (www.infineon.com). Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac your neares Infineon Technologies Office. Infineon Technologies Componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.
F3 PWM conroller Off-Line SMPS Curren Conroller wih inegraed 500V Sarup Cell ( Lached and frequency jier ) Produc Highlighs Acive Burs o reach he lowes Sandby Power Requiremens < 100mW Buil-in lached Off proecion and exernal lach enable funcion o increase robusness of he sysem Buil-in and exendable blanking Window for high load jumps o increase sysem reliabiliy Frequency jier for low EMI Pb-free lead plaing; RoHS compilan PG-DSO-8 P-DSO-8-3, -6 Feaures 500V Sarup Cell swiched off afer Sar Up Acive Burs for lowes Sandby Power Fas load jump response in Acive Burs 100kHz inernally fixed swiching frequency Buil-in Lached Off Proecion for Overemperaure, Overvolage Shor Winding Auo Resar Proecion for Overload, Open Loop,VCC Undervolage Shor Opocoupler Buil-in Sof Sar Buil-in blanking window wih exendable blanking ime for shor duraion high curren Exernal lach off enable funcion Max Duy Cycle 75% Overall olerance of Curren Limiing < ±5% Inernal PWM Leading Edge BiCMOS echnology provide wide VCC range Frequency jier and sof gae driving for low EMI Descripion The is he laes version of he F3 conroller for lowes sandby power and low EMI feaures wih boh auo-resar and lach off proecion feaures o enhance he sysem robusness. I arges for off-line baery adapers, and low cos SMPS for low o medium power range such as applicaion for he DVD R/W, DVD Combi, Blue Ray DVD player and recorder, se op box, charger, noe book adaper, ec. The inheried ousanding feaures includes 500V sarup cell, acive burs mode (achieve he lowes sandby power; i.e. <100mV a no load wih Vin=265Vac) and propagaion delay compensaion (accurae oupu power limi for wide range inpu), modulaed gae drive (low EMI), ec. The newly added echnology and feaures can furher enhance he feaures. I includes BiCMOS echnology (furher lower power consumpion and exend Vcc operaing range o 25V), frequency jiering feaure (low EMI), buil-in sof sar, buil-in blanking window wih exendable blanking ime for high load jump, exernal lach off enable pin (feasible for exra proecion), ec. Therefore, is a versaile PWM conroller for low o medium power applicaion. Typical Applicaion + 85 -- 265 VAC C Bulk Snubber Converer DC Oupu - C VCC HV VCC Sarup Cell PWM Conroller Curren Precise Low Tolerance Peak Curren Limiaion Gae Power Managemen Conrol Uni Acive Burs M ode Lach off CS FB R Sense BL Auo Resar M ode GND ICE3AS03LJ ( Lach Jier ) Type Marking Package F OSC 3AS3LJ PG-DSO-8 100kHz Version 2.0 3 3 Jul 2009
F3 PWM conroller Table of Conens Page 1 Pin Configuraion and Funcionaliy.............................5 1.1 Pin Configuraion wih PG-DSO-8.................................5 1.2 Pin Funcionaliy..............................................5 2 Represenaive Blockdiagram..................................6 3 Funcional Descripion........................................7 3.1 Inroducion..................................................7 3.2 Power Managemen............................................7 3.3 Improved Curren.........................................8 3.3.1 PWM-OP..................................................9 3.3.2 PWM-Comparaor...........................................9 3.4 Sarup Phase...............................................10 3.5 PWM Secion................................................11 3.5.1 Oscillaor.................................................11 3.5.2 PWM-Lach FF.............................................12 3.5.3 Gae Driver...............................................12 3.6 Curren Limiing..............................................12 3.6.1 Leading Edge......................................13 3.6.2 Propagaion Delay Compensaion..............................13 3.7 Conrol Uni.................................................14 3.7.1 Basic and Exendable...........................14 3.7.2 Acive Burs..........................................14 3.7.2.1 Enering Acive Burs.................................15 3.7.2.2 Working in Acive Burs...............................15 3.7.2.3 Leaving Acive Burs.................................15 3.7.3 Proecion s...........................................16 3.7.3.1 Lached Off........................................16 3.7.3.2 Auo Resar........................................17 4 Elecrical Characerisics.....................................18 4.1 Absolue Maximum Raings.....................................18 4.2 Operaing Range.............................................18 4.3 Characerisics...............................................19 4.3.1 Supply Secion.............................................19 4.3.2 Inernal Volage Reference...................................19 4.3.3 PWM Secion..............................................20 4.3.4 Sof Sar ime.............................................20 4.3.5 Conrol Uni...............................................21 4.3.6 Curren Limiing............................................22 4.3.7 Driver Secion.............................................22 5 Ouline Dimension...........................................23 6 Marking....................................................24 Version 2.0 4 3 Jul 2009
1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion wih PG-DSO-8 Pin Symbol Funcion 1 BL exended and Lach off enable 2 FB Feedback 3 CS Curren Sense 4 Gae Gae driver oupu 5 HV High Volage inpu 6 n.c. No Conneced 7 VCC Conroller Supply Volage 8 GND Conroller Ground F3 PWM conroller Pin Configuraion and Funcionaliy 1.2 Pin Funcionaliy BL (exended and Lach off enable) The BL pin combines he funcions of exendable blanking ime for enering he Auo Resar Proecion and he exernal lach off enable. The exendable blanking ime funcion is o exend he buil-in 20ms blanking ime by adding an exernal capacior a BL o ground. The exernal lach off enable funcion is an exernal access o lach off he IC. I is riggered by pulling down he BL pin o less han 0.33V. FB (Feedback) The informaion abou he regulaion is provided by he FB Pin o he inernal Proecion Uni and o he inernal PWM-Comparaor o conrol he duy cycle. The FBsignal is he only conrol in case of ligh load a he Acive Burs. BL Package PG-DSO-8 1 8 GND CS (Curren Sense) The Curren Sense pin senses he volage developed on he series resisor insered in he source of he Power MOSFET. If CS reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is immediaely swiched off. Furhermore, his curren informaion can be used o realize he Curren operaion hrough he PWM-Comparaor where i compares wih FB signal. FB 2 7 VCC Gae The Gae pin is he oupu of he inernal driver sage conneced o he Gae of an exernal power MOSFET. CS Gae 3 4 6 5 N.C. HV HV (High Volage) The high volage Pin is conneced o he recified DC inpu volage. I is he inpu for he inegraed 500V Sarup cell. Figure 1 Pin Configuraion PG-DSO-8(op view) VCC (Power supply) The VCC pin is he posiive supply of he IC. The operaing range is beween 10.5V and 25V. GND (Ground) The GND pin is he ground of he conroller. Version 2.0 5 3 Jul 2009
F3 PWM conroller Represenaive Blockdiagram 2 Represenaive Blockdiagram 85... 270 VAC Lach off Enable Signal #1 BL CBK #2 TAE FB CBulk 3.25kΩ IBK T2 T1 5.0V T3 0.6V 2 ms couner Power Managemen Inernal Bias Volage Reference Lached off Rese VVCC < 6.23V Power-Down Rese 5.0V Undervolage Lockou 18V 10.5V HV 0.9V S1 5.0V RFB 25kΩ 2pF Conrol Uni 0.33V VCC 25.5V 4.0V 4.2V 1.23V 3.5V 3.0V C9 C2 C3 C4 C5 C6a C6b 120us Time 1 G2 20ms Time Spike 25us G5 20ms Time Auo Resar ICE3AS03LJ-F3 PWM conroller ( Lach and Jier ) 1 Thermal Shudown Tj >130 C G3 Lach off Spike 25us G6 Sof Sar Block Sof Sar Acive Burs 0.67V G11 C7 PWM OP Curren Sof-Sar Comparaor PWM Comparaor C8 x3.3 G7 # : opional exernal componens; #1 : CBK is used o exend he Time #2 : TAE is used o enable he exernal Lach off feaure Sarup Cell 0.75 Oscillaor Duy Cycle max Clock Freq. jier 1 G8 Spike 190ns C11 Propagaion-Delay Compensaion C10 Vcsh G10 C12 0.25V CVCC VCC PWM Secion FF1 S R Q Gae Driver G9 1.66V Leading Edge 220ns 1pF 10kΩ D1 Curren Limiing Snubber GND Gae CS RSense + Converer DC Oupu VOUT - Figure 2 Represenaive Blockdiagram Version 2.0 6 3 Jul 2009
F3 PWM conroller Funcional Descripion 3 Funcional Descripion All values which are used in he funcional descripion are ypical values. For calculaing he wors cases he min/max values which can be found in secion 4 Elecrical Characerisics have o be considered. 3.1 Inroducion is an enhanced version of he F3 PWM conroller (ICE3xS02) for he low o medium power applicaion. The paricular enhanced feaures are he buil-in feaures for sof sar, blanking window and frequency jier. I also provides he flexibiliy o increase he blanking window by simply adding capacior in BL pin. To increase he robusness and flexibiliy of he proecion feaure, an exernal lach-off enable feaure is added. Moreover, he proven ousanding feaures in F3 PWM conroller are sill remained such as he acive burs mode, propagaion delay compensaion, modulaed gae drive, proecion for Vcc overvolage, over emperaure, shor winding, shor diode, over load, open loop, Vcc undervolage and shor opocoupler. The inelligen Acive Burs a Sandby can effecive obain he lowes Sandby Power a minimum load and no load condiions. Afer enering his burs mode, here is sill a full conrol of he power conversion by he secondary side via he same opocoupler ha is used for he normal PWM conrol. The response on load jumps is opimized. The volage ripple on V ou is minimized. V ou is on well conrolled in his mode. The usual exernally conneced RC-filer in he feedback line afer he opocoupler is inegraed in he IC o reduce he exernal par coun. Furhermore, a high volage Sarup Cell is inegraed ino he IC which is swiched off once he Undervolage Lockou on-hreshold of 18V is exceeded. The exernal sarup resisor is no longer necessary as his Sarup Cell can direcly conneced o he inpu bulk capacior. Power losses are herefore reduced. This increases he efficiency under ligh load condiions drasically. Adoping he BiCMOS echnology, i can furher decrease he power consumpion and provide a even beer sandby inpu power. Besides, i also increases he design flexibiliy as he Vcc volage range is exended o 25V. The buil-in sof sar ime a 10ms can provide sufficien iming o reduce he over-sress a power MOSFET and he oupu recifier during sarup. There are 2 modes of blanking ime for high load jumps; he basic mode and he exendable mode. The blanking ime for he basic mode is se a 20ms while he exendable mode will increase he blanking ime a basic mode by adding exernal capacior a he BL pin. During his ime window he overload deecion is disabled. Wih his concep no furher exernal componens are necessary o adjus he blanking window. In order o increase he robusness and safey of he sysem, he IC provides 2 levels of proecion modes: Lached Off and Auo Resar. The Lached Off is only enered under dangerous condiions which can damage he SMPS if no swiched off immediaely. A resar of he sysem can only be done by recycling he AC line. In addiion, for his enhanced version, here is an exernal Lach Enable funcion provided o increase he flexibiliy in proecion. When he BL pin is pulled down o less han 0.33V, he Lach Off is riggered. The Auo Resar reduces he average power conversion o a minimum under unsafe operaing condiions. This is necessary for a prolonged faul condiion which could oherwise lead o a desrucion of he SMPS over ime. Once he malfuncion is removed, normal operaion is auomaically reained afer he nex Sar Up Phase. The inernal precise peak curren conrol reduces he coss for he ransformer and he secondary diode. The influence of he change in he inpu volage on he maximum power limiaion can be avoided ogeher wih he inegraed Propagaion Delay Compensaion. Therefore he maximum power is nearly independen on he inpu volage, which is required for wide range SMPS. Thus here is no need for he over-sizing of he SMPS, e.g. he ransformer and he oupu diode. Furhermore, his enhanced version implemens he frequency jier mode o he swiching clock and modulaed gae drive signal a he Gae pin such ha he EMI noise will be effecively reduced. 3.2 Power Managemen The Undervolage Lockou moniors he exernal supply volage V VCC. When he SMPS is plugged o he main line, he inernal Sarup Cell is biased and sars o charge he exernal capacior C VCC which is conneced o he VCC pin. This VCC charge curren is conrolled o 0.9mA by he Sarup Cell. When he V VCC exceeds he on-hreshold V CCon =18V, he bias circui are swiched on. Then he Sarup Cell is swiched off by he Undervolage Lockou and herefore no power losses presen due o he connecion of he Sarup Cell o he Drain volage. To avoid unconrolled ringing a swich-on a hyseresis sar up volage is implemened. The swich-off of he conroller can only ake place afer Acive was enered and V VCC falls below 10.5V. The maximum curren consumpion before he conroller is acivaed is abou 250µA. When V VCC falls below he off-hreshold V CCoff =10.5V, he bias circui swiched off and he sof sar couner is Version 2.0 7 3 Jul 2009
F3 PWM conroller Funcional Descripion rese. Thus i is ensured ha a every sarup cycle he sof sar sars a zero. 3.3 Improved Curren Sof-Sar Comparaor HV VCC Sarup Cell FB C8 PWM-Lach R Q Driver S Q Power Managemen Inernal Bias Lached Off Rese V VCC < 6.23V Power-Down Rese Undervolage Lockou 18V 10.5V Volage Reference Auo Resar 5.0V 0.67V PWM OP x3.3 Improved Curren CS Sof Sar block Acive Burs Lached Off Figure 4 Curren Curren means he duy cycle is conrolled by he slope of he primary curren. This is done by comparing he FB signal wih he amplified curren sense signal. Figure 3 Power Managemen The inernal bias circui is swiched off if Lached Off or Auo Resar is enered. The curren consumpion is hen reduced o 250µA. Once he malfuncion condiion is removed, his block will hen urn back on. The recovery from Auo Resar does no require re-cycling he AC line. In case Lached Off is enered, VCC needs o be dropped below 6.23V o rese he Lached Off. This is done usually by re-cycling he AC line. When Acive Burs is enered, he inernal Bias is swiched off mos of he ime bu he Volage Reference is kep alive in order o reduce he curren consumpion below 450µA. Amplified Curren Signal FB 0.67V Driver on Figure 5 Pulse Widh Modulaion In case he amplified curren sense signal exceeds he FB signal, he on-ime on of he driver is finished by reseing he PWM-Lach (see Figure 5). The primary curren is sensed by he exernal series resisor R Sense insered in he source of he exernal power MOSFET. By means of Curren regulaion, he secondary oupu volage is insensiive Version 2.0 8 3 Jul 2009
F3 PWM conroller Funcional Descripion o he line variaions. The curren waveform slope will change wih he line variaion, which conrols he duy cycle. The exernal R Sense allows an individual adjusmen of he maximum source curren of he exernal power MOSFET. To improve he Curren during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T2, he volage source V1 and a resisor R1 (see Figure 6). Every ime he oscillaor shus down for maximum duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he Gae Driver, T2 is opened so ha he volage ramp can sar. In case of ligh load he amplified curren ramp is oo small o ensure a sable regulaion. In ha case he Volage Ramp is a well defined signal for he comparison wih he FB-signal. The duy cycle is hen conrolled by he slope of he Volage Ramp. By means of he ime delay circui which is riggered by he invered V OSC signal, he Gae Driver is swiched-off unil i reaches approximaely 156ns delay ime (see Figure 7). I allows he duy cycle o be reduced coninuously ill 0% by decreasing V FB below ha hreshold. FB Figure 6 Sof-Sar Comparaor Oscillaor V OSC T 2 R 1 C 1 Volage Ramp PWM Comparaor C8 ime delay circui (156ns) 0.67V 10kΩ V 1 Improved Curren PWM-Lach Gae Driver X3.3 PWM OP Figure 7 V OSC Volage Ramp 0.67V FB Gae Driver 3.3.1 PWM-OP max. Duy Cycle 156ns ime delay Ligh Load Condiions The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor R Sense conneced o pin CS. R Sense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.3 by PWM OP. The oupu of he PWM-OP is conneced o he volage source V 1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM- Comparaor C8 and he Sof-Sar-Comparaor (see Figure 6). 3.3.2 PWM-Comparaor The PWM-Comparaor compares he sensed curren signal of he exernal power MOSFET wih he feedback signal V FB (see Figure 8). V FB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pull-up resisor R FB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he exernal power MOSFET exceeds he signal V FB he PWM- Comparaor swiches off he Gae Driver. Version 2.0 9 3 Jul 2009
F3 PWM conroller Funcional Descripion R FB 5V Sof-Sar Comparaor is a buil-in funcion and i is conrolled by an inernal couner. FB C8 PWM-Lach PWM Comparaor Opocoupler 0.67V PWM OP X3.3 CS V SofS V SofS2 V SofS1 Improved Curren Figure 8 PWM Conrolling 3.4 Sarup Phase Sof Sar couner Figure 10 Sof Sar Phase When he V VCC exceeds he on-hreshold volage, he IC sars he Sof Sar mode (see Figure 10). The funcion is realized by an inernal Sof Sar resisor, an curren sink and a couner. And he ampliude of he curren sink is conrolled by he couner (see Figure 11). 5V Sof Sar finish SofS C7 Sof Sar Sof Sar Sof-Sar Comparaor Gae Driver SofS R SofS G7 Sof Sar Couner 32I 8I 4I 2I I 0.67V PWM OP x3.3 Figure 9 Sof Sar In he Sarup Phase, he IC provides a Sof Sar period o conrol he maximum primary curren by means of a duy cycle limiaion. The Sof Sar funcion CS Figure 11 Sof Sar Circui Afer he IC is swiched on, he V SFOFTS volage is conrolled such ha he volage is increased sepwisely (32 seps) wih he increase of he couns. The Sof Sar couner would send a signal o he curren sink conrol in every 300us such ha he curren sink Version 2.0 10 3 Jul 2009
F3 PWM conroller Funcional Descripion decrease gradually and he duy raio of he gae drive increases gradually. The Sof Sar will be finished in 10ms ( Sof-Sar ) afer he IC is swiched on. A he end of he Sof Sar period, he curren sink is swiched off. V SOFTS32 V SofS Sof-Sar In addiion o Sar-Up, Sof-Sar is also acivaed a each resar aemp during Auo Resar. The Sar-Up ime Sar-Up before he converer oupu volage V OUT is seled, mus be shorer han he Sof- Sar Phase Sof-Sar (see Figure 13). By means of Sof-Sar here is an effecive minimizaion of curren and volage sresses on he exernal power MOSFET, he clamp circui and he oupu overshoo and i helps o preven sauraion of he ransformer during Sar-Up. 3.5 PWM Secion Gae Driver Oscillaor Duy Cycle max 0.75 PWM Secion Clock Frequency Jier Figure 12 Gae drive signal under Sof-Sar Phase Wihin he sof sar period, he duy cycle is increasing from zero o maximum gradually (see Figure 12). V SOFTS32 V SofS Sof-Sar Sof Sar Block Sof Sar Comparaor PWM Comparaor Curren Limiing 1 G8 FF1 S R Q Gae Driver G9 4.2V V FB V OUT V OUT Sar-Up Figure 13 Sar Up Phase Figure 14 PWM Secion Block Gae 3.5.1 Oscillaor The oscillaor generaes a fixed frequency of 100kHz wih frequency jiering of ±4% (which is ±4kHz) a a jiering period of 4ms. A capacior, a curren source and a curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed, in order o achieve a very accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max =0.75. Once he Sof Sar period is over and when he IC goes ino normal operaing mode, he swiching frequency of he clock is varied by he conrol signal from he Sof Version 2.0 11 3 Jul 2009
F3 PWM conroller Funcional Descripion Sar block. Then he swiching frequency is varied in range of 100kHz ± 4kHz a period of 4ms. 3.5.2 PWM-Lach FF The oupu of he oscillaor block provides coninuous pulse o he PWM-Lach which urns on/off he exernal power MOSFET. Afer he PWM-Lach is se, i is rese by he PWM comparaor, he Sof Sar comparaor or he Curren -Limi comparaor. When i is in rese mode, he oupu of he gae driver is shu down immediaely. Thus he leading swich on spike is minimized. Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. During power up, when VCC is below he undervolage lockou hreshold V VCCoff, he oupu of he Gae Driver is se o low in order o disable power ransfer o he secondary side. 3.6 Curren Limiing 3.5.3 Gae Driver VCC PWM-Lach PWM Lach FF1 Lached Off Spike 190ns Curren Limiing 1.66V C11 1 Propagaion-Delay Compensaion OPP Gae Gae Driver PWM-OP G10 C10 C12 V csh 0.25V Leading Edge 220ns Figure 15 Gae Driver The driver-sage is opimized o minimize EMI and o provide high circui efficiency. This is done by reducing he swich on slope when exceeding he exernal power MOSFET hreshold. This is achieved by a slope conrol of he rising edge a he gae driver s oupu (see Figure 16). 5V Figure 16 Gae Rising Slope ca. = 130ns Acive Burs CS 10k D1 1pF Figure 17 Curren Limiing Block There is a cycle by cycle peak curren limiing operaion realized by he Curren-Limi comparaor C10. The source curren of he exernal power MOSFET is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense which is fed ino he pin CS. If he volage V Sense exceeds he inernal hreshold volage V csh, he comparaor C10 immediaely urns off he gae drive by reseing he PWM Lach FF1. A Propagaion Delay Compensaion is added o suppor he immediae shu down of he exernal power MOSFET wih very shor propagaion delay. Thus he influence of he AC inpu volage on he maximum oupu power can be reduced o minimal. In order o preven he curren limi from disorions caused by leading edge spikes, a Leading Edge Version 2.0 12 3 Jul 2009
F3 PWM conroller Funcional Descripion is inegraed in he curren sense pah for he comparaors C10, C12 and he PWM-OP. The oupu of comparaor C12 is acivaed by he AND Gae G10 if Acive Burs is enered. When i is acivaed, he curren limiing is reduced o 0.25V. This volage level deermines he maximum power level in Acive Burs. Furhermore, he comparaor C11 is implemened o deec dangerous curren levels which could occur if here is a shor winding in he ransformer or he secondary diode is shoren. To ensure ha here is no accidenally enering of he Lached by he comparaor C11, a 190ns spike blanking ime is inegraed in he oupu pah of comparaor C11. 3.6.1 Leading Edge V csh V Sense LEB = 220ns induced o he delay, which depends on he raio of di/ d of he peak curren (see Figure 19). The overshoo of Signal2 is larger han of Signal1 due o he seeper rising waveform. This change in he slope is depending on he AC inpu volage. Propagaion Delay Compensaion is inegraed o reduce he overshoo due o di/d of he rising primary curren. Thus he propagaion delay ime beween exceeding he curren sense hreshold V csh and he swiching off of he exernal power MOSFET is compensaed over emperaure wihin a wide range. Curren Limiing is hen very accurae. For example, I peak = 0.5A wih R Sense = 2. The curren sense hreshold is se o a saic volage level V csh =1V wihou Propagaion Delay Compensaion. A curren ramp of di/d = 0.4A/µs, or dv Sense /d = 0.8V/µs, and a propagaion delay ime of Propagaion Delay =180ns leads o an I peak overshoo of 14.4%. Wih he propagaion delay compensaion, he overshoo is only around 2% (see Figure 20). Figure 18 Leading Edge Whenever he power MOSFET is swiched on, a leading edge spike is generaed due o he primaryside capaciances and reverse recovery ime of he secondary-side recifier. This spike can cause he gae drive o swich off uninenionally. In order o avoid a premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220ns. 3.6.2 Propagaion Delay Compensaion V Sense V 1,3 1,25 1,2 1,15 1,1 1,05 1 0,95 Figure 20 wih compensaion 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 dv Sense d Overcurren Shudown wihou compensaion V µ s Signal2 Signal1 V OSC max. Duy Cycle I Sense Propagaion Delay I peak2 I peak1 I Overshoo2 off ime I Limi V Sense Propagaion Delay I Overshoo1 V csh Figure 19 Curren Limiing In case of overcurren deecion, here is always propagaion delay o swich off he exernal power MOSFET. An overshoo of he peak curren I peak is Figure 21 Signal1 Signal2 Dynamic Volage Threshold V csh Version 2.0 13 3 Jul 2009
F3 PWM conroller Funcional Descripion The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (see Figure 21). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. 3.7 Conrol Uni The Conrol Uni conains he funcions for Acive Burs, Auo Resar and Lached Off. The Acive Burs and he Auo Resar boh have 20ms inernal Time. For he Auo Resar, a furher exendable Time is achieved by adding exernal capacior a BL pin. By means of his Time, he IC avoids enering ino hese wo modes accidenally. Furhermore hose buffer ime for he overload deecion is very useful for he applicaion ha works in low curren bu requires a shor duraion of high curren occasionally. 3.7.1 Basic and Exendable BL # C BK I BK S1 0.9V 1 G2 5.0V Sof Sar block blanking ime is passed, he swich S1 is opened by G2. Then he 0.9V clamped volage a BL pin is charged o 4.0V hrough he inernal I BK consan curren. Then G5 is enabled by comparaor C3. Afer he 25us spike blanking ime, he Auo Resar is acivaed. For example, if C BK = 0.22µF, I BK = 13µA ime = 20ms + C BK x (4.0-0.9) / I BK = 72ms The 20ms blanking ime circui afer C4 is disabled by he sof sar block before sar up and he maximum C BK capacior is resriced o use less han 1.3µF such ha he conroller can sar up properly. The Acive Burs has basic blanking mode only while he Auo Resar has boh he basic and he exendable blanking mode. 3.7.2 Acive Burs The IC eners Acive Burs under low load condiions. Wih he Acive Burs, he efficiency increases significanly a ligh load condiions while sill mainaining a low ripple on V OUT and a fas response on load jumps. During Acive Burs, he IC is conrolled by he FB signal. Since he IC is always acive, i can be a very fas response o he quick change a he FB signal. The Sar up Cell is kep OFF in order o minimize he power loss. Inernal Bias 4.0V C3 Spike 25us 20 ms Time Curren Limiing G10 FB 4.2V 1.23V C4 C5 20ms Time 20ms Time Figure 22 Basic and Exendable There are 2 kinds of mode; basic mode and he exendable mode. The basic mode has an inernal pre-se 20ms blanking ime while he exendable mode has exended blanking ime o basic mode by connecing an exernal capacior o he BL pin. For he exendable mode, he gae G5 is blocked even hough he 20ms blanking ime is reached if an exernal capacior C BK is added o BL pin. While he 20ms G5 G6 Auo Resar Conrol Uni Acive Burs FB Figure 23 4.2V 1.23V 3.5V 3.0V C4 C5 C6a C6b Acive Burs G6 Conrol Uni G11 Acive Burs The Acive Burs is locaed in he Conrol Uni. Figure 23 shows he relaed componens. Version 2.0 14 3 Jul 2009
F3 PWM conroller Funcional Descripion 3.7.2.1 Enering Acive Burs The FB signal is kep monioring by he comparaor C4. During normal operaion, he inernal blanking ime couner is rese o 0. When FB signal falls below 1.23V, i sars o coun. When he couner reach 20ms and FB signal is sill below 1.23V, he sysem eners he Acive Burs. This ime window prevens a sudden enering ino he Acive Burs due o large load jumps. Afer enering Acive Burs, a burs flag is se and he inernal bias is swiched off in order o reduce he curren consumpion of he IC o approx. 450µA. I needs he applicaion o enforce he VCC volage above he Undervolage Lockou level of 10.5V such ha he Sarup Cell will no be swiched on accidenally. Or oherwise he power loss will increase drasically. The minimum VCC level during Acive Burs depends on he load condiion and he applicaion. The lowes VCC level is reached a no load condiion. V FB 4.2V 3.5V 3.0V 1.23V Timer V CS Enering Acive Burs 20ms Time Leaving Acive Burs 3.7.2.2 Working in Acive Burs Afer enering he Acive Burs, he FB volage rises as V OUT sars o decrease, which is due o he inacive PWM secion. The comparaor C6a moniors he FB signal. If he volage level is larger han 3.5V, he inernal circui will be acivaed; he Inernal Bias circui resumes and sars o provide swiching pulse. In Acive Burs he gae G10 is released and he curren limi is reduced o 0.25V. In one hand, i can reduce he conducion loss and he oher hand, i can reduce he audible noise. If he load a V OUT is sill kep unchanged, he FB signal will drop o 3.0V. A his level he C6b deacivaes he inernal circui again by swiching off he inernal Bias. The gae G11 is acive again as he burs flag is se afer enering Acive Burs. In Acive Burs, he FB volage is changing like a saw ooh beween 3.0V and 3.5V (see Figure 24). 1.06V 0.25V V VCC 10.5V I VCC 2.5mA Curren limi level during Acive Burs 3.7.2.3 Leaving Acive Burs The FB volage will increase immediaely if here is a high load jump. This is observed by he comparaor C4. As he curren limi is app. 25% during Acive Burs, a cerain load jump is needed so ha he FB signal can exceed 4.2V. A ha ime he comparaor C4 reses he Acive Burs conrol which in urn blocks he comparaor C12 by he gae G10. The maximum curren can hen be resumed o sabilize V OUT. 450uA V OUT Figure 24 Signals in Acive Burs Version 2.0 15 3 Jul 2009
F3 PWM conroller Funcional Descripion 3.7.3 Proecion s The IC provides several proecion feaures which are separaed ino wo caegories. Some ener Lached Off and he ohers ener Auo Resar. Besides he pre-defined proecion feaure for he Lach off mode, here is also an exernal Lach off Enable pin for cusomer defined Lach off proecion feaures. The Lached Off can only be rese if VCC falls below 6.23V. Boh modes preven he SMPS from desrucive saes.the following able shows he relaionship beween possible sysem failures and he chosen proecion modes. VCC Overvolage Overemperaure Shor Winding/Shor Diode Exernal Proecion Enable Overload Open Loop VCC Undervolage Shor Opocoupler Lached Off Lached Off Lached Off Lached Off Auo Resar Auo Resar Auo Resar Auo Resar The VCC volage is observed by comparaor C2. If he VCC volage is > 25.5V and las for 120µs, he overvolage deecion is acivaed. I eners he lach off mode.this proecion mode is acivaed in boh normal operaing mode and burs mode. The inernal Volage Reference is swiched off mos of he ime once Lached Off is enered in order o minimize he curren consumpion of he IC. This Lached Off can only be rese if he V VCC < 6.23V. In his mode, only he UVLO is working which conrols he Sarup Cell by swiching on/off a V VCCon /V VCCoff. During his phase, he average curren consumpion is only 250µA. As here is no longer a self-supply by he auxiliary winding, he VCC drops. The Undervolage Lockou swiches on he inegraed Sarup Cell when VCC falls below 10.5V. The Sarup Cell is swiched off again when VCC has exceeded 18V. Once he Lached Off was enered, here is no Sar Up Phase whenever he VCC exceeds he swich-on level of he Undervolage Lockou. Therefore he VCC volage changes beween he swich-on and swich-off levels of he Undervolage Lockou wih a saw ooh shape (see Figure 26). V VCC 3.7.3.1 Lached Off CS 1.66V C11 Spike 190ns Lached Off Rese V VCC < 6.23V 18V 10.5V T LE BL # Lach Enable signal Figure 25 0.33V VCC 25.5V UVLO 2ms couner C9 C2 25us Time 120us Time Lached Off 1 G3 G1 Thermal Shudown T j >130 C Conrol Uni Spike 25us Lached Off Volage Reference I VCCSar 0.9mA Figure 26 Signals in Lached Off The Thermal Shudown block moniors he juncion emperaure of he IC. Afer deecing a juncion emperaure higher han lached hermal shudown emperaure; T jsd, he Lached Off is enered. The signals coming from he emperaure deecion and VCC overvolage deecion are fed ino a spike blanking wih a ime consan of 25µs in order o ensure he sysem reliabiliy. Furhermore, a shor winding or shor diode on he secondary side can be deeced by he comparaor C11 which is in parallel o he propagaion delay compensaed curren limi comparaor C10. In normal Version 2.0 16 3 Jul 2009
F3 PWM conroller Funcional Descripion operaing mode, comparaor C10 conrols he maximum level of he CS signal a 1.06V. If here is a failure such as shor winding or shor diode, C10 is no longer able o limi he CS signal a 1.06V. Insead he comparaor C11 deecs he peak curren volage > 1.66V and las for 190ns, i eners he Lached Off immediaely in order o keep he SMPS in a safe sage. In case he pre-defined Lach Off feaures are no sufficien, here is a cusomer defined exernal Lach Enable feaure. The Lach Off can be riggered by pulling down he BL pin o < 0.33V. I can simply add a rigger signal o he base of he exernally added ransisor, T LE a he BL pin. To ensure his lach funcion will no be mis-riggered during sar up, a 2ms delay ime is implemened o blank he unsable signal. 3.7.3.2 Auo Resar and I BK is 13uA, he exendable blanking ime is around 52ms and he oal blanking ime is 72ms. In combining he FB and blanking ime, here is a blanking window generaed which prevens he sysem o ener Auo Resar due o large load jumps. In case of VCC undervolage, he IC eners ino he Auo Resar and sars a new sarup cycle. Shor Opocoupler also leads o VCC undervolage as here is no self supply afer acivaing he inernal reference and bias. In conras o he Lached Off, here is always a Sarup Phase wih swiching cycles in Auo Resar. Afer his Sar Up Phase, he condiions are again checked wheher he failure mode is sill presen. Normal operaion is resumed once he failure mode is removed ha had caused he Auo Resar. BL # C BK I BK 5.0V S1 0.9V 1 G2 4.0V C3 Spike 25us 4.2V FB C4 20ms Time G5 Auo Resar Conrol Uni Figure 27 Auo Resar In case of Overload or Open Loop, he FB exceeds 4.2V which will be observed by comparaor C4. Then he inernal blanking couner sars o coun. When i reaches 20ms, he swich S1 is released. Then he clamped volage 0.9V a V BL can increase. When here is no exernal capacior C BK conneced, he V BL will reach 4.0V immediaely. When boh he inpu signals a AND gae G5 is posiive, he Auo-Resar will be acivaed afer he exra spike blanking ime of 25us is elapsed. However, when an exra blanking ime is needed, i can be achieved by adding an exernal capacior, C BK. A consan curren source of I BK will sar o charge he capacior C BK from 0.9V o 4.0V afer he swich S1 is released. The charging ime from 0.9V o 4.0V are he exendable blanking ime. If C BK is 0.22µF Version 2.0 17 3 Jul 2009
F3 PWM conroller Elecrical Characerisics 4 Elecrical Characerisics Noe: All volages are measured wih respec o ground (Pin 8). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 7 (VCC) is discharged before assembling he applicaion circui. T a =25 C unless oherwise specified. Parameer Symbol Limi Values Uni Remarks min. max. HV Volage V HV - 500 V VCC Supply Volage V VCC -0.3 27 V FB Volage V FB -0.3 5.5 V BL Volage V BL -0.3 5.5 V CS Volage V CS -0.3 5.5 V Juncion Temperaure T j -40 150 C Sorage Temperaure T S -55 150 C Thermal Resisance Juncion -Ambien R hja - 185 K/W Soldering emperaure,wave soldering only allowed a leads T sold - 260 C 1.6mm(0.063 in.) from case for 10s ESD Capabiliy (incl. Drain Pin) V ESD - 2 kv Human body model 1) 1) According o EIA/JESD22-A114-B (discharging a 100pF capacior hrough a 1.5kΩ series resisor) 4.2 Operaing Range Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. max. VCC Supply Volage V VCC V VCCoff 25 V Max. value limied due o VCC OVP Juncion Temperaure of Conroller T jcon -25 130 C Max value limied due o hermal shu down of conroller Version 2.0 18 3 Jul 2009
F3 PWM conroller Elecrical Characerisics 4.3 Characerisics 4.3.1 Supply Secion Noe: The elecrical characerisics involve he spread of values wihin he specified supply volage and juncion emperaure range T J from 25 C o 125 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 18 V is assumed. Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCCsar - 150 250 µa V VCC =16.5V VCC Charge Curren I VCCcharge1 - - 5.0 ma V VCC = 0V I VCCcharge2 0.55 0.90 1.60 ma V VCC = 1V I VCCcharge3-0.7 - ma V VCC =16.5V Leakage Curren of Sar Up Cell Supply Curren wih Inacive Gae I SarLeak - 0.2 50 µa V HV = 450V, V VCC =18V I VCCsup1-1.5 2.5 ma Supply Curren wih Acive Gae I VCCsup2-2.5 4.2 ma I FB = 0A, C Load =680pF Supply Curren in Lached Off Supply Curren in Auo Resar wih Inacive Gae Supply Curren in Acive Burs wih Inacive Gae I VCClach - 250 - µa I FB = 0A I VCCresar - 250 - µa I FB = 0A I VCCburs1-450 950 µa V FB = 2.5V I VCCburs2-450 950 µa V VCC = 11.5V,V FB = 2.5V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hyseresis V VCCon V VCCoff V VCChys 17.0 9.8-18.0 10.5 7.5 19.0 11.2 - V V V 4.3.2 Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF 4.90 5.00 5.10 V measured a pin FB I FB = 0 Version 2.0 19 3 Jul 2009
F3 PWM conroller Elecrical Characerisics 4.3.3 PWM Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Oscillaor Frequency f OSC1 87 100 113 khz f OSC2 92 100 108 khz T j = 25 C Frequency Jiering Range f jier - ±4 - khz T j = 25 C Max. Duy Cycle D max 0.70 0.75 0.80 Min. Duy Cycle D min 0 - - V FB < 0.3V PWM-OP Gain A V 3.1 3.3 3.5 Volage Ramp Offse V Offse-Ramp - 0.67 - V V FB Operaing Range Min Level V FBmin - 0.5 - V V FB Operaing Range Max level V FBmax - - 4.3 V CS=1V, limied by Comparaor C4 1) FB Pull-Up Resisor R FB 9 15.4 22 kω 1) The parameer is no subjeced o producion es - verified by design/characerizaion 4.3.4 Sof Sar ime Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sof Sar ime SS - 10 - ms Version 2.0 20 3 Jul 2009
F3 PWM conroller Elecrical Characerisics 4.3.5 Conrol Uni Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Clamped V BL volage during V BLclmp 0.85 0.90 0.95 V V FB = 4V Normal Operaing ime volage limi for V BKC3 3.85 4.00 4.15 V Comparaor C3 Over Load Open Loop Deecion V FBC4 4.05 4.20 4.35 V Limi for Comparaor C4 Acive Burs Level for Comparaor C5 V FBC5 1.12 1.23 1.34 V Acive Burs Level for Comparaor C6a Acive Burs Level for Comparaor C6b V FBC6a 3.35 3.50 3.65 V Afer Acive Burs is enered V FBC6b 2.88 3.00 3.12 V Afer Acive Burs is enered Overvolage Deecion Limi V VCCOVP 25 25.5 26.5 V Lach Enable level a BL pin V LE 0.25 0.33 0.4 V > 25µs Charging curren a BL pin I BK 9.1 13.0 16.9 µa Charge sars afer he buil-in 20ms blanking ime elapsed Lached Thermal Shudown 1) T jsd 130 140 150 C Buil-in Time for Overload Proecion or ener Acive Burs Inhibi Time for Lach Enable funcion during Sar up Spike Time before Lach off or Auo Resar Proecion Power Down Rese for Lached BK - 20 - ms wihou exernal capacior a BL pin IHLE - 2.0 - ms Afer IC urns on Spike - 25 - µs V VCCPD 5.2 6.23 7.8 V Afer Lached Off is enered 1) The parameer is no subjeced o producion es - verified by design/characerizaion. The hermal shu down emperaure refers o he juncion emperaure of he conroller. Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep V VCCOVP and V VCCPD Version 2.0 21 3 Jul 2009
F3 PWM conroller Elecrical Characerisics 4.3.6 Curren Limiing Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Peak Curren Limiaion (incl. Propagaion Delay) Peak Curren Limiaion during Acive Burs V csh 0.99 1.06 1.13 V dv sense / d = 0.6V/µs (see Figure 20) V CS2 0.21 0.25 0.31 V Leading Edge LEB - 220 - ns CS Inpu Bias Curren I CSbias -1.5-0.2 - µa V CS =0V Over Curren Deecion for V CS1 1.57 1.66 1.76 V Lached Off CS Spike for Comparaor C11 CSspike - 190 - ns 4.3.7 Driver Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. GATE Low Volage V GATElow - - 1.2 V V VCC = 5 V I Gae = 1 ma - - 1.5 V V VCC = 5 V I Gae = 5 ma - 0.8 - V I Gae = 0 A - 1.6 2.0 V I Gae = 20 ma -0.2 0.2 - V I Gae = -20 ma GATE High Volage V GATEhigh - 10.0 - V V VCC = 25V C L = 680pF - 9.0 - V V VCC = 15V C L = 680pF - 8.0 - V V VCC = V VCCoff + 0.2V C L = 680pF GATE Rise Time rise - 150 - ns (incl. Gae Rising Slope) V Gae = 2V...9V 1) C L = 680pF GATE Fall Time fall - 55 - ns V Gae = 9V...2V 1) GATE Curren, Peak, Rising Edge GATE Curren, Peak, Falling Edge C L = 680pF I GATE -0.17 - - A C L = 680pF 2) I GATE - - 0.39 A C L = 680pF 2) 1) 2) Transien reference value The parameer is no subjeced o producion es - verified by design/characerizaion Version 2.0 22 3 Jul 2009
F3 PWM conroller Ouline Dimension 5 Ouline Dimension PG-DSO-8 (Plasic Dual Small Ouline) Figure 28 PG-DSO-8 (PB-free Plaing Plasic Dual Small Ouline) Dimensions in mm Version 2.0 23 3 Jul 2009
F3 PWM conroller Marking 6 Marking Marking Figure 29 Marking for Version 2.0 24 3 Jul 2009
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