A 60GHz Transceiver RF Front-End

TAMU ECEN625 FINAL PROJECT REPORT 1 A 60GHz Transceiver RF Front-End Xiangyong Zhou, UIN 421002457, Qiaochu Yang, UIN 221007758, Abstract This final report presents a 60GHz two-step conversion heterodyne RF front-end transceiver in 90nm CMOS technology. The front-end consists of a 20GHz quadrature upconversion mixer, a 40GHz up-conversion mixer and a wideband power amplifier with 4 path power amplifier with combining at the transmitter, and a wideband LNA, 40GHz down-conversion mixer, a 20GHz quadrature down-conversion mixer at the receiver. Local oscillator working at 40GHz and 20GHz dividers are included without PLL control loop to generate the transmitter and receiver LO. The LNA has a 3dB bandwidth of 9GHz with a NF of 2.2dB and consumes 26 mw power. The PA has a PEA of 10% and Power efficiency of 11%, at the DC power of 464mW and 116mW w/wo power combining. A 1dB conpression power of 6dBm and a saturated output power of 13dBm is delivered by the PA. The entire transceiver can transmit QPSK modulated signals at 3.5Gbps data rate in a 2.16GHz channel over 2m LOS. The constellation diagram gives a EVM of -20dB without digital compensation. The transmitter consumes 538mW power and the receiver consumes 153mW power with an overall NF of only 6.4dB. Index Terms 60GHz, transceiver, WPAN, high data rate, wireless, power combining, wideband, QPSK, 16QAM, heterodyne, IEEE802.15.3c, RF front-end. I. INTRODUCTION GHZ wireless data transmission technique is under 60active research in recent years. The unlicensed band of 9GHz around 60GHz is available for free in many countries like USA, Europe, Japan, and can be utilized to transmit high volumes of data in wireless mode which is not comparable by lower Ghz narrow band transmission techniques like WiFi, WiMax or UWB. Some promissing applications of this technique includes WPAN, WiGig and wirelesshd. The IEEE802.15.3c standard made at 2007 set the PHY frame for this technique while the RF front-end realization is still under active research. The IEEE802.15.3c allocates four channels each of 2.16GHz for the band from 57.24GHz to 65.88GHz for data transmission. A complete transceiver for IEEE802.15.3c needs to cover all the four channels with no significant degradation in performance between different channels in case OFDM modulation is used for full data transmission capacity. Three modes of operation are defines by IEEE802.15.3c with high speed and low speed transmission by single carrier QPSK, QAM or multi-carrier OFDM format. When using QPSK, a data rate of 3.5 Gb/s is mandated by the standard over a single channel and when using 16 QAM, a data rate of 7 Gb/s is mandated. This transceiver deals with the single carrier transmission mode, enabling both QPSK and 16 QAM RF to Baseband conversion over a long distance (2m) LOS (line of sight) wireless link. This report is organized as the following. Section II discusses the architecture and system level considerations of this transceiver. Section III discusses about the slow-wave CPW transmission line design. Section IV gives circuit details of each block in the transmitter. Section V gives circuit details of each block in the receiver. Section VI gives details of the 40 GHz LO and 20 GHz IQ LO for both transmitter and receiver. Section VII shows simulation results of the blocks and also the entire transceiver. A comparison to some recently published works is also given. Section VIII concludes the report. II. ARCHITECTURE The transceiver utilized a two step heterodyne frequency conversion architecture 1 to avoid the generation and distribution of 60 GHz LO signals over long distances which adds up phase noise and IQ imbalance, and attenuates amplitude quickly at this frequency [1]. The generation and distribution of 60 GHz IQ LO signals is difficult. A 60 GHz VCO runs at much higher power and also implies high phase noise, low tuning range and also high Kvco which makes PLL design difficult. Also, the amplified RF signal at 60GHz may give frequency pulling effect to the VCO and hence make some phase offset. Then an extra VCO buffer has to be used for better isolation [2]. Two step frequency conversion is used in this transceiver to avoid the 60 GHz LO so the power for the 60 GHz LO buffer can also be saved. Other approaches like polyphase filters can also be used in the signal path to seperate the quadrature signals, but the poly-phase filter with a single input from LNA demostrate poor phase and amplitude balance. IQ seperation then is done with LO frequency division. The 40 GHz LO drives an IQ frequency divider and gives 20 GHz IQ LO signals. IQ generation is easy to get by frequency division than by multiplication. Lower frequency of operation also makes mixer design easier. However, two more mixers implies the use of two more inductors being used. But the low-q wideband feature makes even low frequency inductors compact. Lower LO frequency of 30GHz can also be used. However, the same 30GHz IF frequency then inevitablly affects the VCO by frequency pulling [3]. A. Link Budget The link budget analysis is shown in Table I. The SNR of the TX output signal is very high whose noise will be totally covered by RX noise hence doesn t need consideration. The link is budgeted for the ultimate application of 16QAM OFDM ultra-high data rate of 28Gb/s using the entire 9GHz band. The high SNR required than calls for a high PA output power of 13dBm. The power from adjacent channel interference is negligible for the 13dB SNR at the same distance which is the implied case for short distance applications.

TAMU ECEN625 FINAL PROJECT REPORT 2 Component DC Power Gain Vppout Vn/NF/PN Pin_1dB TX 538mA 43dB 13dBm 20GHz Mix 17.5mA 2 11dB -15dBm 15dB 150mVpp 40GHz Mix 7.5mA 2 15dB -4dBm 12.5dB 200mVpp PA 116mA 4 17dB 13dBm 33aV 2 /Hz -17dBm RX 153mA 55dB 0dBm 6.4dB LNA 26mA 25dB -34dBm 2.4dB -27dBm 40GHz Mix 23mA 14dB -20dBm 10dB 75mVpp 20GHz Mix 40mA 2 15.7dB -4.3dBm 13dB 108mVpp 40GHz LO 8mA 2 1.15Vpp -95dBc 20GHz LO 8mA 4 1.3Vpp -100dBc Table II CIRCUIT SPEC. ASSIGNMENT Figure 1. TXRX Component Contribution Running Total Comment PA output Power 13dBm 13(Sig) OFDM Pmax Path Loss 74dB -61(Sig) 2m LOS Shadow Loss 10dB -71(Sig) Antenna Gain 6dBi -59(Sig) TX, RX each Pin @ RX -59dBm - - Background Noise -174 dbm/hz -174(Vn) KT@25 C Noise BW 93dB -81(Vn) over 2GHz ch. Adj. Inf. -69dBc Interference SNRin 22 RX NF 6 16(SNR) Margin 3 13(SNR) SNRout 13 BER(16QAM) 10 3 for 4ch. OFDM B. Circuit Specifications Table I LINK BUDGET ANALYSIS The acheived specs are both listed in Table II for all active circuit blocks. The overall receiver noise figure is measure using PSS simulation. This result is different from the 50Ω noise figure formula NF RX = NF LNA + NF Mix40GHz 1 NF Mix20GHz 1 G LNA G Mix40GHz G LNA + which gives only 2.47dB. The reason for this discrepancy come from inconsistant measurement setup since measurement for single LNA and mixer uses 50Ω termination while when measuring the entire receiver the 50Ω termination between stages are removed. The measurement setup uses ideal LO due to the lack of control loop, but at this low SNR the effect of LO phase noise is negligible. Figure 2. Slow-Wave CPW as the power in the secondary winding bounces back to each primary winding. However, for heat distribution power combining has to be used after all even if not on-chip [5]. III. PASSIVE ELEMENTS DESIGN A. Slow-Wave CPW Transmission Line The CPW transmission line as in Figure 2 uses a slow-wave structure [4]. The CPW is simulated in Sonnet, the output s- parameter file is then used in cadence simulation. The total transmission line width is 80um to save area. Figure 3. Power Combining Transformer B. Power Combining Transformer The power combining scheme uses a transformer series to add voltage together as in Figure 3. Power loss is inevitable C. RF Choke Inductor The RF choke inductor uses square on chip spiral inductors to save output pin count as in Figure 4. A quality factor of

TAMU ECEN625 FINAL PROJECT REPORT 3 more than 2 is maintained through the 9GHz band as in Figure??. Used as RF choke to keep out RF current, this low quality factor doesn t affect the high frequency performance that much as very little RF power goes through this high impedance path. The low impedance at DC also comsumes negligible DC power. It is simulated in Sonnet and s-parameter files are used in cadence simulation. output level of the Class A PA implies higher heat generation. Power combining technique is hence mandated in this scenario to distribute heat sources to different corners of the chip. For power transistor sizing, load pull analysis is done in Agilent ADS using the 90nm BSIM4 model. Three stages are matched at the maximum power of 13dBm at 1dB gain compression. Impedance mismatch is deliberately introduced to enhance bandwidth. Figure 6. Wideband Class-A Power Amplifier Figure 4. RF Choke Inductor IV. TRANSMITTER CIRCUITS DESIGN A. Up-Conversion Mixer Two double balanced mixers are used both at 20 GHz and 40 GHz for I and Q paths. The four outputs than connects to 4 PA then combined by a transformer. Wideband feature needs to be maintained within 2GHz range for each mixer by using a low-q inductor. V. RECEIVER CIRCUITS DESIGN A. Wideband Common Source LNA A wideband common source LNA as in [6] is used to simutaneously acheive high gain and low noise figure. The last stage is a cascode stage to enhance gain at minimum NF cost and also get better isolation from the 40 GHz mixer. To ensure stability each stage is inductively degenerated to make the K stability factor just above 1. For the input stage, the input impedance is usually not the same for maximum gain and minimum noise figure. A sweep of the transistor size and also the source inductor has to be done to make the two input impedance close enough to get best performance. The sweep is done in Agilent ADS to get the optimal input impedance while keeping conjugate matched condition. Figure 5. Up Conversion Mixers Figure 7. Wideband Common Source LNA B. Wideband Class-A Power Amplifier with 4 Path Power Combining Class A Power Amplifier is used for higher linearity [6]. At this frequency about fmax/4 most efficiency enhancedment techniques cannot be used. The lower efficiency and higher B. Down-Conversion Mixers The 40GHz down-conversion mixer uses a single balanced mixer with RLC tank bandpass filtering at 20 GHz. The tank can be made high Q with just flat band of 2.16 GHz channel

TAMU ECEN625 FINAL PROJECT REPORT 4 width. The leakage from 40 GHz LO and 60 GHz than get attenuated by the high Q filter. the entire band. S11 is matched to below -10dB over the band while S22 is a little worse near 56 GHz to be -6dB, otherwise it all below -10dB. However, regarding a single 2.16 GHz channel, the gain variation is less than 1dB, which makes baseband digital compensation easy to design. Figure 8. Down Conversion Mixers The 20GHz IQ mixer down converts the IF signal to baseband. The 2nd order RC low-pass load of the mixer filters away the down converted leakages at 20 GHz from 40 GHz LO and 40 GHz from 60 GHz RF leakage and also higher frequencies. A 2nd order high Q low-pass with cut-off frequency at 1.5 GHz can sufficiently remove high frequency interferences. The output waveform has an peak amplitude of 100mV, large enough to drive a 50Ω output buffer for baseband interfacing. VI. LO GENERATION AND DISTRIBUTION A cross-coupled VCO and two tail-injected frequency dividers are used to generate the 40GHz and 20GHz IQ LO signals. There will be inevitable phase offset between 40GHz and 20GHz LO signals. System level simulation demostrates that this offset does affect the final EVM for the same IQ balance at 20 GHz LO. Figure 10. Wideband Common Source LNA The PA consumes a DC power of 21.6dBm and has a saturated power of 13dBm at 5 dbm input power. The maximum power added efficiency is acheived at 2dBm input power to be 10% as in Figure 11, maximum output power efficiency with 17dB high gain is 11%, which is comparable to recent published 60 GHz PAs but with a much larger saturated power. The 1dB compression point of the PA occurs at -16dBm input power but with a output power of already 6dBm, large enough for reasonable distance wireless transmission. The maximum power gain of of the PA is 17dBm at -6dBm input power. The gain variation over the band is 3dB at in Figure 12, which become 1dB when power is restricted to within 1 channel, imposing not much burden to digital baseband. Figure 9. 40GHz/20GHz LO generation Figure 11. Power Added Efficiency vs Input Power VII. SIMULATION RESULTS AND COMPARISON The LNA gives a gain of more than 25dB with a 3dB bandwidth of of 10 GHz. A NF of 2.4dB is acheived over The 40 GHz and 20 GHz LO phase noise is shown in Figure 13. The 1MHz offset phase noise is -95dBc for 40GHz

TAMU ECEN625 FINAL PROJECT REPORT 5 TX and RX LO phases by the delay of the PA and LNA. At 60GHz, this delay is very difficult to detect and compensate in analog domain. This is usually done on digital BB chip by using another digital frequency locked loop to remove the frequency and phase offset [7]. Figure 12. Power Gain vs Frequency and -101dBc for 20GHz. This performance is lower than low GHz VCOs. However, the effect of close-in phase noise can be compensated later by digital circuits. The phase noise at 1GHz offset is -165dBc for both frequency LOs. This low phase noise compensates the wide bandwidth of 2.16GHz. At the same carrier power the interference is -69dBc, causing no danger of desensitization. The integrated adjacent inteference power than is simular to 2.4GHz WiFi standard. However, outside the 9GHz band, power emission still needs to satisfy the FCC regulation. Figure 14. Constellation Diagram VIII. CONCLUSIONS This work demostrates a 60GHz band single-chip QPSK transceiver RF front-end. The resultant EVM implies more than enough BER for QPSK modulation. Higher density modulation is also possible at this EVM. The EVM of 20dB can be further improved after the digital compesation for 16QAM modulation requirement. A data rate of 3.5 Gb/s can be transmitted by one 2.16GHz channels over the 2m wireless Link. Possible enhancement can be a 16QAM modulation using the same chip for a data rate of 7 Gb/s per channel as in [8]. REFERENCES Figure 13. 40GHz/20GHz LO phase noise The testbench of the entire transceiver consists of two 1.75 Gb/s PRBS generator for IQ baseband digital input, transmitter output to an -70dB variable gain attenuator, connecting the 50Ω antenna of the receiver, which then gives two differential IQ baseband digital 1.75 Gb/s PRBS stream. The constellation diagram is shown in Figure 14 with an EVM of -20dB. Ideal voltage buffers are used after LO signals to guarantee the same LO frequency. Phase offset between 40GHz and 20GHz are tested to be not affecting the system performance as long as the 20GHz LO signals maintain quadrature phase alignment. The constellation is rotated to some degree due to the inevitable phase misalignment of the [1] Behzad Razavi, A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider, IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 477 485, Feb. 2008. [2] Alexander Tomkins, etc., A Zero-IF 60 GHz 65nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2m Wireless Link, IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2085 2099, Aug. 2009. [3] Ali Parsa and Behzad Razavi, A New Transceiver Architecture for the 60-GHz Band, IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 751 762, Mar. 2009. [4] Stefano Pellerano, etc., A 64 GHz LNA With 15.5dB Gain and 6.5dB NF in 90nm CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1542 1552, Jul. 2008. [5] Jihwan Kim, etc., A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure, IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1034 1048, May 2011. [6] Jau-Jr Lin, etc., Wideband PA and LNA for 60-GHz Radio in 90-nm LP CMOS Technology, Compound Semiconductor Integrated Circuits Symposium, pp. 1 4, 2008. [7] Xiao Yan and Qian Wang, Frequency Pre-estimation Aided Carrier Recovery Algorithm for high-speed M-PSK communication, Communication Systems, 2008. ICCS 2008. 11th IEEE Singapore International Conference, pp. 1 4. [8] Kenichi Okada, etc., Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry, IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 46 65, Jan. 2013.