EE247 Lecture Data converters Sampling, aliasing, reconstruction Amplitude quantization Static converter error sources Offset Full-scale error Differential non-linearity (DNL) Integral non-linearity (INL) Measuring DNL & INL Servo-loop Code density testing (histogram testing) EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page Typical Sampling Process C.T. S.D. D.T. Continuous Time Sampled Data (e.g. T/H signal) time Physical Signals Clock Discrete Time "Memory Content" EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 2
Discrete Time Signals A sequence of numbers (or vector) with discrete index time instants Intermediate signal values not defined (not the same as equal to zero!) Mathematically convenient, non-physical We will use the term "sampled data" for related signals that occur in real, physical interface circuits EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 3 Uniform Sampling y(kt)=y(k) t= T 2T 3T 4T 5T 6T... k= 2 3 4 5 6... Samples spaced T seconds in time Sampling Period T Sampling Frequency f s =/T Problem: Multiple continuous time signals can yield exactly the same discrete time signal (aliasing) EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 4
Data Converters ADC/DACs need to sample/reconstruct to convert from continuous-time to discrete-time signals and back Purely mathematical discrete-time signals are different from "sampled-data signals" that carry information in actual circuits Question: How do we ensure that sampling/reconstruction fully preserve information? EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 5 Aliasing The frequencies f x and nf s ±f x, n integer, are indistinguishable in the discrete time domain Undesired frequency interaction and translation due to sampling is called aliasing If aliasing occurs, no signal processing operation downstream of the sampling process can recover the original continuous time signal! EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 6
Frequency Domain Interpretation Signal scenario before sampling Amplitude f in f s /2 Continuous Time f s 2f s.. f Signal scenario after sampling DT Amplitude.5 Discrete Time f/f s Signals @ nf S ±f max signal fold back into band of interest Aliasing EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 7 Brick Wall Anti-Aliasing Filter Amplitude Filter Continuous Time f s 2f s... f Discrete Time.5 f/f s Sampling at Nyquist rate (f s =2f signal ) required brick-wall anti-aliasing filters EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 8
Practical Anti-Aliasing Filter Desired Signal Parasitic Tone Continuous Time Attenuation B f s /2 f s -B f s... f Discrete Time B/f s.5 f/f s Practical filter: Nonzero "transition band" In order to make this work, we need to sample faster than 2x the signal bandwidth "Oversampling" EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 9 Data Converter Classification f s > 2f max Nyquist Sampling "Nyquist Converters" Actually always slightly oversampled (e.g. CODEC f sig max =3.4kHz & ADC sampling 8kHz f s /f max =2.35) Requires anti-aliasing filtering prior to A-to-D conversion f s >> 2f max Oversampling "Oversampled Converters" Anti-alias filtering is often trivial Oversampling is also used to reduce quantization noise, see later in the course... f s < 2f max Undersampling (sub-sampling) EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page
Continuous Time Sub-Sampling Amplitude BP Filter f s... f Discrete Time.5 f/f s Sub-sampling sampling at a rate less than Nyquist rate aliasing For signals centered @ an intermediate frequency Not destructive! Sub-sampling can be exploited to mix a narrowband RF or IF signal down to lower frequencies EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page Nyquist Data Converter Topics Basic operation of data converters Uniform sampling and reconstruction Uniform amplitude quantization Characterization and testing Common ADC/DAC architectures Selected topics in converter design Practical implementations Compensation & calibration for analog circuit non-idealities Figures of merit and performance trends EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 2
Where Are We Now? Analog Input We now know how to preserve signal information in CT DT transition Analog Preprocessing A/D Conversion DSP Anti-Aliasing Filter Sampling (+Quantization)... How do we go back from DT CT? D/A Conversion Analog Postprocessing? Analog Output EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 3 Ideal Reconstruction x(k) x(t) The DSP books tell us: k = x ( t) = x( k) g( t kt ) sin(2πbt) g( t) = 2πBt Unfortunately not all that practical... EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 4
Zero-Order Hold Reconstruction Amplitude.6.2 -.2 -.6 sampled data - after ZOH 2 3 Time [μs] How about just creating a staircase, i.e. hold each discrete time value until new information becomes available? What does this do to the frequency content of the signal? Let's analyze this in two steps... EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 5 DT CT: Infinite Zero Padding Time Domain Frequency Domain DT sequence.......5 f /f s Infinite Zero padded Interpolation: CT Signal.......5f s.5f s 2.5f s f /f s Next step: pass the samples through a sample & hold stage (ZOH) EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 6
Hold Pulse T p =T s Transfer Function abs(h(f)).8.6.4 sin( Tπ f T p sin(π s ) H( f ) = ftp ) H ( f ) = π f T T s πft s p.2.5.5 2 2.5 3 f /f s EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 7 ZOH Spectral Shaping Continuous Time Pulse Train Spectrum ZOH Transfer Function ("Sinc Shaping") ZOH output, Spectrum of Staircase Approximation.5.5.5 2 2.5 3.5.5.5 2 2.5 3.5.5.5 2 2.5 3 X(k) ZOH f / f s EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 8
Smoothing Filter.8.6.4 Filter out the high frequency content associated with staircase shape of the signal Order of the filter required is a function of oversampling ratio High oversampling helps reduce filter order requirement.2.5.5 2 2.5 3 f / f s EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 9 Summary Sampling theorem f s > 2f max, usually dictates anti-aliasing filter If theorem is met, CT signal can be recovered from DT without loss of information ZOH and smoothing filter reconstruct CT signal from DT vector Oversampling helps reduce order & complexity of anti-aliasing & smoothing filters EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 2
Next Topic Done with "Quantization in time" Next: Quantization in amplitude Analog Input Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Anti-Aliasing Filter Sampling (+Quantization)... D/A+ZOH Smoothing Filter Analog Output EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 2 Data Converter Performance Metrics Data Converters are typically characterized by static, time-domain, & frequency domain performance metrics : Static Offset Full-scale error Differential nonlinearity (DNL) Integral nonlinearity (INL) Monotonicity Dynamic Delay & settling time Aperture uncertainty Distortion- harmonic content Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR) Idle channel noise Dynamic range & spurious-free dynamic range (SFDR) EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 22
Ideal ADC ("Quantizer") Accepts & analog input & generates it s digital representation Quantization step: Δ (= LSB) Full-scale input range: -.5Δ (2 N -.5)Δ E.g. N = 3 Bits V FS = -.5Δ to 7.5Δ Digital Output Code Ideal converter with infinite # of bits ADC characteristics 7 6 5 4 3 2-2 3 4 5 6 7 8 V FS ADC Input Voltage [ Δ] EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 23 Quantization Error Quantization error Difference between analog input and digital output of the ADC converted to analog via an ideal DAC Called: Quantization error Residue Quantization noise V in ADC. Ideal DAC Residue - Σ ε q (V in ) + EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 24
Quantization Error For an ideal ADC: Quantization error is bounded by Δ/2 +Δ/2 for inputs within full-scale range V in ADC Model D + out ε q (V in ) Digital Output Code Quantization error [LSB] 7 6 5 ideal converter with infinite bits ADC characteristics 4 3 2-2 3 4 5 6 7 8.5 -.5-2 3 4 5 6 7 8 ADC Input Voltage [Δ] EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 25 ADC Dynamic Range Assuming quantization noise is much larger compared to circuit generated noise: D.R. Maximum Full Scale Signal Power = log Quantization Noise Power Crude assumption: Same peak/rms ratio for signal and quantization noise! D.R. Maximum Peak Full Scale = 2log Peak Quantization Noise VFS N = 2log = 2log 2 = 6. 2 N [ db ] Δ Question: What is the quantization noise power? EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 26
Quantization Error Assume V in is a slow ramp signal with amplitude equal to ADC full-scale V in _Ramp V FS Quantization error [LSB] Δ/2 Δ/2 Time Time Note: Ideal ADC quantization error waveform periodic and also ramp EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 27 Quantization Error Derivation Need to find the rms value for quantization error waveform: + T/2 + Δ /2k 2 2 Quantization 2 k εeq = ( k t) dt ( k t) = dt error T Δ k k = Δ 2 T/2 Δ/2k + Δ /2k 2 t dt Δ /2k 2 Δ/2 2 Δ ε Δ/2k eq = Independent of k 2 Δ Δ/2 εeq = 2 In general above equation applies if: Input signal much larger than LSB Input signal busy No signal clipping ε q =k.t Δ/2k Time EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 28
Quantization Error PDF Probability density function (PDF) Uniformly distributed from Δ/2 +Δ/2 provided that: Busy input Amplitude is many LSBs No overload Not Gaussian! Zero mean Variance +Δ /2 Δ /2 2 2 2 e Δ e = de= Δ 2 PDF /Δ Ref: W. R. Bennett, Spectra of quantized signals, Bell Syst. Tech. J., vol. 27, pp. 446-72, July 988. -Δ/2 +Δ/2 error B. Widrow, A study of rough amplitude quantization by means of Nyquist sampling theory, IRE Trans. Circuit Theory, vol. CT-3, pp. 266-76, 956. EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 29 Signal-to-Quantization Noise Ratio If certain conditions the quantization error can be viewed as being "random", and is often referred to as noise In this case, we can define a peak signal-to-quantization noise ratio, SQNR, for sinusoidal inputs: N 2 2 Δ e.g. N SQNR 2 2 8 5 db 2N SQNR= =.5 2 2 74 db 2 Δ 6 98 db 2 2 22 db = 6.2N +.76 db Accurate for N>3 Real converters do not quite achieve this performance due to other sources of error: Electronic noise Deviations from the ideal quantization levels EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 3
Static Ideal Macro Models DAC D in V out V in ADC + ε q D out +-.5LSB ambiguity EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 3 Cascade of Data Converters q ADC DAC V in + ε V out D in DAC ADC + εq D out EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 32
Static Converter Errors Deviation of converter characteristics from ideal: Offset Full-scale error Differential nonlinearity DNL Integral nonlinearity INL EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 33 ADC Offset Error DAC Ref: Understanding Data Converters, Texas Instruments Application Report SLAA3, Mixed-Signal Products, 995. EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 34
Full-Scale Error ADC Actual full-scale point Ideal full-scale point DAC Ideal full-scale point Full-scale error Full-scale error Actual full-scale point EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 35 Offset and Full-Scale Errors Alternative specification in % Full-Scale = % * (# of LSB value)/ 2 N Gain error can be extracted from offset & full-scale error Non-trivial to build a converter with extremely good full-scale/offset specs Typically full-scale/offset error is most easily compensated by the digital pre/post-processor More critical: Linearity measures DNL, INL EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 36
Offset and Full-Scale Error Note: For further measurements (DNL, INL) connecting the endpoints & deriving ideal codes based on the non-ideal endpoints eliminates offset and fullscale error Digital Output Code 7 6 5 4 3 2 ADC characteristics ideal converter Offset error Full-scale error - 2 3 4 5 6 7 8 ADC Input Voltage [LSB] EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 37 ADC Differential Nonlinearity DNL = deviation of code width from Δ (LSB). Endpoints connected 2. Ideal characteristics derived eliminating offset & full-scale error 3. DNL measured code width deviation from LSB Digital Output Code 8 7 6 5 4 3 2 ADC Transfer Curve Real Ideal -.4 LSB DNL error LSB DNL error +.4 LSB DNL error 2 3 4 5 6 7 8 ADC Input Voltage [Δ] EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 38
ADC Differential Nonlinearity Ideal ADC transitions point equally spaced by LSB For DNL measurement, offset and full-scale error is eliminated DNL [k] (a vector) measures the deviation of each code from its ideal width Typically, the vector for the entire code is reported If only one DNL # is presented that would be the worst case EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 39 ADC DNL DNL=- implies missing code For an ADC DNL < - not possible undefined Can show: all i DNL[i] = For a DAC possible to have DNL < - EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 4
DAC Differential Nonlinearity EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 4 DAC Differential Nonlinearity To find DNL for DAC Draw end-point line from st point to last Find ideal LSB size for the end-point corrected curve Find segment sizes: segment [m]=v[m]-v[m-] segment[m] V[LSB] DNL[m] = V[LSB] Unlike ADC DNL, for a DAC DNL can be <-LSB EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 42
Impact of DNL on Performance Same as a somewhat larger quantization error, consequently degrades SQNR How much later in the course... The term "DNL noise", usually means "additional quantization noise due to DNL" EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 43 ADC Integral Nonlinearity End-Point INL = deviation of code transition from its ideal location. Endpoints connected 2. Ideal characteristics derived eliminating offset & full-scale error (same as for DNL) 3. INL deviation of code transition from ideal is measured Digital Output Code 7 6 5 4 3 2 - LSB INL - 2 3 4 5 6 7 8 ADC Input Voltage [Δ] EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 44
ADC Integral Nonlinearity INL = deviation of code transition from its ideal location INL is also a vector INL[k] If one INL # reported Worst case INL ADC Transfer Function Output INL Max Real Ideal Most common End-point: Straight line through the endpoints is usually used as reference, i.e. offset and full scale errors are eliminated in INL calculation INL INL Max Input Ideal converter steps found for the endpoint line, then INL is measured INL Curve Digital Output EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 45 ADC Integral Nonlinearity Best-Fit INL = deviation of code transition from its ideal location Output Best-Fit A best-fit line (in the leastmean squared sense) fitted to measured data Ideal converter steps found then INL measured Real Ideal Input ADC Transfer Function INL Note: Typically INL #s smaller for best-fit compared to end-point INL Curve EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 46
ADC Integral Nonlinearity Best Fit versus End-Point Best-Fit A best-fit line (in the least-mean squared sense) Ideal converter steps is found then INL is measured Digital Output Code 7 6 5 4 3 2 -/2 LSB INL +/2 LSB INL Best Fit End-point INL max =LSB Best-fit INL max =+-/2LSB - 2 3 4 5 6 7 8 ADC Input Voltage [Δ] EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 47 ADC Integral Nonlinearity Can derive INL by: - Construct uniform staircase between st and last transition INL for each code: T[m] T[ideal] INL[m] = W[ideal] 2- Can show m INL[m] = i= DNL[i] INL is found by computing the cumulative sum of DNL EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 48
ADC Differential & Integral Nonlinearity Example m INL[m] = i= DNL[i] Code # - DNL [LSB] INL [LSB] - Notice: 2.8 -.55.8 INL[] undefined INL[]= 3 4 5.55 -.55 -.27 -.37.8 -.37 INL[2 N -]= 6 7.64 - -.64 EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 49 DNL [LSB] INL [LSB].5 -.5 ADC Differential & Integral Nonlinearity Example - 2 3 4 5 6 7.5 Max. DNL -.5 Max. - INL 2 3 4 5 6 7 Code # Code # INL [LSB] - EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 5 2 3 4 5 6 7 -.8 -.55.55 -.55 -.27.64 - DNL [LSB].8 -.37.8 -.37 -.64
Can derive INL by: Connect end points Find ideal output values INL for each code: DAC Integral Nonlinearity V[m] V[ideal] INL[m] = V[LSB] 2- Can show m INL[m] = i= DNL[i] INL is found by computing the cumulative sum of DNL EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 5 DAC Integral Nonlinearity EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 52
DAC DNL and INL * Ref: Understanding Data Converters, Texas Instruments Application Report SLAA3, Mixed-Signal Products, 995. EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 53 Example: INL & DNL Large INL & Small DNL Smooth variations in transfer curve Small DNL Large DNL & Small INL Abrupt variations in transfer curve Large DNL EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 54
Non-Monotonic DAC segment[m] V[LSB] DNL[m] = V[LSB] segment[4] V[LSB] DNL[4] = V[LSB].5 = =. 5[ LSB] 2.5 DNL[5] = =.5[LSB] DNL< -LSB for a DAC Non-monotonicity When can non-monotonicity cause major problems? 7 6 5 4 3 2 Analog Output [LSB] -.5 2.5 Digital Input EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 55 Non-Monotonic ADC Code associated with two transition levels! For non-monotonic ADC DNL not defined @ nonmonotonic steps Digital Output Analog input Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 56
How to measure DNL/INL? DAC: Simply apply digital codes and use a good voltmeter to measure corresponding analog output ADC Not as simple as DAC need to find "decision levels", i.e. input voltages at all code boundaries One way: Adjust voltage source to find exact code trip points "code boundary servo" More versatile: Histogram testing Apply a signal with known amplitude distribution and analyze digital code distribution at ADC output EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 57 Code Boundary Servo Input Digital Code A A<B Digital Comp. B A B i C R 2 ADC Input V REF f S ADC Under Test C 2 i 2 ADC Output EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 58
Code Boundary Servo i and i2 are small, and C is large (dv=it/c), so the ADC analog input moves a small fraction of an LSB (e.g..lsb) each sampling period For a code input of, the ADC analog input settles to the code boundary shown ADC Digital Output Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ ADC Analog Input EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 59 Input Digital Code Code Boundary Servo A A<B Digital Comp. B A B i i 2 C ADC Output R 2 C 2 Good DVM V REF f S ADC EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 6
Code Boundary Servo A very good digital voltmeter (DVM) measures the analog input voltage corresponding to the desired code boundary DVMs have some interesting properties They can have very high resolutions (8½ decimal digit meters are inexpensive) To achieve stable readings, DVMs average voltage measurements over multiple 6Hz ac line cycles to filter out pickup in the measurement loop EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 6 Code Boundary Servo ADCs of all kinds are notorious for kicking back high-frequency, signal-dependent glitches to their analog inputs R 2 Good DVM V REF f S ADC A magnified view of an analog input glitch follows C 2 EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 62
Code Boundary Servo Just before the input is sampled and conversion starts, the analog input is pretty quiet As the converter begins to quantize the signal, it kicks back charge analog input start of conversion /f S time EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 63 Code Boundary Servo The difference between what the ADC measures and what the DVM measures is not ADC INL, it s error in the INL measurement analog input DVM measures the average input including the glitch How do we control this error? ADC converts this voltage /f S time EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 64
Code Boundary Servo A large C 2 reduces the effect of kick-back At the expense of longer measurement time R 2 Good DVM V REF f S ADC C 2 EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 65 Histogram Testing Code boundary measurements are slow Long testing time Histogram testing Quantize input with known pdf (e.g. ramp or sinusoid) Measure output pdf Derive INL and DNL from deviation of measured pdf from expected result EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 66
Histogram Test Setup V REF f S Ramp V REF ADC PC Time Slow (wrt conversion time) linear ramp applied to ADC DNL derived directly from total number of occurrences of each code @ the output of the ADC EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 67 A/D Histogram Test Using Ramp Signal Example: ADC sampling rate: f s =khz T s =μsec Digital Output ADC Input/Output LSB =mv For.LSB measurement resolution: n = samples/code Analog input Ramp duration per code: =xμsec=msec Ramp slope: mv/msec n.t s Time Ramp EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 68
A/D Histogram Test Using Ramp Signal Example: Ramp slope: mv/msec LSB =mv Each ADC code msec f s =khz T s =μsec Digital Output ADC Input/Output Analog input n = samples/code n/f s Ramp Time # of Samples Per code Digital Output EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 69 Ramp Histogram Example: Ideal 3-Bit ADC Digital Output Code 7 6 5 4 3 2 ADC characteristics ideal converter Code Count 2 8 6 4 2 8 6 4 2 2 3 4 5 6 7 8 ADC Input Voltage [Δ] 2 3 4 5 6 7 ADC output code EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 7
Ramp Histogram Example: Real 3-Bit ADC Including Non-Idealities 7 ADC characteristics ideal converter 2 8 Digital Output Code 6 5 4 3 2 -.4 LSB DNL +.4 LSB INL Code Count 6 4 2 8 6 +.4 LSB DNL 4 2 2 3 4 5 6 7 8 ADC Input Voltage [Δ] 2 3 4 5 6 7 ADC output code EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 7 Example: 3 Bit ADC DNL Extracted from Histogram - Remove Over-range bins ( and full-scale) 2- Compute average count/bin (6/6= in this case) Code Count, End bins removed 4 2 8 6 4 2 2 3 4 5 6 7 ADC output code EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 72
Example: 3 Bit ADC Process of Extracting from Histogram 3- Normalize: - Divide histogram by average count/bin ideal bins have exactly the average count, which, after normalization, would be Normalized Code Count Non-ideal bins would have.2 a normalized value greater of smaller than 2 3 4 5 6 7 ADC output code.4.2.8.6.4 EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 73 Example: 3 Bit ADC DNL Extracted from Histogram 4- Subtract from the normalized code count 5- Result DNL (+-.4LSB in this case) DNL = Counts / Mean(Counts) -.4.3.2. -. -.2 -.3 -.4 2 3 4 5 6 7 ADC output code EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 74
Example: 3-Bit ADC Static Characteristics Extracted from Histogram DNL histogram used to reconstruct the exact converter characteristic (having measured only the histogram) Width of all codes derived from measured DNL (Code=DNL + LSB) INL (deviation from a straight line through the end points)- is found Digital Output 7 6 5 4 3 2 Reconstructed ADC Transfer Characteristic 2 3 4 5 6 7 ADC Input Voltage EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 75 Example: 3 Bit ADC DNL & INL Extracted from Histogram Digital Output Code 7 6 5 4 3 2 ADC characteristics Ideal converter -.4 LSB DNL +.4 LSB INL +.4 LSB DNL 2 3 4 5 6 7 ADC Input Voltage [Δ] DNL [LSB] INL [LSB].5 -.5-2 3 4 5 6.5 -.5-2 3 4 5 6 Digital Output Code EECS 247 Lecture : Intro. to Data Converters & Performance Metrics 29 H. K. Page 76