Source/Drain Parasitic Resistance Role and Electric Coupling Effect in Sub 50 nm MOSFET Design 9/25/2002 Jun Yuan, Peter M. Zeitzoff*, and Jason C.S. Woo Department of Electrical Engineering University of California, Los Angeles * SEMATECH, Austin, TX
Outline Introduction Simulated Device Structure Source/Drain Engineering Contact Depth Effect in S/D Region Conclusions
Introduction MOSFET device performance is determined by carrier transportation, Source/Drain (S/D) electrostatic coupling, and parasitic resistance/capacitance effects Critical parameters for digital: I on / I off, DIBL, C*V/I MOSFET is driven into nanoscale regime 2 Carrier transportation is enhanced velocity overshoot 2 Worse SCE increased S/D electrostatic coupling effect Scaled down S/D junction depth S/D series resistance limitation
Introduction (cont) Reduce gate oxide thickness to enhance gate controllability gate tunneling limitation Increase substrate doping to reduce S/D electric coupling Carrier mobility, B-B tunneling and junction capacitance 2 R con / R c h is increased L g & T ox, contact area look for new material to reduce schottky barrier height (Φ B ) The purpose of this work is to study parasitic resistance role and S/D electric coupling effect in 45nm NMOS design, thus provide guideline for further scaling down of conventional bulk device
Outline Introduction Simulated Device Structure Source/Drain Engineering Contact Depth Effect in S/D Region Conclusions
Simulated Device Structure (NMOS) contact Source POLY contact Drain L gate = 45nm L m = 30nm T gate,eq = 0.8nm K gate = 25 SDE offset region X je = 15nm X jc = 45nm Si substrate n - = 1~5x10 19 /cm 3 n + = 3x10 20 /cm 3 Abrupt junction is defined since hot carrier effect is not an issue SILVACO tool is used with energy balance model
Outline Introduction Simulated Device Structure Source/Drain Engineering Contact Depth Effect in S/D Region Conclusions
S/D Extension Doping Effect 700 110 Ion (µa/µm) 650 600 550 500 450 400 350 I on,offset=0nm 300 I on,offset=7.5nm DIBL,offset=0nm 250 DIBL,offset=7.5nm 10 18 10 19 10 20 100 90 80 70 60 50 40 DIBL (mv/v) ρ c = 1.2x10-7 Ω/µm 2 V dd =0.8 V I off =10 na/µm Extension doping concentration (cm -3, log) SCE is very sensitive to SDE doping (1x10 19 cm -3 ~1x10 20 cm -3 ) SDE doping in nonzero offset region is critical to series resistance
S/D Extension Offset Length Effect 550 130 120 I on (µa/µm) 500 450 400 350 Ion,SDE=5x10 19 cm -3 Ion,SDE=1x10 19 cm -3 DIBL,SDE=5x10 19 cm -3 DIBL,SDE=1x10 19 cm -3 110 100 90 80 70 60 50 40 30 DIBl (mv/v) Normalied C*V/I 1.05 1.00 0.95 0.90 0.85 0.80 N ext =5x10 19 cm -3 N ext =1x10 19 cm -3 0.75-10 -5 0 5 10 15 20 Extension offset length (nm) -10-5 0 5 10 15 20 Extension offset length (nm) S/D series resistance is increased with SDE offset length increment DIBL can be decoupled from deep S/D region with large spacer design Device with low SDE doping but zero offset length design can improve Ion, DIBL and C*V/I
SDE-to-Gate Overlap Depth/Length Effect 650 600 Ion,N ext =1x10 19 cm -3 Ion,N ext =5x10 19 cm -3 110 100 100 95 90 I off =10nA/µm 650 600 550 85 550 I on (µa/µm) 500 450 400 350 300 I off =10nA/µm DIBL,N ext =1x10 19 cm -3 DIBL,N ext =5x10 19 cm -3 0 50 100 150 200 Extension junction depth (Α) 90 80 70 60 DIBL (mv/v) DIBL (mv/v) 80 75 70 65 60 55 DIBL, doping=1x10 19 cm -3 DIBL, doping=5x10 19 cm -3 I on, doping=1x10 19 cm -3 I on, doping=5x10 19 cm -3 0 25 50 75 SDE-to-Gate overlap length (A) 500 450 400 350 Ion (µa/µm) Drive current is independent of SDE-togate overlap depth/length due to trade-off between V th and overlap resistance SDE-to-gate overlap can be eliminated to reduce SCE and overlap capacitance Source POLY ~ ~
Zero & Nonzero Gate-to-SDE overlap Device Performance Comparison (1) Drain current (µa/µm) 700 650 600 550 500 with ext. overlap without ext. overlap Lg=45nm Drain current (µa/µm) 650 600 550 500 450 400 350 300 250 200 with ext. overlap without ext. overlap Lg=500nm 10-9 10-8 10-7 10-6 leakage current (A/µm) 450 10-9 10-8 10-7 10-6 Leakage current (A/µm) Long channel: device with overlap has higher current drive due to smaller effective channel length, I on L eff -1 Short channel: Similar I on /I off performance due to velocity saturation and SCE limitation
Zero & Nonzero Gate-to-SDE Overlap Device Performance Comparison (2) 1.05 normalized C*V/I 1.00 0.95 0.90 0.85 0.80 Lg=45nm with ext. overlap without ext. overlap 0.75 10-9 10-8 10-7 10-6 leakage current (A/µm) normalized C*V/I 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Lg=500nm with ext. overlap without ext. overlap 10-9 10-8 10-7 10-6 leakage current (A/µm) Long channel: SDE-to-Gate overlap improves device intrinsic speed due to enhanced drive current Short channel: SDE-to-Gate overlap degrades device speed due to increased overlap capacitance
Deep S/D Junction Depth Effect DIBL (mv/v) 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 I off =10nA/µm DIBL, doping=3x10 20 cm -3 DIBL, doping=3x10 21 cm -3 I on, doping=3x10 20 cm -3 I on, doping=3x10 21 cm -3 640 620 600 580 560 540 520 500 480 460 Ion (µa/µm) contact Source Source POLY POLY ~ ~ ~ ~ 100 200 300 400 500 600 deep S/D junction depth (A) Shallow and highly doped Source/Drain is needed for high drive current and low DIBL
Outline Introduction Simulated device structure Source/Drain Engineering Contact depth effect in S/D region Conclusions
Source/Drain contact resistance Contact resistance can be major parasitic resistance component in nanoscale MOSFET device Contact resistance can be reduced by increasing silicide interface doping concentration and reducing schottky barrier height Φ B: ρ Exp( Φ c B * ε / N d ) Recessed contact depth effect on contact resistance 2 Long contact limit device: silicide-diffusion resistance is increased with contact depth increment in S/D region 2How about in short contact limit device?
Recessed Contact Depth Effect 720 spacer gate Drain Current (µa/µm) 690 660 630 600 570 I on (µa/µm) Silicide 540 Junction 0 100 200 300 400 Contact electrode depth in source/drain region (A) Unlike long contact limit case, Current drive capability is enhanced by increased contact depth in S/D region for short contact limit device Reason: current flows to both bottom and side of contact electrode
Optimized MOSFET Bulk Device POLY contact Source contact Drain Si substrate Device structure is optimized based on S/D series resistance, short channel effect and recessed contact depth effect Bulk device can be further scaled down below 45nm
Outline Introduction Simulated Device Structure Source/Drain Engineering Contact Depth Effect in S/D Region Conclusions
Conclusions MOSFET Short Channel Effect is Source/Drain (S/D) electrostatic coupling result SCE is sensitive to SDE doping and junction depth, but it can be de-coupled from deep S/D region Doping concentration and length in SDE offset region is critical to S/D series resistance Shallow and highly doped S/D is expected for both I on and DIBL
Conclusions Unlike long channel device, SDE-to-Gate overlap in nanoscale device can be eliminated without degrading I on /I off performance due to velocity saturation limitation and S/D electric coupling effect Zero SDE-to-Gate overlap design can improve device speed in nanoscale MOSFET device Increased contact electrode depth in S/D region can enhance drive current in short contact limit case due to increased current spreading