Record Extrinsic Transconductance (2.45 ms/μm at = 0.5 V) InAs/In 0.53 Ga 7 As Channel MOSFETs Using MOCVD Source-Drain Regrowth Sanghoon Lee 1*, C.-Y. Huang 1, A. D. Carter 1, D. C. Elias 1, J. J. M. Law 1, V. Chobpattana 2, S. Krӓmer 2, B. J. Thibeault 1, W. Mitchell 1, S. Stemmer 2, A. C. Gossard 2, and M. J. W. Rodwell 1 1 ECE and 2 Materials Departments University of California, Santa Barbara, CA 2013 Symposium on VLSI Technology Kyoto, Japan 06/13/2013 *sanghoon_lee@ece.ucsb.edu 1
Outline Motivation: Why III-V MOSFETs? Design Considerations Process Flow Key Process Developments - Damaged Surface removal - Interfacial trap Passivation Measurement Results - I-V Characteristics - Gate leakage & TLM measurement - Peak g m and R on VS L g (Benchmarking) Conclusion 2
Why III-V MOSFETs in VLSI? more transconductance per gate width more current (at a fixed V dd ) IC speed or reduced V dd (at a constant I on ) reduced power or reduced FET widths reduced IC size increased transconductance from: low mass high injection velocities lower density of states less scattering higher mobility in N+ regions lower access resistance Other advantages heterojunctions strong carrier confinement wide range of available materials epitaxial growth atomic layer control 3
Key Design Considerations Device structure: Scalability (sub 20 nm-l g,<30 nm contact pitch) : self-aligned S/D, very low ρ c Carrier supply: heavily doped N+ source region Shallow junction: regrown S/D or Trench-gate Channel Design: Thinner wavefunction depth: Thin channel More injection velocity: higher In-content channel Gate Dielectric: Thinner EOT : scaled high-k dielectric Low D it : surface passivation, minimized process damage 4
Process Flow 5 nm n+ InGaAs (Capping layer) 3/5/3 nm In 0.53 GaAs/InAs/In 0.53 GaAs (Channel) 3 nm 3.9e12/cm 2 Pulse doping - Epitaxial layer growth using MBE HSQ 5 nm n+ InGaAs (Capping layer) 3/5/3 nm Composite Channel - Dummy gate definition using e-beam lithography HSQ N+ InGaAs (Regrown S/D) 5 nm n+ InGaAs (Capping layer) 3/5/3 nm Composite channel - N+ InGaAs S/D regrowth using MOCVD N+ InGaAs (Regrown S/D) Capping layer 3.6 nm HfO 2 Ni/Au N+ InGaAs (Regrown S/D) Capping layer Ti/Pd/ Au Ni/Au S/D metal N+ InGaAs (Regrown S/D) Capping layer 5/3 nm InAs/InGaAs channel 5/3 nm InAs/InGaAs channel 5/3 nm InAs/InGaAs channel - Dummy gate removal - Capping layer digital etching - High-k deposition - Post Deposition Annealing - Gate metal deposition 5 - S/D metal deposition
Capacitance ( F/cm 2 ) Evidence of Surface Damage During Regrowth Long-channel FETs: consistently show >100 mv/dec. subthreshold swing Indicates high D it despite good MOSCAP data. Suggests process damage. Experiment: SiO 2 capping + high temp anneal + strip MOSCAP Process Finding: large degradation in MOSCAP dispersion. Confirms process damage hypothesis. 1.2 Control SiO 2 Capped, 500 o C anneal 1 0.6 1 KHz 10 KHz 100 KHz 1 MHz Large dispersion Large D it 0.2 0-2 -1 0 1 2 Voltage (V) -2-1 0 1 2 6 Voltage (V)
Post-Regrowth Surface Digital Etching for Damage Removal HSQ N+ InGaAs (Regrown S/D) 5 nm n+ InGaAs (Capping layer) 3/5/3 nm Composite channel Damaged surface N+ InGaAs (Regrown S/D) Capping layer 5/3 nm InAs/InGaAs channel - Surface removed by digital etch process # cycles: 15 UV ozone (surface oxidation) 1 dilute HCl (native oxide removal) Ti/Pd/ Au 13-15 Ȧ/cycle, ~0.16 nm RMS roughness Ni/Au S/D metal - Etch significantly N+ InGaAs improves (Regrown S/D) swing and transconductance Capping layer - Using this 5/3 nm technique, InAs/InGaAs channel the upper cladding of the composite channel is removed 7
D it Passivation : In-situ N 2 plasma and TMA pretreatment False inversion - Cyclic H 2 plasma and TMA treatment D it passivated (A. Carter et al., APEX 2012) H 2 +TMA+H 2 N 2 +TMA+N 2 - Lower Midgap D it for N 2 plasma pretreatment - Al 2 O 3 interfacial layer is not needed (V. Chobpattana, et al. APL 2013) 8
Cross-sectional STEM image Ni 3.6 nm HfO 2 60 nm 5 nm InAs L g ~40 nm 3 nm In 0.53 GaAs In 0.52 AlAs 8 nm channel (5 nm/3 nm InAs/In 0.53 GaAs) ; The InAs channel is not relaxed ~ 3.5 nm HfO 2 and ~0.5 nm interfacial layer formed by cyclic N 2 and TMA treatment 9
Current Density (ma/ m) Current Density (ma/ m) Gm (ms/ m) Gm (ms/ m) Current Density (ma/ m) Current Density (ma/ m) Current Density (ma/ m) Current Density (ma/ m) I-V characteristics for short and long channel devices W = 10.1 μm, L = 40 nm / 70 nm / 90 nm 1.8 1.6 1.4 1.2 1.0 0.6 0.2 0.0 40 nm 70 nm 90 nm -0.2 0.0 0.2 0.6 Gate Bias (V) = 0.5 V 2.8 2.4 2.0 1.6 1.2 0.0 W = 10.1 μm, L = 510 nm 2.4 2.0 1.6 1.2 0.0 =0.05 V =0.5 V -0.2 0.0 0.2 0.6 Gate Bias (V) 2.4 2.0 1.6 1.2 0.0 10 1 =0.5 V 10 0 10-1 10-2 10-3 10-4 10-5 -0.2 0.0 0.2 0.6 Gate Bias (V) 10 1 =0.05 V 10 0 10-1 10-2 10-3 10-4 10-5 10-6 =0.5 V ~2.45 ms/μm Peak Gm at =0.5 V, 93 mv/dec long-channel SS 10 =0.05 V 40 nm 70 nm 90 nm SS ~ 93 mv/dec at =0.05 V -0.2 0.0 0.2 0.6 Gate Bias (V) 2.2 2.0 V GS = - V to 1.4 V 1.8 0.2 V increment 1.6 1.4 R on = 214 Ohm- m 1.2 1.0 0.6 0.2 0.0 0.0 0.1 0.2 0.3 0.5 0.7 0.6 0.5 0.3 0.2 0.1 Drain Bias (V) V GS = - V to 1.4 V 0.2 V increment R on = 495 Ohm- m 0.0 0.0 0.1 0.2 0.3 0.5 Drain Bias (V)
Resistance (Ohm- m) Gate leakage (A/cm 2 ) Gate leakage, access resistance, g m uniformity 10-1 800 10-2 700 600 500 400 300 Ti/Pd/Au Gap 60 nm n++ InGaAs (regrown contact layer) 5 nm n++ InGaAs (Capping layer) Y = 21.8 + 25.1X ~1.2 μm 10-3 10-4 10-5 10-6 10-7 =0.5 V =0.05 V -0.2 0.0 0.2 0.6 Gate Bias (V) = 200 100 Ti/Pd/Au 50 nm n++ InGaAs (regrown) 5 nm n++ InGaAs 0 0 5 10 15 20 25 Gap ( m) 3/4/3 nm In 0.53 GaAs/InAs/In 0.53 GaAs 400 nm In 0.52 AlAs (UID) R sheet = 25 ohm/sq ρ c = ~4.7 ohm-μm 2 ; ~82 Ohm-μm R SD : ~8% degradation gate leakage <10-4 A/cm 2 at all bias conditions 11 Gate metal S.I. InP 3 nm 3.9e12/cm 2 Pulse doping
G m_max (ms/ m) R on (Ohm- m) Peak g m and R on vs. L g (Benchmarking) 2.8 2.4 D.-H. Kim 2011 IEDM (HEMT) at V ds =0.5V 800 2.0 1.6 J.J. Gu 2012 IEDM D.-H. Kim 2012 IEDM T.-W. Kim 2012 VLSI Intel 2009 IEDM This work 600 400 D.-H. Kim 2012 IEDM Intel 2009 IEDM T.-W Kim 2012 IEDM This work 1.2 M. Egard 2011 IEDM Y. Yonai 2011 IEDM D.-H. Kim 2012 IEDM ( =1V) 200 M. Egard 2011 IEDM Y. Yonai 2011 IEDM 0.1 1 Gate length ( m) 0.01 0.1 1 Gate length ( m) Record G m over all the gate lengths Very Low R on when considering not fully self-aligned S/D contact 12
Conclusion Using digital etching, damaged surface during S/D regrowth can be effectively removed and the channel thinned in a nanometer precision without etch-stop. Employing N 2 plasma and TMA in-situ treatment, thin HfO 2 (3.5 nm) gate dielectric can be incorporated with low D it. Peak g m = 2.45 ms/μm at V ds =0.5 V for a 40 nm-l g device Regrown S/D provides very low access resistance (~ 200 ohm-μm) even with non-self aligned S/D metal contact. 13
Acknowledgment Thanks for your attention! Questions? This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.006). A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR05-20415. *sanghoon_lee@ece.ucsb.edu 14