RP220 Trigger update & issues after the new baseline By P. Le Dû pledu@cea.fr Cracow - P. Le Dû 1
New layout features Consequence of the meeting with RP420 in Paris last September Add 2 vertical detection system in the RP for elastic scattering Alignment and calibration (10 4 events per store @ 10 σ) Multiply the number of position planes by 3 Use 3D pixel detector (from RP420) Trigger plan read out using strip mode with fast read out. Si Trips with ABCD read out becomes a back up solution Separate the position and timing detectors Easier implementation : Cooling ) Position : Pixel 3D planes in the Roman Pot Time : Movable Beam Pipe ( from RP420) with GasTOF (15 psec resolution @ the early stage) and MCP (5 psec resolution in a second step) Cracow - P. Le Dû 2
MCP-PMT New Layout U Y V 8 x 8 Pixels Light Guide Radiator 3D pixels 3 time more channels MCP GASTOF S I D E U P D O W N Timing detectors Movable Beam Pipe Roman Pot B Roman Pot A 2 x 21 planes of 3D pixels Cracow - P. Le Dû 3
RP220 only PLtrack Trigger topologies JET 1 PL. AND PR track with ζ cut Et JET 1 AND 2 > 40 Gev JET Rapidity correlation? Dijet ENERGY /TOTAL > 0,9 RP 220 1 KHz @ 10 33 20-30 KHz @ 10 34 JET 2 RP 220 PR track RP220 + FP420 PL Track JET 1 PL track with ζ cut Et JET 1 AND 2 > 40 Gev JET 1 Rapidity Cut Dijet ENERGY /TOTAL > 0,9 1,6 KHz RP 220 JET 2 FP420 Cracow - P. Le Dû 4
Horizontal roman pots (a la TOTEM) - 224 m xa - 216 m xb Diffractive Trigger jet 5 plans Si strips /Roman Pot σ position 5 microns σ time < 10 psec PA SH Front end Pipeline buffer (6.4 µsec) xa xb T Left Pretrigger xa - xb =0 +850 ns (air cable) jet ATLAS detector LR Trigger Logic LP AND RP TR - TL L1 CTP Right Pretrigger 2 Jets with Pt > 40 Gev/c Max 75KHz xd - xc =0 T T R +730 ns 1,0 µsec 2,0 µsec 2,5µsec 30 nov 2006 R O D ATLAS standard HLT Trigger (ROB) Refined Jet Pt cut Vertice within millimeter Δ time < 5 to 10 psec Cracow - P. Le Dû ATLAS Standard 5 US15
Timing and Data flow Bing Proton @ RP 0 ns Flight path Pretrigger Data available @ 220 m(alcove) 733 ns Detector response 11 ns ABCD response 150 ns 20 ms cable 80 ns Pretrigger Processing 50 ns Processing RP Triigger Data @ ATLAS CTP 1024 ns RP ASIC & FPGA SI ---> 4 Events x 2 Si Strips x 10 bit words MCP ---> 4 Events x 6 bit words per ing = 104 bit/bx Average Rate = 4,16 Gbit/sec (11ns through cable to Alcove) ALCOVE µcta crate PRETRIGGER Matching 2RPs with overlap Si Strips Add Timing information from relevant MCP PMT pixel (1 mm 2) ) Cable 1921 ns 80 bit/b x 40 MHz = 3,2 Gb/s 80 bit @ 10 GB/s - 880 transfert time LVL1 ACCEPT (75 KHz) Processing RPs data @ ROD Data Production per Roman Pot to ROD 4 events x(7 Si detectors x10 bit word stored in the pipeline) 4 events x 1 MCP-PMT detector x (6 bit adress + 8 bit fine timing) Total per LV1 Accet = 336 bit Total x 75 KHz =25 Mb/s Max 2500 ns Cable 588 ns 5120ns 2x 1100 ns + 7.4 K bit @ 4x 5 Gb/s= 2620 ns Cracow - P. Le Dû 6
Implementation block diagram MBP RP B RP A // IP Detector ASIC Picosecond CLK 160 MHz Trigger DATA 4,16 Gb/s RO DATA 670 kb/s Local Logic 20 m Cables FPGA FPGA FPGA RP Left Trigger 1Cable L1 ACCEPT ATLAS LVL1 CTP RP Right Trigger 2 x 3,2 Gb/s DATA 4 fiberss ATLAS ROD (LVL2 LHC & CLK DAQ) µcta crate 75 KHz Shielded Alcove Pretrigger logic Read Out Control & Monitoring 25 Mb/s 160 MHz CLK (fiber) Reference clock (Atomic) LHC CLK US 15 Cracow - P. Le Dû 7
Multi Chanel Plate PMT Operation photon Faceplate Photocathode Dual MCP Photoelectron ΔV ~ 200V ΔV ~ 2000V MCP-OUT Pulse Gain ~ 10 6 ΔV ~ 200V Anode Cracow - P. Le Dû 8
Major advances for TOF measurements in HEP Burle- Photonis MCP 2 x 2 sensitive area Development of MCP s with 6-10 micron pore diameters Ability to simulate electronics and systems to predict design performance Oscillator with predicted jitters << 100 femtosec Use Cherenkov light for incoming rel particle Custom Anode with Equal Time Transmission Lines + Capacitative return Two cards 2 x 2 connected to the MCP anode planes (8x8 pads) Picosecond card with picosecond Time stretcher SiGe chip includes: Discriminator 2 GHz PLL Time stretcher FPGA card includes 200ps TDC Control, calibration, interface Cracow - P. Le Dû 10 µm pores 860 fs 20 Pe IBM 8 HP Chip 9
Generating the signal Incoming rel. particle Use Cherenkov light fast Custom Anode with Equal Time Transmission Lines + Capacitative. Return Collect charge here differential Input to 200 GHz TDC chip A 2 x 2 MCP actual thickness ~3/4 e.g. Burle (Photonis) 85022 with mods Cracow - P. Le Dû 10
Equal Time Anode structure RF Transmission Lines Summing smaller anode pads into 1by 1 readout pixels An equal time sum make transmission lines equal propagation times Work on leading edge ringing not a problem for this fine segmentation Cracow - P. Le Dû 11
Synoptic of the MCP UC Read Out/DAQ chain Objective : 1 psec M C P DAQ Chip Fukung Tanget al. 200 MHz TDC (FPGA) Cracow - P. Le Dû 12
New MCP - PMT development Collaboration between U. Chicago (Henry Frisch et al.) Argonne FNAL Saclay Burle-Photonis Memorandum Of Undestanding to be signed next week Our needs 5 psec resolution ( instead of 1psec) Make the read out more easier --> fully digital 1 x 1 inch 2 instead of 2 x 2 8 x 8 64 outputs pixels of 3x3 mm 2 Cracow - P. Le Dû 13
ASIC MCP-PMT 8 x 8 Pixels MCP PMT implementation issues? Light Guide? Radiator Need to optimize (MC) Radiator thickness Nb of Photo electron Light guide angle Simulations by Tim Credo (UC) Cracow - P. Le Dû 14
Best results with 2 TOF counters in tandem From J. Va vra Cracow - P. Le Dû 15
Issues and workplan Common to RP420 (Join( effort) 3D pixel standard planes GasTOF and movable beampipe Trigger @ L2 Specific to RP220 (need( to find a better acronym) 3D large size detectors ( 2,5 x 2,5 cm 2 ) 3D Strips trigger planes fast read out MCP-PMT optimization and integration in movable beampipe --> MC simulation Trigger @ L1 Backgrounds produced in detectors Need for sweeping the low Pt particles? Cracow - P. Le Dû 16