Hot Swap Controller Features 0 to 90V operation, positive or negative supply / lock out & power-on-reset Circuit breaker 00ms startup timer Automatic retry or latched operation Low Power, 400µA sleep mode Active low power good -Lead SOIC package Applications 4V central office switching 4V cellular and fixed wireless systems 4V PBX systems Line cards 4V powered ethernet for VoIP Distributed power systems Power supply control 4V storage networks Electronic circuit breaker General Description The Supertex Hot Swap Controller provides inrush current limiting and other power supply support functions for hot swap equipment Current limiting is provided by control of an external MOSFET which is placed in the return line of the power supply connection Placement in the return allows use of an N-channel MOSFET without the need for high side driving An internal clamp at the GATE pin activates when full bias for the is not available, thus keeping the MOSFET in the off-state during the initial insertion phase As soon as adequate bias is available for the main control circuits, the (undervoltage) and (overvoltage) pins check for normal operating voltage on the power supply input Once normal operating voltage is present, the GATE voltage for the external MOSFET ramps up at a constant rate The rate is controlled by the value of an external capacitor placed at the pin At some point the external MOSFET channel is enhanced, allowing power supply current to flow, thereby energizing downstream power supply capacitors During the GATE ramp up the power supply current is monitored with the aid of an external sense resistor which forces reduction in the ramp rate when the power supply current reaches a set limit The limit is set by the value of the external sense resistor and the threshold of the current sense amplifier (0mV) Once inrush current subsides, the GATE voltage resumes its rise to the output voltage of an internal regulator V REG, with an output voltage ranging from to V When GATE is within V of V REG, GATE is pulled high to V REG with an internal switch, the open-drain pin pulls low, and the enters a low power mode Typical Application Circuit -4V R 47kΩ kω R 97kΩ V DD 4 mω Q IRF0 The includes a start-up timer and a circuit breaker function to protect the MOSFET from excessive power dissipation The start-up timer trips when the start-up phase exceeds 00ms The circuit breaker trips at double the current limit threshold (00mV) Upon tripping of either the start-up timer or the circuit breaker the MOSFET is turned off, and the pin becomes high impedance Thereafter, a programmable automatic retry timer allows the MOSFET to cool down before resetting and restarting The automatic retry can be disabled by adding an external resistor at the pin (about MΩ, see applications section) 7-4V C 0nF +0V NOTES: Undervoltage threshold () set to V Overvoltage threshold () set to V Startup current set to 4A 4 Circuit breaker set to A 00ms max startup time Automatic retry enabled Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Ordering Information Package Options Device -Lead SOIC (Narrow Body) 490x90mm body 7mm height (max) 7mm pitch LG-G -G indicates package is RoHS compliant ( Green ) Absolute Maximum Ratings Configuration Parameter Value V DD (referenced to V EE ) -0V to +00V 7 V (referenced to V EE ) -0V to +00V GATE V and V (referenced to V EE ) -0V to +V VEE 4 SENSE Operating ambient temperature, T J -40 C to + C -Lead SOIC (LG) Operating junction temperature, T J -40 C to + C Storage temperature range, T S - C to +0 C Absolute Maximum Ratings are those values beyond which damage to the device may occur Functional operation under these conditions is not implied Continuous operation of the device at the absolute rating level may affect device reliability All voltages are referenced to device ground Product Marking Y W W L L L L Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number = Green Packaging -Lead SOIC (LG) Electrical Characteristics (-40 O C to + C unless otherwise specified, all voltages are referenced to V EE ) Sym Parameter Min Typ Max Units Conditions Supply V DD Supply voltage 0-90 V --- I DD Supply current - 00 700 µa V DD = 4V, mode = limiting Standby mode supply current - 400 40 µa V DD = 4V, mode = standby and Comparators V RTH Rising threshold - - V Low to high transition V FTH Falling threshold - - V High to low transition V HYS Hysteresis - 00 - mv --- I Input current - - 0 na V = 9V Current Limit V CL Current limit threshold voltage 40 0 0 mv V = 9V, V = 0V V CB Circuit breaker threshold voltage 0 00 0 mv V = 9V, V = 0V Notes: Guaranteed by design Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Electrical Characteristics (-40 O C to + C unless otherwise specified, all voltages are referenced to V EE ) Notes: Sym Parameter Min Typ Max Units Conditions Gate Drive Output V GATE Maximum GATE drive voltage 0 V V = 9V, V =0V I GATEUP GATE drive pull-up current 00 - - µa V = 9V, V = 0V I GATEDOWN GATE drive pull-down current 40 - - ma V = 0V, V = 0V Ramp Timing Control (Test conditions: = 00µF, C = 0nF, V = 9V, V = 0V, External MOSFET is IRF0 ) I Ramp pin output current - 0 - µa V SENSE = 0V t POR Time from to GATE turn on 0 - - ms --- t RISE Time from GATE turn on to V SENSE limit 400 - - µs --- t LIMIT Duration of current limit mode - 0 - ms --- t Time from current limit to - 0 - ms --- V Voltage on ramp pin in current limit mode - - V --- t STARTLIMIT Start up time limit 0 00 0 ms --- t CBTRIP Circuit breaker delay time 0-0 µs t AUTO Automatic restart delay time - - s --- Power Good Output V (HI) Power good pin breakdown voltage 90 - - V is high May be extended by external RC circuit V (LO) Power good pin output low voltage - 0 0 V I = 0mA, is low Dynamic Characteristics t GATEHL delay - - 00 ns --- t GATEHL delay - - 00 ns --- This timing depends on the threshold voltage of the external N-Channel MOSFET The higher its threshold is, the longer this timing This voltage depends on the characteristics of the external N-Channel MOSFET V th = 0V for an IRF0 IRF0 is a registered trademark of International Rectifier Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Functional Block Diagram C Regulator & POR VIN V BG LO C Logic ~9V C Latch High Sleep D I S A B L E P U L L H I G H V REG 0A V BG : mirror buffer GATE Transconductor SENSE Transconductor kω gm k VEE Clamp Mechanism Functional Description The provides control over the power supply current on systems where circuit cards are inserted into live backplanes Such systems can frequently be found in the telecom, data networking and computing industry The device provides means of limiting the power supply current after contact with the live backplane is made, thereby protecting card and backplane connectors and reducing the voltage disturbance on the backplane s power supply Additional protection is provided in the form of a circuit breaker function and a start-up time limiter, both for protection of the external MOSFET and the system as a whole Start-up Sequence After first contact is made with the backplane, the tries to establish an internal bias supply of 0V During this time, GATE and are positively held low by circuitry that can operate with partial supply voltage, and is in a high impedance state When the internal bias supply is in regulation, the undervoltage () and overvoltage () comparators start monitoring the external power supply External resistor dividers at and pin set the window for normal operating supply voltage These may be two individual dividers, or a single divider with two taps, as shown in the application diagrams Once the power supply voltage is within normal operating range, a 0μA internal source turns on to charge an external capacitor at the pin The voltage at the GATE output follows the pin voltage with an offset of about V for control of the external MOSFET Power supply current starts to flow once the GATE voltage reaches the MOSFET threshold voltage, which is typically in the 0 to 40V range The current sense amplifier at the SENSE pin reduces the charging current in proportion to the supply current, thereby slowing the voltage rise at, and thus the rise of the GATE voltage At a sense voltage of 0mV the current is reduced to zero, and the and GATE voltages stop rising, thereby preventing a further rise in the power supply current Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom 4
Functional Description (cont) Once external power supply capacitors are charged, the power supply current subsides, and the current increases again to its maximum value of 0μA The and GATE voltages resume their rise When the voltage is within V of the internal supply, then GATE is connected to the internal supply, and the open-drain pin is pulled low, marking the end of the start-up If the start-up sequence is not finished within 00ms, then the internal start-up timer causes a reset of the and GATE voltage to 0V, and the automatic retry timer is started to allow the MOSFET to cool off After the retry delay a new startup sequence is initiated if the power supply voltage is within the normal operating range, as determined by the and comparators The circuit breaker monitors the sense amplifier for the presence of an overcurrent condition at all times The overcurrent threshold is set at twice the maximum inrush current threshold Should overcurrent occur, then and GATE are brought to zero, returs to high impedance, and the automatic retry timer is started The automatic retry timer can be disabled by attachment of an additional resistor at the pin if a latched shutdown is desired A further reduction in the ramp rate of the and GATE voltages can be attained by connection of a feedback capacitor from the drain node to the pin During startup the drain voltage drops at a rate proportional to the inrush current This falling voltage waveform can be used to further reduce the current that flows onto the capacitor, thereby reducing the maximum inrush current Design Information Setting up the and comparators The following example shows how the resistors for the threshold setting divider can be determined The procedure applies to the (R,, R) divider having two taps as shown on the typical applications diagram The following procedure bases the selection of the divider resistors on specification of the shutdown / disable voltages A similar procedure can be devised that bases selection on specification of the enable voltages Let s assume the following: nominal divider current draw I NOM = 00μA, nominal power supply voltage V NOM = 0V, overvoltage shutdown voltage V S = V, undervoltage shutdown voltage V S = V, negligible (, ) comparator input currents, Comparator rising threshold V RTH = V Comparator falling threshold V FTH = V The following applies: R = (R + R + R ) R = V NOM / I NOM R = 00kΩ R follows from the shutdown voltage: DF = R / R V RTH = V S DF R = R V RTH / V S R = 99kΩ (97k %) R follows from the shutdown voltage: DF = (R + R ) / R V FTH = V S DF R + R = R V FTH / V S = 79kΩ (k %) And: R = 449kΩ (47k %) Now the upper and lower enable voltages can be determined: Lower Enable Voltage V LEN Upper Enable Voltage V UEN V RTH = DF V LEN V FTH = DF V UEN V LEN = 0V V UEN = 9V Programming Maximum Inrush Current and Circuit Breaker Current The values of the current limit threshold voltage V CL and the external current sense resistor R CS determine the maximum power supply current during startup I MAX (the maximum inrush current) Similarly the circuit breaker trip current I CB is determined by the values of the circuit breaker threshold voltage V CB and the value of R CS Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Design Information (cont) A numerical example: V CL = 0mV V CB = 00mV R CS = 0mΩ I MAX R CS = V CL I CB R CS = V CB I MAX = 0A I CB = 0A Timing contact bounce A number of false starts may be caused by contact bounce at the card edge The startup begins when V VIN rises through the lower enable voltage V LEN, whose level is programmed at the comparator t START During this time the voltage rises steadily as the 0μA current source charges capacitor C The voltage at the GATE pin starts to follow the pin voltage when V reaches a fixed offset voltage V OFS of about V after a delay indicated as t START in the figure t START I = V OFS C t START = ()(0n)/(0μ) t START = ms V IN V OUT -4V V V GATE V L t START V IN V OUT V V V GATE GS(th) V GS(lim) V GATE t TH This time interval is associated with the rise of the GATE voltage from zero to the gate threshold voltage of the external MOSFET t TH I = V GS(TH) C t TH = ()(0n)/(0μ) t START = 0ms V EE The figure shows the sequence of events during startup and associated timing characteristics The following is a discussion of timing values assuming the following component values: I IN inactive active t RISE t TH t POR 90% C = 0nF = 00μF V = 4V MOSFET = IRF0 V GS(TH) = 0V g m = 74S R CS = 0mΩ (I MAX = 0A) t LIM I LIM t Initialization Limiting Full On t RISE During this time period the drain current rises more or less exponentially to the maximum inrush current I MAX As current rises from zero, the current is reduced by the action of the current sense amplifier, hence the more or less exponential current rise t RISE is here defined as the time to reach 90% of I MAX 90% rise corresponds to τ I τ = C ΔV GS I MAX g m ΔV GS t RISE (C I MAX ) / (I g m ) t RISE ()(0n)()/(0μ)(74) = 0ms t LIM During this time period the external load capacitor is charged at I MAX I MAX t LIM = V t LIM = (00μ)(4) / () t LIM = 4ms t Final rise of GATE voltage to V REG minus about V I t = C (V REG (V + V GS(TH) + ΔV GS )) t = (0n)(0 ( + + /74)/(0μ) t = 4ms Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Startup Timer The startup timer limits the startup to 00ms Should there be an overload or short circuit during startup, then the external pass transistor will carry current for no more than 00ms Upon tripping of the timer the and GATE voltages reset to zero, and the autoretry timer starts if enabled Circuit Breaker The circuit breaker trips in less than 0μs when the voltage across the sense resistor reaches 00mV Upon tripping of the circuit breaker the and GATE voltages reset to zero, and the autoretry timer starts if enabled Autoretry Timer The retry interval is determined by charging and discharging the C capacitor times One cycle corresponds to charging of C to 0V with a current of μa, and subsequent discharging to zero with a current of μa Hence: I CHARGE t CYCLE = C ΔV t CYCLE = (0n)()()/(μ) t CYCLE = 4ms t AUTORETRY = ()(4m) t AUTORETRY = 4s The autoretry timer can be disabled by adding a resistor at the pin A resistor which keeps the voltage from rising to 0V will keep the timer from counting This can accomplished by adding a resistor at the pin with a value of about MΩ Note that this resistor forms an additional load during the startup, thereby causing the time intervals to increase somewhat Kelvin Connections In order to make an accurate measurement of power supply current it is advisable to make use of Kelvin connections The idea is to not incur voltage drops in the sense leads due to the main power supply current See diagram below To Negative Terminal of Power Source To V EE To SENSE Sense Resistor To Source of MOSFET Paralleling External MOSFETs Equal current sharing may not be achievable due to the tolerance issues with the threshold voltage and gain characteristics of the MOSFETs Paralleling of devices is not recommended The issues with paralleling can be alleviated by using resistor ballasting For this application the with active low is recommended where the pins of multiple hot swap circuits can be connected in a wired OR configuration Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom 7
Application Circuit Output Many converters reference their inputs to the negative input terminal If the input is active LOW then the can be directly connected as shown below (Application Circuit ) since the open drain output is in a High-Z state until the external MOSFET is fully turned on and the potential on the negative input of the converter is essentially the same as the VEE pin of the R 47kΩ kω R 97kΩ VEE SENSE 7 C 4 0nF GATE + - +0V -4V mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Application Circuit However, if the Converter with the input circuit configuration was active HIGH, then the apparent choice of the would result in the creation of a current path through the protective diode clamp of the input and the output MOSFET of the For this situation the should be used as shown below R 47kΩ kω R 97kΩ -4V C 0nF 7 4 VEE SENSE GATE Cload + - +0V mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Application Circuit In some applications the signal is used to activate load circuitry on the isolated output side of the Converter In this situation an optocoupler is needed to provide the required isolation as shown below Optocoupler R LOAD R 47kΩ kω R 97kΩ -4V A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO +V 7 C 4 0nF mw Q IRF0 Application Circuit 4 When the details of the load circuitry is not known, using an optocoupler always provides a safe solution Optocoupler R 47kΩ kω R 97kΩ -4V +0V 7 C 4 0nF 0mΩ Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom 9
Application Circuit Filtering Voltage Spikes on Input Supply In some systems over voltage spikes of very short duration may exist For these systems a small capacitor may be added from the pin to the VEE pin to filter the voltage spikes R 47kΩ -4V kω R 97kΩ C 7 C 4 0nF +0V mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Application Circuit Unfortunately this will also cause some delay in responding to conditions If this delay is not acceptable, then separate resistor dividers can be provided for and with a capacitor connected from pin to the VEE pin R 47kΩ kω -4V R kω 0kΩ C 7 4 C 0nF +0V R mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom 0
Application Circuit 7 Using Short Connector In some systems short connector pins are used to guarantee that the power pins are fully mated before the hot swap control circuit is enabled For these systems the positive () end of the R,, and R resistor divider should be connected to -4V Long Short R 47kΩ kω R 97kΩ Long mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO C 0nF 7 4 +0V Application Circuit If separate resistor dividers are used for and, then only the positive () end of the resistor divider should be connected to the short pin R 47KΩ -4V Long Short KΩ Long R KΩ 0KΩ R mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO C 0nF 7 4 +0V Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Application Circuit 9 If a system requires the use of a short connector pin on the negative supply lead to guarantee that the power pins are fully mated before the hot swap control circuit is enabled and uses separate resistor dividers for and, then a to 0V Zener diode must be connected from the pin to the VEE pin and only the divider should be connected to the short pin Long R 47kΩ kω R 97kΩ A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO -4V Short 7 4 V C -4V Long 0nF mω Q IRF0 +0V Application Circuit 0 If a system requires the use of a short connector pin on the negative supply lead to guarantee that the power pins are fully mated before the hot swap control circuit is enabled and uses separate resistor dividers for and, then a V to 0V zener diode must be connected from the pin to the VEE pin and only the divider should be connected to the short pin Long R 47kΩ R kω -4V kω 0kΩ Short -4V V Long 7 4 C 0nF R mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO +0V Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Application Circuit Increasing Under Voltage Hysteresis If the internally fixed under voltage hysteresis is insufficient for a particular system application, then it may be increased by using separate resistor dividers for and and providing a resistor feedback path from the GATE pin to the pin R 47kΩ kω -4V R kω 0kΩ R 7 4 C 0nF A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO R mω Q IRF0 +V Application Circuit Reverse Polarity Protection The and pins are protected against reverse polarity input supplies by internal clamping diodes and the fault currents are sufficiently limited by the impedance of the external resistor divider, however, a low current diode with a 00V breakdown rating must be inserted in series with the pin This method (shown in Application Circuit ) will protect the hot swap control circuit however, due to the intrinsic diode in the external MOSFET, the load will not be protected from reverse polarity voltages R 47kΩ D kω +V -4V R 97kΩ C 0nF 7 4 mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Application Circuit Redundant Supplies Many systems use redundant primary power supplies or battery backup When redundant AC powered sources are used they are generally diode OR ed to the load on the hot terminal For these systems, the use of independent hot swap controllers is recommended with the diode OR ing provided after the hot swap controllers The is ideally suited for such applications since two or more active low signals can be connected to a single active low pin, thus enabling the load as long as at least one primary power source is available By adding low current 00V diodes in series with the pins, full reverse polarity protection on either power source is also provided R 47kΩ D PS kω R 97kΩ -4V 7 4 C 0nF D 0mΩ Q IRF0 R 47kΩ D PS kω +V R 97kΩ 7 4-4V C 0nF D 0mΩ Q IRF0 NOTES: Undervoltage Shutdown () set to V Overvoltage Shutdown () set to V Current Limit set to 0A A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom 4
Application Circuit 4 Use with Negative Ground The may be used with many positive ground systems where converters have isolated outputs and their inputs need not be ground referenced +4V R 47kΩ kω R 97kΩ C 0nF 7 4 +V mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Application Circuit Extending Circuit Breaker Delay Connecting a resistor in series with the SENSE pin and a capacitor between the SENSE and VEE pins as shown in the following diagram may be used to extend the circuit breaker delay time beyond the µs internally set delay time The time delay achievable by this method is limited since this Application Circuit 7 delay circuit will also effect the current control feedback loop and will result in a current overshoot during the external pass device turn on transition to current limit If the time delay required for the circuit breaker causes excessive current overshoot during the turn on transition then the following circuit may be used, where the RC filter is switched on after the completion of the current limit control function of the hot swap controller -4V R 47kΩ kω R 97kΩ +V 7 4 C R mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
Application Circuit Latched Operations For those applications that need to disable the auto retry capability, the following circuit disables the auto retry feature -4V R 47kΩ kω R 97kΩ +V 4 7 MΩ mω Q IRF0 A capacitor may be needed to slow dv/dt if gate oscillations are observed when V IN is close to LO Description # Name Description The power good output pin is an open-drain output Connect to power module enable pins and the like with internal or external pull-up resistor(s) This open-drain pin is high impedance during the start-up phase, during fault, and automatic retry periods, and low otherwise The overvoltage input pin Input to the / window comparator Monitors the power supply voltage, for purpose of detecting the normal operating voltage condition The undervoltage input pin Input to the / window comparator Monitors the power supply voltage, for purpose of detecting the normal operating voltage condition 4 VEE The negative power supply pin Connect to the negative of the incoming power supply SENSE The current sense pin Connect the current sense resistor between the VEE and SENSE pins Regulates the Inrush current to 0mV equivalent Trips on over current at 00mV equivalent GATE The gate output Connect to the gate of external MOSFET Connect the source of the MOSFET source to the VEE pin 7 The input pin Connect a capacitor between this pin and VEE to control the ramp rate of the voltage at the GATE pin during power-up Add a resistor of about MΩ to disable the autoretry feature The positive power supply pin Connect to the positive of the incoming power supply Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom
A -Lead SOIC (Narrow Body) Package Outline (LG) 490x90mm body, 7mm height (max), 7mm pitch D θ E Note (Index Area D/ x E/) E L Gauge Plane L L θ Seating Plane A A Top View Seating Plane A Note h h View B View B A e b Side View View A-A This chamfer feature is optional A identifier must be located in the index area indicated The identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator Dimension (mm) Symbol A A A b D E E e h L L L θ θ MIN * 00 0 40* 0* 0* 0 040 0 O O 7 04 0 NOM - - - - 490 00 90 - - - - BSC REF BSC MAX 7 0 * 0 00* 0* 400* 00 7 O O JEDEC Registration MS-0, Variation AA, Issue E, Sept 00 * This dimension is not specified in the original JEDEC drawing The value listed is for reference only Drawings are not to scale Supertex Doc #: DSPD-SOLGTG, Version H070 (The package drawings in this data sheet may not reflect the most current specifications For the latest package outline information go to http://wwwsupertexcom/packaginghtml) Supertex inc does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement Supertex inc does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship No responsibility is assumed for possible omissions and inaccuracies Circuitry and specifications are subject to change without notice For the latest product specifications refer to the Supertex inc website: http//wwwsupertexcom 00 All rights reserved Unauthorized use or reproduction is prohibited Doc# DSFP- A00 7 Bordeaux Drive, Sunnyvale, CA 9409 Tel: 40-- wwwsupertexcom