TN264 Features Low threshold (2.V max.) High input impedance Low input capacitance Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage pplications Logic level interfaces - ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives nalog switches General purpose line drivers Telecom switches N-Channel Enhancement-Mode Vertical DMOS FETs General Description This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Supertex s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Ordering Information Part Number Package Option Packing TN264K4-G TO-252 (D-PK) 2/Reel TN264LG-G 8-Lead SOIC 25/Reel TN264N3-G 3-Lead 1/Bag TN264N3-G P2 TN264N3-G P3 TN264N3-G P5 TN264N3-G P13 TN264N3-G P15 3-Lead 2/Reel For packaged products, -G indicates package is RoHS compliant ( Green ). taping specifications and winding styles per EI-468 Standard. Devices in Wafer / Die form are RoHS compliant ( Green ). Refer to Die Specification VF57 for layout and dimensions. bsolute Maximum Ratings Parameter Drain-to-source voltage Drain-to-gate voltage Value BS BV DGS Gate-to-source voltage ±2V Operating and storage temperature -55 C to +15 C bsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. ll voltages are referenced to device ground. Product Summary BS /BV DGS Pin Configuration SOURCE GTE (max) TO-252 (D-PK) SOURCE (ON) (min) GTE 8-Lead SOIC (th) (max) 4V 5.Ω 2. 2.V Typical Thermal Resistance Package TO-252 (D-PK) 8-Lead SOIC θ ja 81 O C/W 11 O C/W 132 O C/W GTE SOURCE N/C N/C
Product Marking TN264 Si YYWW TN264 LLLLLLL YY = Year Sealed WW = Week Sealed L = Lot Number = Green Packaging YYWW N264 LLLL YY = Year Sealed WW = Week Sealed L = Lot Number = Green Packaging Package may or may not include the following marks: Si or TO-252 (D-PK) Package may or may not include the following marks: Si or 8-Lead SOIC SiTN 264 YYWW YY = Year Sealed WW = Week Sealed = Green Packaging Thermal Characteristics Package may or may not include the following marks: Si or Package Power Dissipation (continuous) (pulsed) @T = 25 O C R RM TO-252 (D-PK) 5m 3. 2.5W 5m 3. 8-Lead SOIC 26m 2. 1.3W 26m 2. 22m 2..74W 22m 2. Notes: (continuous) is limited by max rated T j. Mounted on FR4 board, 25mm x 25mm x 1.57mm Electrical Characteristics (T = 25 C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage 4 - - V = V, = 1.m (th) Gate threshold voltage.8-2. V =, = 2.m Δ(th) Change in (th) with temperature - -2.5-4. mv/ O C =, = 2.m I GSS Gate body leakage - 1 n = ±2V, = V SS (ON) Zero gate voltage drain current On-state drain current Static drain-to-source on-state resistance - - 1 µ = V, = Max rating - - 1. m =.8 Max Rating, = V, T = 125 O C 1.5 3.5 - = 5.V, = 25V 2. 4. - = 1V, = 25V - 3.2 5. = 4.5V, = 5m Ω - 3. 5. = 1V, = 5m Δ Change in with temperature - -.75 %/ O C = 1V, = 5m G FS Forward transconductance 2 33 - mmho = 25V, = 1m C ISS Input capacitance - 21 225 C OSS Common source output capacitance - 3 5 C RSS Reverse transfer capacitance - 8. 15 pf = V, = 25V, f = 1.MHz 2
TN264 Electrical Characteristics (T = 25 C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions t d(on) Turn-on delay time - 4. 15 t r Rise time - 15 2 t d(off) Turn-off delay time - 2 25 t f Fall time - 22 27 ns V DD = 25V, = 2., R GEN = 25Ω V SD Diode forward voltage drop - -.9 V = V, I SD = 2m t rr Reverse recovery time - 3 - ns = V, I SD = 1. Notes: 1. ll D.C. parameters 1% tested at 25 O C unless otherwise stated. (Pulse test: 3µs pulse, 2% duty cycle.) 2. ll.c. parameters sample tested. N- Channel Switching Waveforms and Test Circuit 1V 9% VDD INPUT V 1% Pulse Generator R L OUTPUT t (ON) t (OFF) R GEN t d(on) t r t d(off) t f VDD OUTPUT 1% 1% INPUT D.U.T. V 9% 9% 3
TN264 Typical Performance Curves 1.15 BS Variation with Temperature 1 On-Resistance vs. Drain Current = 5.V 1.1 8 BS (normalized) 1.5 1. (ohms) 6 4 = 1V.95 2.9-5 5 1 15 T j ( O C) 1. 2. 3. 4. 5. 3. 2.4 Transfer Characteristics 25 O C V (th) and R DS Variation with Temperature 1.4 2.2 V (th) @ 2.m 1.2 1.8 1.8 1.2 T = -55 O C 125 O C = -25V (th) (normalized) 1..8 1.4-1. (normalized).6.6 @ 1V,.5.6 2 4 6 8 1.4-5 5 1.2 15 T j ( O C) Capacitance vs. Drain-to-Source Voltage 4 1 Gate Drive Dynamic Characteristics 3 f = 1MHz 8 C (picofarads) 653pF 6 2 = 1V 4 C ISS = 4V 1 2 C OSS 253pF C RSS 1 2 3 4 1 2 3 4 5 Q G (nanocoulombs) 4
TN264 Typical Performance Curves (cont.) 5. 4. Output Characteristics 2.5 2. Saturation Characteristics = 1V 8V 6V 4V 3. 2. = 1V 8V 6V 4V 1.5 1. 3V 1. 1 2 3 4 5 3V 2V.5 2 4 6 8 1 2V 2. 1.6 Transconductance vs. Drain Current = 25V 3. 2.4 Power Dissipation vs. Temperature DPK G FS (siemens) 1.2.8 T = -55 O C P D (watts) 1.8 1.2 SO-8.4 25 O C.6 125 O C 1. 2. 3. 4. 5. 25 5 75 1 125 15 T C ( O C) 1 Maximum Rated Safe Operating rea 1. Thermal Response Characteristics 1..1.1 DPK (DC) (DC) SO-8 (DC) T C = 25 O C SO-8 (pulsed) (pulsed) Thermal Resistance (normalized).8.6.4.2 P D = 1W T C = 25 O C.1 1. 1 1 5.1.1.1 1. 1 t P (seconds)
3-Lead TO-252 D-PK Package Outline (K4) TN264 E b3 E1 c2 4 L3 θ1 D1 H D 1 2 3 L4 L5 Note 1 b2 e b View B Front View Rear View Side View L2 Gauge 1 Seating θ L L1 View B Note: 1. lthough 4 terminal locations are shown, only 3 are functional. Lead number 2 was removed. Dimension (inches) Symbol 1 b b2 b3 c2 D D1 E E1 e H L L1 L2 L3 L4 L5 θ θ1 MIN.86.*.25.3.195.18.235.25.25.17.37.55.35.25*.45 O O.9.18.2 NOM - - - - - -.24 - - - -.6 - - - - - BSC REF BSC MX.94.5.35.45.215.35.245.217*.265.182*.41.7.5.4.6 1 O 15 O JEDEC Registration TO-252, Variation, Issue E, June 24. * This dimension is not specified in the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-3TO252K4, Version E4139. 6
8-Lead SOIC (Narrow Body) Package Outline (LG) 4.9x3.9mm body, 1.75mm height (max), 1.27mm pitch TN264 D θ1 8 Note 1 (Index rea D/2 x E1/2) E1 E L2 Gauge 1 L L1 Seating Top View 2 1 e b Seating Side View θ View B View B Note 1 h h View - Note: 1. This chamfer feature is optional. Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Dimension (mm) Symbol 1 2 b D E E1 e h L L1 L2 θ θ1 MIN 1.35*.1 1.25.31 4.8* 5.8* 3.8*.25.4 O 5 O 1.27 1.4.25 NOM - - - - 4.9 6. 3.9 - - - - BSC REF BSC MX 1.75.25 1.65*.51 5.* 6.2* 4.*.5 1.27 8 O 15 O JEDEC Registration MS-12, Variation, Issue E, Sept. 25. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version I4139. 7
3-Lead Package Outline (N3) TN264 D Seating 1 2 3 L e1 e Front View b c Side View E1 1 3 E 2 Bottom View Dimensions (inches) Symbol b c D E E1 e e1 L MIN.17.14.14.175.125.8.95.45.5 NOM - - - - - - - - - MX.21.22.22.25.165.15.15.55.61* JEDEC Registration. * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E419. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http:///packaging.html.) does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 213 ll rights reserved. Unauthorized use or reproduction is prohibited. 8 1235 Bordeaux Drive, Sunnyvale, C 9489 Tel: 48-222-8888