Miniaturization and future prospects of Si devices

Miniaturization and future prospects of Si devices G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices: Prospects by World s Leading Scientists October 4, 2011 Hiroshi Iwai, Tokyo Institute of Technology 1

First Computer Eniac: made of huge number of vacuum tubes 1946 Big size, huge power, short life time filament dreamed of replacing vacuum tube with solid state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption 2

Mechanism of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) G Surface Gate electrode Gate Oxd Source Channel Drain S D Electron flow 0 bias for gate Positive bias for gate Surface Potential (Negative direction) 0V Negative N + -Si P-Si 1V N-Si Source Channel Drain 0V N + -Si P-Si 1V N-Si Source Channel Drain

1960: First MOSFET by D. Kahng and M. Atalla Top View Si Source Al Gate Al Drain Si SiO 2 Si Si/SiO2 Interface is exceptionally good 4

1970,71: 1st generation of LSIs 1kbit DRAM Intel 1103 4bit MPU Intel 4004 5

2011 Most recent SD Card 6

Most Recent SD Card 128GB (Bite) = 128G X 8bit = 1024Gbit = 1.024T(Tera)bit 1T = 10 12 = Trillion Brain Cell 10 100 Billion World Population 6 Billion Stars in Galaxy 100 Billion 7

Most Recent SD Card 8

2.4cm X 3.2cm X 0.21cm Volume 1. 6cm³ Weight 2g Voltage 2.7-3.6V Old Vacuum Tube 5cm X 5cm X 10cm, 100g,100W 1Tbit = 10k X10k X 10k bit Volume = 0.5km X 0.5km X 1km = 0.25 km 3 = 0.25X10 12 cm 3 Weight = 0.1 kgx10 12 = 0.1X10 9 ton = 100 M ton Power = 0.1kWX10 12 =50 TW Supply Capability of Tokyo Electric Power Company: 55 BW 9

So, progress of IC technology is most important for the power saving!

Downsizing of the components has been the driving force for circuit evolution 1900 1950 1960 1970 2000 Vacuum Transistor IC LSI ULSI Tube 10 cm cm mm 10 µm 100 nm 10-1 m 10-2 m 10-3 m 10-5 m 10-7 m In 100 years, the size reduced by one million times. There have been many devices from stone age. We have never experienced such a tremendous reduction of devices in human history. 11

Downsizing 1. Reduce Capacitance Reduce switching time of MOSFETs Increase clock frequency Increase circuit operation speed 2. Increase number of Transistors Parallel processing Increase circuit operation speed Downsizing contribute to the performance increase in double ways Thus, downsizing of Si devices is the most important and critical issue. 12

Many people wanted to say about the limit. Past predictions were not correct!! Period Expected Cause limit(size) Late 1970 s 1µm: SCE Early 1980 s 0.5µm: S/D resistance Early 1980 s 0.25µm: Direct tunneling of gate SiO 2 Late 1980 s 0.1µm: 0.1µm brick wall (various) 2000 50nm: Red brick wall (various) 2000 10nm: Fundamental? 13

14 Qi Xinag, ECS 2004, AMD

5 nm gate length CMOS Is a Real Nano Device!! 5nm Length of 18 Si atoms H. Wakabayashi et.al, NEC IEDM, 2003 15

Surface Source Gate electrode Gate Oxd Channel Drain 0 bias for gate Surface Potential (Negative direction) 0V Negative N + -Si P-Si 3nm 1V N-Si Source Channel Drain Tunneling @Vg=0V, Transistor cannot be switched off 16

Prediction now! Limitation for MOSFET operation Tunneling distance 3 nm Lg = Sub 3 nm? Below this, no one knows future! 17

Prediction now! Limitation for MOSFET operation Tunneling distance 3 nm Lg = Sub 3 nm? Ultimate limitation Atom distance 0.3 nm Below this, no one knows future! No one can make a MOSET below this size! 18

Question: How far we can go with downscaling?

How far can we go for production? Past 1970 0.7 times per 3 years In 40 years: 18 generations, Size 1/300, Area 1/100,000 Now 10µm 8µm 6µm 4µm 3µm 2µm 1.2µm 0.8µm 0.5µm 0.35µm 0.25µm 180nm 130nm 90nm 65nm 45nm 32nm Future (28nm) 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm? At least 4,5 generations to 8nm Hopefully 8 generations to 3nm

Subtheshold leakage current of MOSFET Id Ion OFF ON Subthreshould Leakage Current Vg=0V Ioff Subthreshold region Vg Vth (Threshold Voltage) 21

Vth cannot be decreased anymore Log scale Id plot Ion significant Ioff increase Ioff Vth: 300mV 100mV Ioff increases with 3.3 decades (300 100)mV/(60mv/dec) = 3.3 dec Ioff Log Id per unit gate width (= 1µm) Subthreshold slope (SS) = (Ln10)(kT/q)(C ox +C D +C it )/C ox > ~ 60 mv/decade at RT 10-3 A 10-4 A 10-5 A 10-6 A 10-7 A 10-8 A 10-9 A 10-10 A Vg = 0V Vdd down-scaling Vdd=0.5V Vth down-scaling Vth = 300mV Vth = 100mV SS value: Constant and does not become small with down-scaling Vdd=1.5V Vg (V) 22 22

Subtheshold leakage current of MOSFET Id Ion Subthreshold Current Is OK at Single Tr. level Subthreshould Leakage Current OFF ON But not OK For Billions of Trs. Ioff Vg Vg=0V Subthreshold region Vth (Threshold Voltage) 23

The limit is deferent depending on application 100 e) Operation Frequency (a.u.) 10 1 Subthreshold Leakage (A/µm) Source: 2007 ITRS Winter Public Conf. 24

Scaling Method: by R. Dennard in 1974 1 S 1 Wdep 1 1 D Wdep: Space Charge Region (or Depletion Region) Width Wdep has to be suppressed Otherwise, large leakage between S and D I Leakage current K=0.7 for example K K Wdep Potential in space charge region is high, and thus, electrons in source are attracted to the space charge region. X, Y, Z : K, V : K, Na : 1/K K Wdep V/Na : K I K 0 0 K V 0 0 V 1 By the scaling, Wdep is suppressed in proportion, and thus, leakage can be suppressed. Good scaled I-V characteristics I : K 25 25

Down scaling is the most effective way of Power saving. The down scaling of MOSFETs is still possible for another 10 years! 3 important technological items for DS. New materials 1. Thinning of high-k beyond 0.5 nm 2. Metal S/D New structures 3. Wire channel

1. High-k beyond 0.5 nm

0.8 nm Gate Oxide Thickness MOSFETs operates!! 0.8 nm: Distance of 3 Si atoms!! 28 By Robert Chau, IWGI 2003

There is a solution! K: Dielectric Constant To use high k dielectrics Thin gate SiO 2 Thick gate high k dielectrics Thick K=4 Almost the same electric characteristics K=20 Small leakage Current However, very difficult and big challenge! Remember MOSFET had not been realized without Si/SiO 2! 29

Choice of High-k elements for oxide Gas or liquid at 1000 K Radio active He B C N O F Ne Unstable at Si interface H Si + MO X M + SiO 2 Li Be Si + MO X MSi X + SiO 2 Na Mg Si + MO X M + MSi X O Y Al Si P S Cl Ar Ca K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe Cs Ba Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn Fr Ra Rf Ha Sg Ns Hs Mt Candidates La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Y Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr R. Hauser, IEDM Short Course, 1999 Hubbard and Schlom, J Mater Res 11 2757 (1996) HfO 2 based dielectrics are selected as the first generation materials, because of their merit in 1) band-offset, 2) dielectric constant 3) thermal stability La 2 O 3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer 30

Conduction band offset vs. Dielectric Constant Leakage Current by Tunneling Band offset Si Oxide SiO 2 Band Discontinuity [ev] 4 2 0-2 -4-6 0 10 20 30 40 50 Dielectric Constant XPS measurement by Prof. T. Hattori, INFOS 2003 31

High k gate insulator MOSFETs for Intel: EOT=1nm HfO 2 based high k PMOS 32

Power per MOSFET (P) (Scaling) P L g 3 For the past 45 years SiO2 and SiON For gate insulator Today EOT=1.0nm EOT Limit 0.7~0.8 nm One order of Magnitude 45nm node EOT=0.5nm Metal SiO 2 /SiON Si Metal HfO 2 SiO 2 /SiON Si 0.5 0.7nm Introduction of High-k Still SiO2 or SiON Is used at Si interface Metal High-k Si Direct Contact Of high-k and Si EOT can be reduced further beyond 0.5 nm by using direct contact to Si By choosing appropriate materials and processes. Now Year 33

Cluster tool for high-k thin film deposition Preparation Room Sputter for metal 5 different target Robot room E-Beam Evaporation 8 different target Flash Lamp Anneal Micro to mille-seconds

SiO x -IL growth at HfO 2 /Si Interface TEM image 500 o C 30min Intensity (a.u) 1846 500 o C Hf Silicate SiO 2 Si sub. 1843 1840 Binding energy (ev) Phase separator XPS Si1s spectrum 1837 1 nm W HfO 2 SiO x -IL k=16 k=4 HfO 2 + Si + O 2 HfO 2 + Si + 2O* HfO 2 +SiO 2 SiO x -IL is formed after annealing H. Shimizu, JJAP, 44, pp. 6131 Oxygen supplied from W gate electrode D.J.Lichtenwalner, Tans. ECS 11, 319 Oxygen control is required for optimizing the reaction 35

La-Silicate Reaction at La 2 O 3 /Si Direct contact high-k/si is possible Intensity (a.u) as depo. 300 o C 500 o C XPS Si1s spectra La-silicate Si sub. TEM image 500 o C, 30 min 1 nm W La 2 O 3 La-silicate k=23 k=8~14 1846 1843 1840 Binding energy (ev) 1837 La 2 O 3 + Si + no 2 La 2 SiO 5, La 2 Si 2 O 7, La 9.33 Si 6 O 26, La 10 (SiO 4 ) 6 O 3, etc. La 2 O 3 can achieve direct contact of high-k/si 36

Current density ( A/cm 2 ) Gate Leakage vs EOT, (Vg= 1 V) Al2O3 1.E+01 HfAlO(N) HfO2 HfO2 1.E+00 HfSiO(N) HfTaO La2O3 La2O3 1.E-01 Nd2O3 Pr2O3 1.E-02 PrSiO PrTiO 1.E-03 SiON/SiN Sm2O3 1.E-04 SrTiO3 Ta2O5 TiO2 1.E-05 ZrO2(N) 0 0.5 1 1.5 2 2.5 3 ZrSiO EOT ( nm ) ZrAlO(N) 37

La 2 O 3 at 300 o C process make sub-0.4 nm EOT MOSFET EOT=0.37nm EOT=0.37nm EOT=0.40nm EOT=0.48nm I d (V) 3.5E-03 3.0E-03 2.5E-03 2.0E-03 1.5E-03 Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V W/L = 50µm /2.5µm Vth=-0.06V Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V W/L = 50µm /2.5µm Vth=-0.05V Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V W/L = 50µm /2.5µm Vth=-0.04V 1.0E-03 5.0E-04 0.0E+00 0 0.2 0.4 0.6 0.8 10 0.2 0.4 0.6 0.8 10 0.2 0.4 0.6 0.8 1 V d (V) V d (V) V d (V) 0.48 0.37nm Increase of Id at 30% 38

Capacitance [µf/cm 2 ] However, high-temperature anneal is necessary for the good interfacial property FGA500 o C 30min FGA700 o C 30min FGA800 o C 30min 2 1.5 1 0.5 20 x 20µm 2 1.5 10kHz 100kHz 1MHz Capacitance [µf/cm 2 ] 1 0.5 20 x 20µm 2 10kHz 100kHz 1MHz Capacitance [µf/cm 2 ] 2 1.5 1 0.5 20 x 20µm 2 10kHz 100kHz 1MHz 0-1 -0.5 0 0.5 1 Gate Voltage [V] 0-1.5-1 -0.5 0 0.5 Gate Voltage [V] 0-1.5-1 -0.5 0 0.5 Gate Voltage [V] A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800 o C) 39

Charge pumping current [A] 10-6 10-7 10-8 10-9 D it = 2 x 10 12 [cm -2 /ev] 500 o C 700 o C 800 o C Pulse input D it = 5 x 10 11 [cm -2 /ev] D it = 1.6 x 10 11 [cm -2 /ev] 10 4 10 5 10 6 Frequency [Hz] Electron Mobility [cm 2 /Vsec] 500 400 300 200 100 0 0 FGA 800 o C FGA 700 o C FGA 500 o C 0.2 0.4 0.6 E eff [MV/cm] Universal EOT~1.3nm T = 300K N sub = 3 x 10 16 cm -3 0.8 1 A small D it of 1.6x10 11 cm -2 /ev, results in better electron mobility. 40

Physical mechanisms for small Dit silicate-reaction-formed fresh interface stress relaxation at interface by glass type structure of La silicate. metal La 2 O 3 Si Si sub. Si metal La-silicate Si sub. La atom La-O-Si bonding Si sub. SiO 4 tetrahedron network Fresh interface with silicate reaction FGA800 o C is necessary to reduce the interfacial stress J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p. 102908 S. D. Kosowsky, et al., Appl. Phys. 41Lett., Vol. 70, No. 23, (1997) pp. 3119

EOT growth suppression by Si coverage Si Gate-Channel Capacitance [µf/cm 2 ] 4 EOT=0.71nm FGA 800 o C 30min 3 L / W = 20 / 20µm EOT=1.02nm 2 EOT=1.63nm 1 at 1MHz 0-1 -0.5 0 0.5 1 Gate Voltage [V] TiN W La-silicate Si sub. TiN W La-silicate Si sub. W La-silicate Si sub. Drain Current [A] 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 V ds = 0.05V 65~70mV/dec EOT = 0.71nm EOT = 1.02nm EOT = 1.63nm L / W = 2.5 / 50µm -1-0.5 0 0.5 1 V g - V th [V] Increasing EOT caused by high temperature annealing can be dramatically suppressed by Silicon masked stacks 42

La2O3 W TiN/W Si/TiN/W MIPS MG HK Si 2nm 2nm 2nm K av ~ 8 K av ~ 12 K av ~ 16 No interfacial layer can be confirmed with Si/TiN/W 43

nmosfet with EOT of 0.62nm Gate-Channel Capacitance [µf/cm 2 ] 4 3 2 1 0 FGA 800 o C 30min L / W = 10 / 10µm -0.5 10kHz 100kHz 1MHz 0 0.5 Gate Voltage [V] EOT=0.62nm No frequency dispersion 1 Electron Mobility [cm 2 /Vsec] 200 150 100 50 0 0 EOT=0.62nm T = 300K N sub = 3 x 10 16 cm -3 L / W = 10 / 10µm 0.5 1 E eff [MV/cm] 1.5 EOT of 0.62nm and 155 cm 2 /Vsec at 1MV/cm can be achieved 44

J g at V g = 1V [A/cm 2 ] 10 4 10 3 10 2 10 1 10 0 10-1 10-2 Benchmark of La-silicate dielectrics 0.5 MIPS Stacks 0.55 ITRS requirements 0.6 0.65 0.7 EOT [nm] A = 10 x 10µm 2 0.75 Gate leakage is two orders of magnitude lower than that of ITRS 0.8 Electron Mobility [cm 2 /Vsec] 300 250 200 150 100 50 0 0.5 This work (MIPS Stacks) 0.6 0.7 0.8 0.9 1 EOT [nm] T. Ando et al., IEDM2009 at 1MV/cm T = 300K Open : Hf-based oxides 1.1 1.2 1.3 Electron mobility is comparable to record mobility with Hf-based oxides 45

Metal (Silicide) S/D

Extreme scaling in MOSFET L phy - Dopant abruptness at S/D -V t and I ON variation - GIDL Dopant Conc. n + -Si δ σ Gate δ σ n + -Si Metal Schottky S/D junctions S Channel D - Atomically abrupt junction - Lowering S/D resistances - Low temperature process for S/D Metal Conc. Metal Silicide L phy = L eff Gate Metal Silicide Schottky Barrier FET is a strong candidate for extremely scaled MOSFET S Channel D

Surface or interface control Diffusion species: metal atom (Ni, Co) Rough interface at silicide/si - Excess silicide formation - Different φ Bn presented at interface - Process temperature dependent composition Diffusion species: Si atom (Ti) Surface roughness increases - Line dependent resistivity change Annealing: 650 o C Si(001) sub. Epitaxial NiSi 2 O. Nakatsuka et al., Microelectron. Eng., 83, 2272 (2006). Top view Line width of 0.1 µm H. Iwai et al., Microelectron. Eng., 60, 157 (2002). 48

Unwanted leakage current - Edge leakage current at periphery - Generation current due to defects in substrate Variable leakage current in smaller contact Specification for metal silicide S/D Annealing: 500 o C 10 10 2 Length of a contact side (µm) - Atomically flat interface with smooth surface - Suppressed leakage current - Stability of silicide phase and interface in a wide process temperature Current density (A/cm 2 ) 10-2 10-3 V app = -0.2V φ Bn = ~0.57 ev Ni silicide/si diodes 49

Deposition of Ni film Si substrate Annealing Ni-silicide Si substrate Rough interface Deposition from NiSi 2 source Si substrate Annealing Ni-silicide Si substrate No Si substrate consumption Flat interface Deposition of Ni-Si mixed films from NiSi 2 source - No consumption of Si atoms from substrate - No structural size effect in silicidation process - Stable in a wide process temperature range 50

- n-type Si substrate, Si(100) with 400 nm SiO 2 isolation Doping concentration : 3x10 15 cm -3 SPM and HF cleaning Ni source Diode patterning by photolithography and BHF etching of SiO 2 Deposition of 10-nm-thick NiSi 2 and Ni sources by RF sputtering in Ar atmosphere Ni silicidation by Rapid Thermal Annealing (RTA) in N 2 atmosphere Al contact deposition on substrate backside by thermal evaporation - Measurement of electrical characteristics - SEM and TEM observation - XRD and XPS analysis Si substrate Al contact SiO 2 NiSi 2 source Si substrate Al contact Schottky diode structures 51

SEM views of silicide/si interfaces Ni source (50nm) NiSi 2 source (50nm) Ni source NiSi 2 source Ni-silicide Ni-silicide STI rough 500nm STI 600 o C, 1min flat 500nm Si substrate Ni source STI Si substrate STI rough 500nm STI 700 o C, 1min flat 500nm - Rough interfaces - Consumed Si substrate - Thickness increase ~100 nm NiSi 2 source STI rough 500nm STI 800 o C, 1min flat 500nm - Atomically flat interfaces - No Si consumption - Temperature-independent 52

Ni source Si substrate Al contact NiSi 2 source Si substrate Al contact Schottky diode structures NiSi 2 source Current Diode current density (A/cm 2 2 ) ) 10-2 10-3 10-4 10-5 RTA 500 o C, 1min Source φ Bn (ev) n Ni 0.676 1.08 NiSi 2 0.659 1.00 Ni Generation Leakage current current NiSi 2-0.8-0.6-0.4-0.2 0.0 0.2 Applied Voltage (V) Diode voltage (V) Ideal characteristics (n = 1.00, suppressed leakage current) Suppressed reverse leakage current - Flat interface and No Si substrate consumption - No defects in Si substrate 53

as-deposited Ni source Ni-silicide Ni-rich 300 o C 550 o C 800 o C Agglomeration NiSi NiSi NiSi 2 Si substrate Si substrate Si substrate Si substrate Si substrate NiSi 2 source amorphous Ni-rich+a-NiSi 2 Ni-rich+a-NiSi 2 Ni-rich+a-NiSi 2 NiSi 2 NiSi 2 NiSi 2 NiSi 2 Si substrate Si substrate Si substrate Si substrate Si substrate - Ni-rich phases in the silicide layer are maintained with NiSi 2 source - No distinct structure change at the interface Stable φ Bn and n-factor No structural effect for silicidation 54

Wire channel

Suppression of subthreshold leakage by surrounding gate structure 0V 0V 0V G 1V 0V G 1V S S 0V D 0V V 1V 0V G 0V Planar Surrounding gate 56

Because of off-leakage control, Planar Nanowire S Wdep 1 D 0V G S 0V D 0V 1V G 0V Leakage current Source Gate Drain Planar FET Fin FET Nanowire FET

Nanowire structures in a wide meaning G G G G G Fin Tri-gate Ω-gate Nanowire 58

Nanowire FET 2015 2020 22 or 16nm node 11 or 8nm node Multiple Gate (Fin) FET Nanowire FET ITRS 2009 Bulk Fin Nanowire Bulk or SOI Fin Si Si Nanowire

Si nanowire FET as a strong candidate 1. Compatibility with current CMOS process 2. Good controllability of I OFF S Leakage current Wdep 1 D cut-off Off 3. High drive current source Drain Gate:OFF Gate: OFF drain Source 1D ballistic conduction Multi quantum Channel E Quantum channel Quantum channel Quantum channel k Quantum channel High integration of wires 60

Increase the Number of quantum channels By Prof. Shiraishi of Tsukuba univ. 4 channels can be used Eg Eg Energy band of Bulk Si Energy band of 3 x 3 Si wire 61

Si/Si 0.8 Ge 0.2 superlattice epitaxy on SOI SiN HM SiN SiGe Si SiGe Si SiGe Si BOX Device fabrication Anisotropic etching of these layers BOX Isotropic etching of SiGe BOX ( ) The NW diameter is controllable down to 5 nm by self limited oxidation. Gate depositions HfO 2 (3nm) TiN (10nm) Poly-Si (200nm) Gate Gate etching Gate S/D implantation Spacer formation Activation anneal Salicidation Standard Back-End of-line Process BOX BOX Process Details : C. Dupre et al., IEDM Tech. Dig., p.749, 2008 7

3D-stacked Si NWs with Hi-k/MG Top view Cross-section SiN HM Source Gate Drain 500 nm <110> Wire direction : <110> 50 NWs in parallel 3 levels vertically-stacked Total array of 150 wires EOT ~2.6 nm C. Dupre et al., IEDM Tech. Dig., p.749, 2008 50nm NWs BOX 8

SiNW FET Fabrication S/D & Fin Patterning Sacrificial Oxidation 30nm Oixde etch back 30nm SiN sidewall support formation 30nm Gate Oxidation & Poly-Si Deposition Gate Lithography & RIE Etching Gate Sidewall Formation Ni SALISIDE Process (Ni 9nm / TiN 10nm) Backend Standard recipe for gate stack formation

(a) SEM image of Si NW FET (Lg = 200nm) (b) high magnification observation of gate and its sidewall. 65

Recent results to be presented by ESSDERC 2010 next week in Sevile Wire cross-section: 20 nm X 10 nm 7.E-05 60 6.E-05 50 5.E-05 40 4.E-05 30 3.E-05 20 2.E-05 10 1.E-05 0 0.E+00 (µa)70 Drain Current (a) V g -V th =1.0 V 0.8 V 0.6 V V g -V th = -1.0 V 0.4 V 0.2 V -1.0-0.5 0.0 0.5 1.0 Drain Voltage (V) On/Off>10 6 60uA/wire 1.E-03 1.E-04 10-4 1.E-05 10-5 1.E-06 10-6 1.E-07 10-7 1.E-08 10-8 1.E-09 10-9 1.E-10 10 1.E-11 10 1.E-12 10 10-3 Drain Current (A) (b) V d =-1V V d =-50mV pfet nfet -1.5-1.0-0.5 0.0 0.5 1.0 Gate Voltage (V) L g =65nm, T ox =3nm V d =1V V d =50mV

Bench Mark I ON (µa / wire) 70 60 50 40 30 20 10 0 nmos pmos (34) (13) (10) 102µA (16) (12) (13x20) (8) (8) (10) (10x20) (9x14) (12) (12x19) (12) (12x19) (10) V DD : 1.0~1.5 V (5) (5) (10) (10) (3) (3) (30) (19) 1 10 100 1000 Gate Length (nm) Our Work

I ON /I OFF OFF Bench mark Planer FET 1.0 1.1V S. Kamiyama, IEDM 2009, p. 431 P. Packan, IEDM 2009, p.659 L g =500 65nm This work Si FET 1.2 1.3V Y. Jiang, VLSI 2008, p.34 H.-S. Wong, VLSI 2009, p.92 S. Bangsaruntip, IEDM 2009, p.297 C. Dupre, IEDM 2008, p. 749 S.D.Suk, IEDM 2005, p.735 G.Bidel, VLSI 2009, p.240

Electron Density (x10 19 cm -3 ) 6 6.E+19 5 5.E+19 4 4.E+19 3 3.E+19 2 2.E+19 1 1.E+19 0 0.E+00 Edge portion Flat portion 0 2 4 6 8 Distance from SiNW Surface (nm)

Primitive estimation! I ON (µa/µm) P-MOS pmos improvement (26) S/D Low resistance (11) (20) (15) bulk Compact model Small EOT for high-k (33) 1µm # of wires /1µm FD SiNW (12nm 19nm) I ON Nanowire Assumption I ON L g -0.5 T ox -1 ITRS MG Year

Intel announcement 72

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Our roadmap for R &D Source: H. Iwai, IWJT 2008 Current Issues Si Nanowire Control of wire surface property Source Drain contact Optimization of wire diameter Compact I-V model III-V & Ge Nanowire High-k gate insulator Wire formation technique CNT: Growth and integration of CNT Width and Chirality control Chirality determines conduction types: metal or semiconductor Graphene: Graphene formation technique Suppression of off-current Very small bandgap or no bandgap (semi-metal) Control of ribbon edge structure which affects bandgap 74

Thank you for your attention! 75