PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec

Similar documents
450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D

HOW TO CONTINUE COST SCALING. Hans Lebon

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group

Outline. Introduction on IMEC & IMEC cooperation model. Program Challenges in CMOS scaling

Holistic View of Lithography for Double Patterning. Skip Miller ASML

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm

ASML, Brion and Computational Lithography. Neal Callan 15 October 2008, Veldhoven

22nm node imaging and beyond: a comparison of EUV and ArFi double patterning

The future of lithography and its impact on design

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm

Nanometer Technologies: Where Design and Manufacturing Converge. Walden C. Rhines CHAIRMAN & CEO

IMEC update. A.M. Goethals. IMEC, Leuven, Belgium

Scaling of Semiconductor Integrated Circuits and EUV Lithography

Lithography Roadmap. without immersion lithography. Node Half pitch. 248nm. 193nm. 157nm EUVL. 3-year cycle: 2-year cycle: imec 2005

Computational Lithography Requirements & Challenges for Mask Making. Naoya Hayashi, Dai Nippon Printing Co., Ltd

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09

EUVL getting ready for volume introduction

Public. Introduction to ASML. Ron Kool. SVP Corporate Strategy and Marketing. March-2015 Veldhoven

EUVL Scanners Operational at Chipmakers. Skip Miller Semicon West 2011

5 th Annual ebeam Initiative Luncheon SPIE February 26, Aki Fujimura CEO D2S, Inc. Managing Company Sponsor ebeam Initiative

EUV lithography: today and tomorrow

2008 European EUVL. EUV activities the EUVL shop future plans. Rob Hartman

Limitations and Challenges to Meet Moore's Law

Advanced Patterning Techniques for 22nm HP and beyond

Holistic Lithography. Christophe Fouquet. Executive Vice President, Applications. 24 November 2014

Impact of 3-D Mask Effects on CD and Overlay over Image Field in Extreme Ultraviolet Lithography

The Development of the Semiconductor CVD and ALD Requirement

Chapter 7 Introduction to 3D Integration Technology using TSV

Imaging for the next decade

450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum July 10, 2013 Doug Shelton Canon USA Inc.

NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY

Lithography Industry Collaborations

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978)

Innovation to Advance Moore s Law Requires Core Technology Revolution

Present Status and Future Prospects of EUV Lithography

Process Variability and the SUPERAID7 Approach

Sustaining the Si Revolution: From 3D Transistors to 3D Integration

TECHNOLOGY ROADMAP 2011 EDITION LITHOGRAPHY FOR

Enabling Breakthroughs In Technology

Competitive in Mainstream Products

Novel EUV Resist Development for Sub-14nm Half Pitch

Imec pushes the limits of EUV lithography single exposure for future logic and memory

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING

NEXT GENERATION SILICON PHOTONICS FOR COMPUTING AND COMMUNICATION PHILIPPE ABSIL

EUV lithography: status, future requirements and challenges

Technological Challenges in Semiconductor Lithography

Roadmap Semiconductor Equipment Innovation Agenda

Towards an affordable Cost of Ownership for EUVL. Melissa Shell Principal Engineer & Program Manager, EUVL Research Components Research October 2006

Mask Technology Development in Extreme-Ultraviolet Lithography

Progress in full field EUV lithography program at IMEC

Enabling Semiconductor Innovation and Growth

DUV. Matthew McLaren Vice President Program Management, DUV. 24 November 2014

Status and challenges of EUV Lithography

Shot noise and process window study for printing small contacts using EUVL. Sang Hun Lee John Bjorkohlm Robert Bristol

Update on 193nm immersion exposure tool

ATV 2011: Computer Engineering

Optics for EUV Lithography

Scope and Limit of Lithography to the End of Moore s Law

Fabricating 2.5D, 3D, 5.5D Devices

INTERNATIONAL TECHNOLOGY ROADMAP LITHOGRAPHY FOR SEMICONDUCTORS 2009 EDITION

MAPPER: High throughput Maskless Lithography

Foundry processes for silicon photonics. Pieter Dumon 7 April 2010 ECIO

EUV Supporting Moore s Law

Flare compensation in EUV lithography

(Complementary E-Beam Lithography)

45nm Foundry CMOS with Mask-Lite Reduced Mask Costs

Silicon Photonics Transceivers for Hyper Scale Datacenters: Deployment and Roadmap

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

The Future of Packaging ~ Advanced System Integration

State-of-the-art device fabrication techniques

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141

Silicon VLSI Technology. Fundamentals, Practice and Modeling. Class Notes For Instructors. J. D. Plummer, M. D. Deal and P. B.

Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel

Market and technology trends in advanced packaging

Light Sources for EUV Mask Metrology. Heiko Feldmann, Ulrich Müller

EUV: Status and Challenges Ahead International Workshop on EUVL, Maui 2010

Newer process technology (since 1999) includes :

Photoresists & Ancillaries. Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report

Discovering Electrical & Computer Engineering. Carmen S. Menoni Professor Week 3 armain.

EUVL Challenges for Next Generation Devices

Optolith 2D Lithography Simulator

Optical Microlithography XXVIII

Feature-level Compensation & Control

OPTICAL I/O RESEARCH PROGRAM AT IMEC

Photolithography. References: Introduction to Microlithography Thompson, Willson & Bowder, 1994

Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions.

New Process Technologies Will silicon CMOS carry us to the end of the Roadmap?

16nm with 193nm Immersion Lithography and Double Exposure

Jan Bogaerts imec

Litho Metrology. Program

Double Patterning Combined with Shrink Technique to Extend ArF Lithography for Contact Holes to 22nm Node and Beyond

Application-Based Opportunities for Reused Fab Lines

Facing Moore s Law with Model-Driven R&D

From ArF Immersion to EUV Lithography

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

Spring of EUVL: SPIE 2012 AL EUVL Conference Review

Packaging Roadmap: The impact of miniaturization. Bob Pfahl, inemi Celestica-iNEMI Technology Forum May 15, 2007

Lecture 0: Introduction

Negative tone development process for double patterning

Transcription:

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS LUC VAN DEN HOVE President & CEO imec

OUTLINE! Industry drivers! Roadmap extension! Lithography options! Innovation through global collaboration imec 2010

Experience the world wherever you are Computer Communication Consumer Connected World Computer Always connected Virtual Social Networks (Facebook, LinkedIn, Twitter, You Tube...)

Experience the world wherever you are Video to dominate mobile data traffic Total mobile data traffic (Tetabyte per month) 2,000,000 1,500,000 1,000,000 500,000 Global mobile data traffic, by type 7% 0 2008 2009E 2010E 2011E 2012E 2013E Source: Morgan Stanley Data Ubiquitous Connectivity 10% P2P Video + Ultimate Graphics 19% 3D 64% Video Voice NVIDIA

Computing Communication Consumer

Computing Communication Consumer Lifestyle Healthcare

BUSY LIFESTYLE 1 billion overweight people 300 million of those are obese

AGING POPULATION 600 million persons 60+ Expected to double by 2025

RISE IN CHRONIC DISEASES 600 million people worldwide $500 billion a year (US) $685 billion by 2020 (US)

MEDICINE GOES DIGITAL PERSONALIZED - PREDICTIVE - PREVENTIVE

WEARABLE HEALTH AND COMFORT MONITORING internet doctor hospital Anywhere, anytime Connected health Health and lifestyle

WEARABLE HEALTH AND COMFORT MONITORING ECG NECKLACE FOR AMBULATORY APPLICATIONS

WEARABLE HEALTH AND COMFORT MONITORING

BOOSTING CHIP PERFORMANCE AND SYSTEM FUNCTIONALITY TERAFLOP TERABIT MORE FUNCTIONALITY

BOOSTING CHIP PERFORMANCE AND SYSTEM FUNCTIONALITY TERAFLOP TERABIT MORE FUNCTIONALITY

RELENTLESS SCALING 1965 2002-2003 ~ 90 nm Lithography Enabled Scaling STOP Geometric (Dennard s Law) Scale: tox, Lg, xj,...

RELENTLESS SCALING 1965 2002-2003 ~ 90 nm Lithography Enabled Scaling Geometric (Dennard s Law) Materials Enabled Scaling Scale: tox, Lg, xj,...

RELENTLESS SCALING 1965 2002-2003 ~ 90 nm Lithography Enabled Scaling Materials Enabled Scaling Metal gate High-k Intel High mobility SiGe channel

RELENTLESS SCALING 1965 2002-2003 ~ 90 nm ~ 15nm Lithography Enabled Scaling Materials Enabled Scaling Fin Fin poly-si Strained Si High-k Metal Gate Multi Gate FINFET

RELENTLESS SCALING 1965 2002-2003 ~ 90 nm ~ 15nm Lithography Enabled Scaling Materials Enabled Scaling

EXTREME HIGH MOBILITY CHANNELS

EXTREME HIGH MOBILITY CHANNELS

RELENTLESS SCALING Lithography Enabled Scaling Materials Enabled Scaling 3D Enabled Scaling From Plane to Cube

3D STACKED ICs CONNECTED THROUGH TSVs Top die 10um 10um 25um 25um 5um Top tier Bottom tier Bottom die Cu - Cu bonding

PERFORMANCE MOBILE SYSTEMS E.g., Netbooks Cost, Power, Form factor, Performance REUSE COMPUTE SYSTEMS E.g., Routers, Severs Performance, Power efficiency, heat dissipation, Reliability 3D Integration & advanced packaging CONSUMER E.g., micro-servers Power, Cost, Performance, Form factor,... MODULARITY HEALTHCARE E.g., sensor nodes Form-factor, power, bio-compatibility,reliability FORMFACTOR

3D STACKED ICs CONNECTED THROUGH TSVs Optical interconnects Photonics Multi-core logic Memory

NEW MEMORY CONCEPTS GdAlSiO x Si 3 N 4 BiCS (ref. Toshiba) Explore Marc Heyns!imec 2009

NEW MEMORY CONCEPTS GdAlSiO x Cross-bar memory Si 3 N 4 Explore Marc Heyns!imec 2009

LIKELY FLASH ROADMAP 2010 2011 2012 2013 2014 >2015 RRAM <1F 2 3D NAND 1F 2 GdAlSiO x 3 bit FG 4 bit FG 2F 2 2 bit FG

LIKELY DRAM ROADMAP 2010 2011 2012 2013 2014 >2015 RRAM 1x nm 4F 2 3x nm 2x nm 6F 2 6x nm 5x nm GdAlSiO x 4x nm 8F 2

RELENTLESS SCALING Lithography Enabled Scaling Materials Enabled Scaling 3D Enabled Scaling

DOUBLE PATTERNING Litho-Etch-Litho-Etch Spacer defined DP First exposure First exposure Etch Second exposure Spacer making Final CD < 10%CD Etch Final CD < 10% CD Etch 32nm Lines/32nm Spaces Surname + Name! IMEC restricted 2009 36

SOURCE MASK OPTIMIZATION 22NM SRAM PROCESS WINDOW WITH DOUBLE PATTERNING Freeform illumination Mask!56 nm defocus!48 nm defocus Best focus best dose +40 nm defocus +48 nm defocus Standard illumination Contact layer design split k 1 =0.384 Exposure Latitude (%)! 10! 8! MEEF = 3.0 6! 4! MEEF = 4.4 2! 0! 0 20 40 60 80 100 120 Depth of Focus (nm) Process window limiting feature Surname + Name! IMEC restricted 2009 37

28 nm 30 nm EUV LITHOGRAPHY

EUV TOOL OUTPUT 2500 2000 1500 2009 cumulative wafer output # good wafers 2500 2000 1500 2010 cumulative wafer output ~ 2200 1000 1000 500 500 0 1 6 11 16 21 26 31 36 41 46 51 Weeks 0 1 6 11 16 21 26 31 36 41 46 51 Weeks

22nm NODE SRAM PATTERNING WITH EUV 0.089 µm 2 0.406µm! 0.22µm! 40

IMEC PARTNER EXPOSURES

RESIST MATERIALS Sensitivity Resolution Acid Diffusion Length = Pixel Size Shot Noise Statistics = Photons/ Pixel Acid Diffusion Length Line Width Roughness Surname + Name! IMEC restricted 2009 42

RESIST MATERIALS 09-58 10.04 10-01 09-48 10-05 10-02 10-03 SEVR-59 09-45 09-46 Surname + Name! IMEC restricted 2009 43

EUV ROADMAP TOWARDS 10nm ADT NXE:3100 NXE:3300 imec 2010

ML2 LITHO DEVELOPMENT Meeting the 3 key targets (resolution, overlay, throughput) for direct write on Si is extremely challenging! Targets are rapidly moving according to Moore s law. Missing the targeted insertion node can have major impact on the ROI Focusing on mask writing as intermediate milestone! Reduces the risk: any throughput improvement is welcome Both 193nm and EUVL can use this LUC VAN DEN HOVE / IMEC 2010 45

OUTLINE! Industry drivers! Roadmap extension! Lithography options! Innovation through global collaboration imec 2010

BRINGING TOGETHER FULL ECO SYSTEM System Logic IDM Memory IDM Fabless Fablite Foundries EDA Material Suppliers Suppliers Equipment Suppliers SAT imec 2010

BRINGING TOGETHER FULL ECO SYSTEM System Logic IDM Memory IDM Fabless Fablite Foundries EDA Material Suppliers Suppliers Equipment Suppliers SAT imec 2010

CONCLUSIONS!Nano-electronics will continue to bring innovation into many converging application fields!concurrent scaling enabled by lithography materials innovations 3D!Momentum on EUV has increased tremendously during last year!global collaboration (including entire value chain) is required to address the huge R&D challenges LUC VAN DEN HOVE / IMEC 2010

ASPIRE INVENT ACHIEVE