Supertex inc. TN0702. N-Channel Enhancement-Mode Vertical DMOS FET. Features

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TN72 Features Low threshold - 1.6V max. High input impedance Low input capacitance - 13pF typical Fast switching speeds Low on-resistance guaranteed at = 2, 3, and 5V Free from secondary breakdown Low input and output leakage Applications Logic level interfaces ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches N-Channel Enhancement-Mode Vertical DMOS FET General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Ordering Information Part Number Package Option Packing TN72N3-G 1/Bag TN72N3-G P2 TN72N3-G P3 TN72N3-G P5 TN72N3-G P13 TN72N3-G P14 Absolute Maximum Ratings Parameter Value Drain-to-source voltage BS Drain-to-gate voltage BV DGS Gate-to-source voltage ±2V Operating and storage temperature -55 O C to +15 O C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Doc.# DSFP-TN72 C8813 -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. Typical Thermal Resistance Package θ ja 132 O C/W 2/Reel Product Summary BS /BV DGS Pin Configuration SiTN 72 YYWW (max) SOURCE Product Marking (ON) (min) DRAIN GATE YY = Year Sealed WW = Week Sealed = Green Packaging Package may or may not include the following marks: Si or (th) (max) 2V 1.3Ω.5A V

Thermal Characteristics Package (continuous) (pulsed) Electrical Characteristics (T A unless otherwise specified) Sym Parameter Min Typ Max Units Conditions TN72 BS Drain-to-source breakdown voltage 2 - - V = V, = ma (th) Gate threshold voltage.5.8 V =, = ma Δ(th) Change in (th) with temperature - - -4. mv/ O C =, = ma I GSS Gate body leakage - - 1 na = ± 2V, = V - - 1 na = V, = Max Rating SS Zero gate voltage drain current V - - 1 µa DS =.8 Max Rating, = V, T A = 125 C (ON) On-state drain current.5 - A = = 5.V - 4. 5. = 2.V, = 5mA Static drain-to-source on-state resistance - 1.9 2.5 Ω = 3.V, = 2mA - 1.3 = 5.V, = 5mA Δ Change in with temperature - -.75 %/ O C = 5.V, = 5mA G FS Forward transductance 1 5 - mmho = 5.V, = 5mA C ISS Input capacitance - 13 2 = V, C OSS Common source output capacitance - 7 125 pf = 2V, C RSS Reverse transfer capacitance - 3 6 f = MHz t d(on) Turn-on delay time - - 2 t V DD = 2V, r Rise time - - 2 ns =.5A, t d(off) Turn-off delay time - - 3 R GEN = 25Ω t f Fall time - - 2 V SD Diode forward voltage drop - - V = V, I SD =.5A Notes: 1. All D.C. parameters 1% tested at 25 O C unless otherwise stated. (Pulse test: 3µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit Power Dissipation @ 53mA A W 53mA A Notes: (continuous) is limited by max rated T j. R RM INPUT 1V V 1% 9% Pulse Generator VDD R L OUTPUT t (ON) t (OFF) R GEN t d(on) t r t d(off) t f VDD OUTPUT 1% 1% INPUT D.U.T. V 9% 9% Doc.# DSFP-TN72 C8813 2

TN72 Typical Performance Curves 5. Output Characteristics 5. Saturation Characteristics = 8V = 8V 4. 4. 3. 2. 6V 5V 3. 2. 6V 5V 4V 4V 3V 3V 5. 1 15 2 2V 2V 2. 4. 6. 8. 1 Transconductance vs. Drain Current 2. = 5.V Power Dissipation vs. Case Temperature 2. G FS (siemens) T A = -55 O C 25 O P D (watts) 15 O.5 1.5 2. 2.5 25 5 75 1 125 15 1 Maximum Rated Safe Operating Area Thermal Response Characteristics.1 (Pulsed) Thermal Resistance.8.6.4.2 P D = W Doc.# DSFP-TN72 C8813.1.1 1 1 3.1.1.1 1 t P (seconds)

Typical Performance Curves (cont.) BS Variation with Temperature 5. On-Resistance vs. Drain Current TN72 4. BS (ohms) 3. 2. = 2.V = 3.V = 5.V.8-5 5 1 15 T j.5 1.5 2. 2.5 5. Transfer Characteristics V (th) and R DS Variation with Temperature 1.6 4. 3. 2. = 5V T A = -55 O C 125 O C 25 O C (th) 1.4.8 V (th) @ ma R DS @ 1V,.5A 1.4.8.6 2. 4. 6. 8. 1-5 5 1 15 T j.6 Capacitance vs. Drain-to-Source Voltage 2 1 Gate Drive Dynamic Characteristics 15 f = MHz 8. = 1V C (picofarads) 1 C ISS 6. 4. 2 pf = 2V C OSS 5 2. 146 pf C RSS 5. 1 15 2.6 1.8 2.4 3. Q G (nanocoulombs) Doc.# DSFP-TN72 C8813 4

3-Lead Package Outline (N3) TN72 D Seating Plane 1 2 3 A L e1 e Front View b c Side View E1 1 3 E 2 Bottom View Dimensions (inches) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http:///packaging.html.) does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 213 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TN72 C8813 Symbol A b c D E E1 e e1 L MIN.17.14.14.175.125.8.95.45.5 NOM - - - - - - - - - MAX.21.22.22.25.165.15.15.55.61* JEDEC Registration. * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E419. 5 1235 Bordeaux Drive, Sunnyvale, CA 9489 Tel: 48-222-8888