EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Spring 2015 Dae Hyun Kim daehyun@eecs.wsu.edu 1
Lecture 4 More on CMOS Gates Ref: Textbook chapter 2 Some of the slides are adopted from Digital Integrated Circuits by Jan M Rabaey 2
CMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratio less Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors N fan-in gates need 2N transistors 3
Special CMOS Design Styles Ratioed Logic (Pseudo-nMOS) Dynamic CMOS Domino Logic Multiple-Output Domino Logic Dual-Rail Logic Pass Transistor Logic Transmissions Gate Logic 4
Ratioed Logic Pseudo NMOS Smaller area and load, but static power dissipation Follow board notes 5
Pseudo-nMOS More accurate computation PMOS: Saturation NMOS: Linear V DD 0 ββ nn 2 2 VV DDDD VV tttt VV OOOO VV OOOO 2 = ββ pp 2 (VV DDDD VV tttt ) 2 VV oooooo A VV OOOO = VV DDDD VV tttt VV DDDD VV tttt 2 ββ pp ββ nn (VV DDDD VV tttt ) 2 6
Pseudo-nMOS V DD V DD V DD 0 RR pp VV oooooo VV oooooo = VV DDDD RR nn VV oooooo = VV DDDD RR pp + RR nn A B C RR nn RR nn VV oooooo = 0.1VV DDDD = VV DDDD RR pp + RR nn RR pp = 9RR nn 7
Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors 8
Dynamic CMOS Clk M p Clk M p Out Out In 1 In 2 In 3 Clk PDN (nfets) M n C L A B Clk M n C Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) 9
Dynamic CMOS Operation CCCC VV DDDD 0 Precharge Evaluate Precharge Evaluate tt Mp: ON Mp: OFF Mn: OFF Mn: ON 10
Dynamic CMOS FF = AA BB CC Mp VV oooooo A CC oooooo B C CK Mn 11
Dynamic CMOS Precharge Mp VV oooooo = 1 A CC oooooo B C CK=0 Mn 12
Dynamic CMOS Evaluation Mp VV oooooo = 0 oooo 1 A CC oooooo B C CK=1 Mn 13
Properties of Dynamic CMOS Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static CMOS gates) Full swing outputs Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (Cout) 14
Properties of Dynamic CMOS Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND no glitching higher transition probabilities extra load on Clk Needs a precharge/evaluate clock 15
Dynamic CMOS Charge sharing Mp VV oooooo A CC oooooo B CC 1 C CC 2 CK Mn CC 3 16
Dynamic CMOS Charge sharing Mp VV oooooo = VV DDDD VV oooooo A=0 VV 1 = 0 CC oooooo A=1 VV 11 CC oooooo B=0 VV 2 = 0 CC 1 B=1 VV 22 CC 1 C=0 CC 2 C=0 CC 2 CK=0 VV 3 = 0 CC 3 CK=1 Mn VV 3 = 0 CC 3 17
Dynamic CMOS Charge sharing VV oooooo = VV 1 = VV 2 QQ = CC oooooo VV DDDD = CC oooooo VV ff + CC 1 VV ff + CC 2 VV ff = CC oooooo + CC 1 + CC 2 VV ff VV ff = ( CC oooooo CC oooooo +CC 1 +CC 2 )VV DDDD A=1 VV 11 VV oooooo CC oooooo B=1 VV 22 CC 1 C=0 CC 2 Mn VV 3 = 0 CC 3 18
Dynamic CMOS How to solve the charge sharing problem Constraint: CC oooooo CC 1 + CC 2 Keeper Keeper Clk M p M kp A B C L Out Clk M e 19
Dynamic CMOS How to solve the charge sharing problem Clk A M p M kp Out Clk B Clk M e Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) 20
Domino Logic CK 21
Domino Logic PDN PDN PDN CK 22
Domino Logic Example SSSSSS = aa bb cc a b c Sum XX XX SSSSSS a aa a aa X XX b bb bb b cc c CK CK CK 23
Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced 24
Multiple-Output Domino Logic (MODL) ff 1 = GG ff 2 = FF GG ff 2 = FF GG F ff 1 = GG G CK 25
Dual-Rail Logic Network Differential Cascode Voltage Switch Logic (DCVSL) VV DDDD ff ff XX 1 XX 2 XX 3 Logic tree XX 1 XX 2 XX 3 26
Dual-Rail Logic Network Differential Cascode Voltage Switch Logic (DCVSL) VV DDDD VV DDDD ff ff aa bb aa bb XX 1 XX 2 Logic tree XX 1 XX 2 aa bb aa XX 3 XX 3 bb 27
Pass Transistor Logic B Inputs Switch Network Out A B B Out N transistors No static consumption 28
Pass Transistor Logic Example BB BB AA AA BB FF = AA BB BB FF = AA + BB 0 1 29
Issues with Pass Transistor Logic Threshold drop Capacitive feed through Charge sharing Follow board notes VV DDDD VV tttt VV DDDD 2VV tttt 30
Pass Transistor Logic Capacitive Feedthrough VV DDDD 0VV G CC ff VV oooooo VV iiii D S CC gggggg 0VV 31
Transmission Gate Logic A S S VDD M2 F The control signal S turns the transfer gates on and off depending on its value. When s=1, the upper transfer gate is on and that allows A to follow to the output M1 B S Implement the Multiplexer with static CMOS and compare with this 32
Transmission Gate Logic B M2 B A M1 B F B A M3/M4 33