Thermal Management in the 3D-SiP World of the Future Presented by W. R. Bottoms March 181 th, 2013
Smaller, More Powerful Portable Devices Are Driving Up Power Density Power (both power delivery and power integrity) and physical density of bandwidth are the two major limiting factors for the digital electronics industry. Neither of these limiting factors will be resolved without improvements in Thermal Management 2
N810.113mvc-tra ffic N1110.146mvc Changing Landscape M Units 2,500 2,000 1,500 1,000 500 0 Bandit Phones Branded Phones Smartphones MOBILE PHONE MARKET Exabytes 50 15 10 Networking & Server 5 0 6.2% 3.6% 2009 2,100 GLOBAL MOBILE DATA TRAFFIC (2009-2015) 300 7.5% 1,650 10.8% 1,535 Traffic doubles every year 1,385 4.0% 260 45 6.7% PoP + WLCSP+ FCCSP 4.2% 250 Capacity strain on infrastructure 1,800 240 8.2% 40 Si Interposer + 3D 12.2% In every case Thermal 1,390 35 Heterogeneous Management Integration SiP 1,285 1,145 30 19.8% Cisco 720 27.3% 25 is the limiting factor 57.1% 350 275 CAAGR 2009-2014 175 2009 2010 2011 20 2015 109% Packaging Technology Ultra Low Alpha Large Die, Large Package Heterogeneous Integration SiP Silicon Interposer + 3D Traffic doubles every year Ericsson CAAGR 2009-2014 120% 2010 2011 2012 2013 2014 Smart Phone Packaging Technology Data transmission and memory are Capacity strain joining on infrastructure logic making significant and growing power demands 2015 Source: Cisco and Ericsson Measurements in Global Networks Where we are Where we are going 3
Thermal Density Is Impacting Everything 4 Qualcomm Presentation At RTI 3D Conference 2012
The first and most effective technique for thermal management is to reduce power requirement 5
Thermal Management Solutions Reduce Power Requirements Continue Moore s Law scaling As long as it s effective Use equivalent scaling through functional diversification Use the 3 rd dimension New Materials New device and package architectures 6
The 45 Year History Of Knowing What Comes Next Is Over Progress has been paced by Moore s Law and driven by: Focus was on design and fab Shrinking geometries Expanding wafer size Higher density designs For digital circuits there are now limitations that can t be met by these activities alone. 7
Power Density Limitations Of Moore s Law It Will Not Be Able To Keep Up This Pace Of Progress CMOS Power is no longer scaling with feature size A majority of the capacitance is in the interconnect Resistivity of Copper is rising with decreased feature size Power is rising with increased frequency International Electron Devices Meeting December 2012 Kurt Ronse, IMEC 14-nm chips likely will deliver about 15 to 20 percent performance boosts over the prior generation, rather than the typical 30 percent boost 8
Problems Arising From Shrinking CMOS Gate tunneling current increases Subthreshold channel leakage current increases Device parameter variability increases Source/drain resistance increases Copper interconnect resistivity increases Power no longer scales with feature size, both static and dynamic power dissipation increase due to these barriers. 9
How Can We Reduce Power In Scaling CMOS? Reduce leakage currents Reduce on-chip Interconnect power by: Decrease conductor resistance Decrease capacitance Reduce interconnect length Reduce operating frequency Reduce operating voltage Voltage regulator per core Reduce high speed electrical signal length (new transistor designs) (new material) (new material) (3D integration) (increased parallelism) (reduced frequency& size) (new IC designs; FINFET) (serdes with short path To very wide bus) 10
Decrease The Operating Voltage Qi Wang, Cadence technical marketing group director In the last 10 to 20 years, there has been a lot of effort devoted to performance, but we have left a lot of margin on the power side. Why do we keep Vdd at 1 volt? There s no point. You can drop Vdd to 0.3 or 0.4. People need a safer way to do circuit design. Note: This decreases power requirement but increases need for low cost high k dielectrics 11
Functional diversification and Heterogeneous integration enable equivalent scaling This has been titled More than Moore 12
Moore s Law Scaling Can Not Maintain The Pace Of Progress And Packaging Enables Equivalent Scaling More Moore : Scaling Beyond CMOS Λ. 14nm 28nm 32nm Baseline CMOS: CPU, Memory, Logic Information Processing Digital content System-on-Chip 45nm 65nm 90nm Analog/RF Passives HV Power Sensors Actuators More than Moore : Functional Diversification Biochips Fluidics o o o o Interacting with people and environment Non-digital content System-in-Package (SiP) 13
More Than Moore Heterogeneous Integration Enabled By Sip Functional diversification delivers equivalent scaling The most cost efficient, energy efficient and highest performance is achieved when each circuit fabric type is fabricated with process and materials optimized for that component The contribution of Assembly and Packaging to MtM is System in Package integration SiP. The package provides: The use of the most efficient component for each function The delivery of the resources to the components necessary for their function The delivery of output/removal of heat and by products from operation of the SiP Protection of the components in the package 14
Examples Of 3d-SiP Products 15 Source: Fraunhofer IZM
Use of the third Dimension 3D System Integration 16
Cost (arbitrary units) Semiconductor Electronics Has Been Characterized By An S-curve Production Ramp-up Model and Technology/Cycle Timing.00001.0001.001.01 1 Development First Conf. Papers Production In the first S-Curve cycle in the semiconductor industry the Technology was the transistor First Two Companies 100 10 in Production 1 10,000 1000 Volume (arbitrary units) -2-1 0 1 2 Time (arbitrary units) 17
Cost (arbitrary units) Can The 3D IC Maintain Progress Through A Third S-curve Cycle? Production Ramp-up Model and Technology/Cycle Timing.00001 3D 3D IC 10,000.0001.001.01 1 1D 2D Transistors Integrated Circuits 1000 100 10 1 Volume (arbitrary units) 18
Speed and Power Advantages of 3D 3D interconnect decreases path lengths. For n TSV stacked layers, this may reduce global interconnect path lengths by square root of n Reduction in interconnect length Faster circuit speed Reduced power consumption Standby power reduced by 75% compared to PoP and MCP packages Smaller physical size Eventually, lower cost 19
3D Components For Smart Phones 20 Source: Yole
Thermal management challenges for 3D-SiP Architecture Finding solutions is not going to be easy High thermal dissipation density Hot spots Differential thermal expansion Heterogeneous integration Both circuit type and material The result is thermal limitations for: Bandwidth Power density Cost Reliability 21
Hot Spots management is critical for Heterogeneous Integration 22 Qualcomm Presentation At RTI 3D Conference 2012
New Materials are an essential tool in Thermal Management 23
New Materials Will Be Required Many are in use today Many are in development Cu interconnect Ultra Low k dielectrics High k dielectrics Organic semiconductors Green Materials Pb free Halogen free Nanotubes Nano Wires Macromolecules Nano Particles Composite materials But improvements are needed 24
Thermal Management Materials Requirements Examples Thermal Interface Mat. Mold Compound Conductors Adhesives Underfill Adhesion Functional Properties Moisture Resistance Modulus Fracture Toughness CTE Highly coupled Material Properties Novel materials to achieve optimal performance for each parameter 25
New Materials Requirements New dielectrics Both high and low K New conductors Both thermal and electrical Improved thermal interface materials Nano-materials Particularly as fillers for composite materials 26
Dielectrics And Conductors Are Changing Si based Low k dielectrics in engineering status today Properties Value k 1.8 n 633 1.21 E (GPa) 3.0 H (GPa) 0.5 Adhesion, Critical Load (mn) TBD Etch stability 0.5% HF at RT P 1% KOH at 50 o C P Porosity > 40% Source: SBA Materials 27
Dielectrics And Conductors Are Changing Composite Copper is in evaluation. Current status: The first electrical performance improvement in copper since 1913 makes composite copper the most electrically conducting material known at room temperature. Targets for improvement compared to conventional copper are: 100 % increase in electrical conductivity 100% increase in thermal conductivity 300% increase in tensile strength 28 Source: NanoRidge
Graphene Supports >10X Cu A/Cm 2 29
Graphene Has Superior Electromigration Lifetime 30
Carbon Conductors Look Better Than Cu Many questions still to be answered before graphene or CNT can be considered as a practical interconnect materials. The results so far are very promising. 31
Other Techniques For Thermal Management 32
High Thermal Conductivity Materials For Thermal Management In Stacked Die Composite underfill and inter-layer dielectric with high thermal conductivity Thin, high efficiency heat sink Composite Mold Compound with high thermal conductivity Thermal Vias in the stack Composite Mold Compound with high thermal conductivity 33
Reduce Power The low hanging Fruit Move the photons as close to the transistors as possible 34
Microfluidic Cooling Is One Solution T. Brunschwiler et al., 3D-IC 2009 (IBM) 35
What Can We Do To Meet Thermal Challenges With 3D-SiP Archtecture? Reduce the power dissipation Use the 3 rd dimension. Stacking can reduce power by as much as the square root of the number of layers Reduce operating frequency. Increased parallelism can restore performance at lower power cost. Reduce operating voltage. You don t need the voltage if you operate at lower frequency. Smart power management in the package. Turn off the power to sections of the circuit not in use; voltage regulator per core. New materials (for reduced power, improved thermal tolerance and improved heat removal) Ultra-low K dielectrics. Power dissipation is proportional to C. Composite copper. Improved thermal and electrical conductivity. Direct band gap semiconductors. Extreme CMOS with Ge and IIIV compounds for higher speed and lower power. Carbon nanotubes for improved conductors and heat spreaders. Graphene for improved conductors and heat spreaders. Nanowires for improved conductors with reduced edge and grain boundary scattering. Nano-ribbons for improved conductors with reduced edge and grain boundary scattering Nano-solders for higher conductivity and reduced processing temperatures New Device and Package architectures Microfluidics to the package and to the chip Move photonics closer to the transistors. On package and, eventually, on chip. Increased parallelism to meet bandwidth requirements at lower voltage. Bus widths of several thousand. Heterogeneous integration in SiP allowing optimal materials and process selection for each different circuit fabric type. 36
Thermal Management In The 3d-sip World Of The Future These thermal management techniques Reduce the power dissipation combined New materials can reduce thermal density by more New than device 2 orders and package of magnitude architectures and increase thermal dissipation efficiency. Reduce frequency by increasing parallelism Lower operating voltage Smart power management in the package However, thermal management will continue Examples: to low be k, a composite primary copper, limiting nano-solders, factor high k materials, 3D integration, thermal vias, for heat the spreaders, electronics SiP to industry; limit interconnect at least distance until the CMOS switch is replaced. 37
Thank You for your attention 38