Intelligent Power Module and Gate Drive Interface Optocouplers Technical Data HCPL- HCPL-J HCPL- HCNW Features Performance Specified for Common IPM Applications over Industrial Temperature Range: - C to C Fast Maximum Propagation Delays t PHL = ns t PLH = ns Minimized Pulse Width Distortion PWD = ns kv/µs Minimum Common Mode Transient Immunity at V CM = V CTR > % at I F = ma Safety Approval UL Recognized - V rms / min. for HCPL-//J - V rms / min. for HCPL- Option and HCNW CSA Approved IEC/EN/DIN EN -- Approved -V IORM = Vpeak for HCPL- Option -V IORM = Vpeak for HCPL- Option -V IORM = 9 Vpeak for HCPL-J -V IORM = Vpeak for HCNW Functional Diagram NC ANODE kω V CC V L Applications IPM Isolation Isolated IGBT/MOSFET Gate Drive AC and Brushless DC Motor Drives Industrial Inverters Truth Table LED ON OFF V O L H CATHODE V O NC GND The connection of a. µf bypass capacitor between pins and is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Description The HCPL- and HCPL- contain a GaAsP LED while the HCPL-J and the HCNW contain an AlGaAs LED. The LED is optically coupled to an integrated high gain photo detector. Minimized propagation delay difference between devices makes these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. An on chip kω output pull-up resistor can be enabled by shorting output pins and, thus eliminating the need for an external pull-up resistor in common IPM applications. Specifications and performance plots are given for typical IPM applications. Selection Guide Standard White Mold Package -Pin DIP -Pin DIP Small Outline Widebody Type ( Mil) ( Mil) SO ( Mil) Hermetic* Part HCPL- HCPL-J HCPL- HCNW HCPL- Number HCPL- IEC/EN/DIN V IORM = Vpeak V IORM = 9 Vpeak V IORM = Vpeak V IORM = Vpeak EN - (Option ) (Option ) - Approval *Technical data for these products are on separate Agilent publications. Ordering Information Specify Part Number followed by Option Number (if desired). Example: HCPL-#XXXX = UL V rms/ minute Option** for HCPL- Only. = IEC/EN/DIN EN -- Option** for HCPL-/. = Gull Wing Lead Option for HCPL-/J, HCNW. = Tape and Reel Packaging Option XXXE = Lead Free Option Option data sheets are available. Contact Agilent sales representative or authorized distributor for information. **Combination of Option and Option is not available. Remarks: The notation # is used for existing products, while (new) products launched since th July and lead free option will use -
UR Package Outline Drawings HCPL- Outline Drawing 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXZ OPTION CODE* DATE CODE. ±. (. ±.) YYWW UL RECOGNITION.9 (.). ±. (. ±.). (.). (.) TYP.. +. -. (. +.) -.).9 (.) MIN.. (.) MIN.. ±. (. ±.). (.). ±. (. ±.) DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) HCPL- Gull Wing Surface Mount Option Outline Drawing LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.). (.). ±. (. ±.) 9. ±. (. ±.). ±. (. ±.). +. -. (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils)
UR Package Outline Drawings HCPL-J Outline Drawing 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXZ OPTION CODE* DATE CODE. ±. (. ±.) YYWW UL RECOGNITION.9 (.). ±. (. ±.). (.). (.) TYP.. +. -. (. +.) -.).9 (.) MIN.. (.) MIN.. ±. (. ±.). (.). ±. (. ±.) DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION "V" = OPTION OPTION NUMBERS AND NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) HCPL-J Gull Wing Surface Mount Option Outline Drawing LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.). (.). ±. (. ±.) 9. ±. (. ±.). ±. (. ±.). +. -. (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils)
HCPL- Outline Drawing (-Pin Small Outline Package) LAND PATTERN RECOMMENDATION.9 ±. (. ±.) PIN ONE XXX YWW. ±. (. ±.). (.) BSC.99 ±. (. ±.) TYPE NUMBER (LAST DIGITS) DATE CODE. (.).9 (.).9 (.9) *. ±. (. ±.) X. (.). ±. (. ±.). (.) ~. ±. (.9 ±.) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH). ±. (. ±.) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES). (.) MIN.. ±. (. ±.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) HCNW Outline Drawing (-Pin Widebody Package). ±. (. ±.) A HCNWXXXX YYWW TYPE NUMBER DATE CODE. (.) 9. ±. (. ±.). (.) TYP.. (.). (.) TYP.. +. -. (. +.) -.). (.).9 (.). (.) MIN.. (.) TYP.. ±. (. ±.). (.). (.) DIMENSIONS IN MILLIMETERS (INCHES). NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils)
HCNW Gull Wing Surface Mount Option Outline Drawing. ±. (. ±.) LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). (.).9 (.9). (.). ±. (. ±.). (.). (.). ±. (. ±.). (.) BSC DIMENSIONS IN MILLIMETERS (INCHES).. ±. (. ±.) LEAD COPLANARITY =. mm (. INCHES).. ±. (.9 ±.) NOM.. +. -. (. +.) -.) NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils)
Solder Reflow Temperature Profile TEMPERATURE ( C) PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. PEAK TEMP. C SEC. SEC. SEC. PEAK TEMP. C SOLDERING TIME C PEAK TEMP. C ROOM TEMPERATURE TIME (SECONDS) TIGHT TYPICAL LOOSE Recommended Pb-Free IR Profile TEMPERATURE T p +/- C T L C RAMP-UP C/SEC. T smax - C T smin t s PREHEAT to SEC. t p t L TIME WITHIN C of ACTUAL PEAK TEMPERATURE - SEC. RAMP-DOWN C/SEC. to SEC. t C to PEAK TIME NOTES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES T smax = C, T smin = C
Regulatory Information The devices contained in this data sheet have been approved by the following agencies: Agency/Standard HCPL- HCPL-J HCPL- HCNW Underwriters Laboratories (UL) UL Recognized under UL, Component Recognized Program, Category FPQU, File E Canadian Standards Component Association (CSA) Acceptance File CA Notice # Verband Deutscher DIN VDE Electrotechniker (VDE) (June 99) IEC/EN/DIN EN -- Approved under: IEC --:99 + A: EN --: + A: DIN EN -- (VDE Teil ):- Insulation and Safety Related Specifications Value Parameter Symbol HCPL- HCPL-J HCPL- HCNW Units Conditions Minimum External L()...9 9. mm Measured from input Air Gap (External terminals to output Clearance) terminals, shortest distance through air. Minimum External L().... mm Measured from input Tracking (External terminals to output Creepage) terminals, shortest distance path along body. Minimum Internal.... mm Through insulation Plastic Gap distance, conductor to (Internal Clearance) conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Minimum Internal NA NA NA. mm Measured from input Tracking (Internal terminals to output Creepage) terminals, along internal cavity. Tracking Resistance CTI Volts DIN IEC /VDE (Comparative Part Tracing Index) Isolation Group IIIa IIIa IIIa IIIa Material Group (DIN VDE, /9, Table ) All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
9 IEC/EN/DIN EN -- Insulation Related Characteristics HCPL- HCPL- Description Symbol Option Option HCPL-J HCNW Unit Installation classification per DIN VDE /.9, Table for rated mains voltage V rms I-IV I-IV I-IV I-IV for rated mains voltage V rms I-III I-IV I-IV I-IV for rated mains voltage V rms I-III I-III I-IV for rated mains voltage V rms I-III I-IV for rated mains voltage V rms I-III Climatic Classification // // // // Pollution Degree (DIN VDE /.9) Maximum Working V IORM 9 V peak Insulation Voltage Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = V PR V peak sec, Partial Discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and Sample Test, t m = sec, V PR 9 V peak Partial Discharge < pc Highest Allowable Overvoltage* V IOTM V peak (Transient Overvoltage, t ini = sec) Safety Limiting Values maximum values allowed in the event of a failure, also see Thermal Derating curve. Case Temperature T S C Input Current I S INPUT ma Output Power P S OUTPUT mw Insulation Resistance at T S, R S 9 9 9 9 Ω V IO = V *Refer to the optocoupler section of the Designer's Catalog, under regulatory information (IEC/EN/DIN EN --) for a detailed description of Method a and Method b partial discharge test profiles. Note: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Note: Insulation Characteristics are per IEC/EN/DIN EN --. Note: Surface mount classification is Class A in accordance with CECC.
Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T S - C Operating Temperature T A - C Average Input Current [] I F(avg) ma Peak Input Current [] (% duty cycle, ms pulse width) I F(peak) ma Peak Transient Input Current (< µs pulse width, pps) I F(tran). A Reverse Input Voltage (Pin -) HCPL-, HCPL- V R Volts HCPL-J, HCNW Average Output Current (Pin ) I O(avg) ma Resistor Voltage (Pin ) V -. V CC Volts Output Voltage (Pin -) V O -. Volts Supply Voltage (Pin -) V CC -. Volts Output Power Dissipation [] P O mw Total Power Dissipation [] P T mw Lead Solder Temperature (HCPL-, HCPL-J) C for s,. mm below seating plane Lead Solder Temperature (HCNW) C for s (up to seating plane) Infrared and Vapor Phase Reflow Temperature See Package Outline Drawings Section (HCPL- and Option ) Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage V CC. Volts Output Voltage V O Volts Input Current (ON) I F(on) ma Input Voltage (OFF) V F(off) * -. V Operating Temperature T A - C *Recommended V F(OFF) = - V to. V for HCPL-J, HCNW.
Electrical Specifications Over recommended operating conditions unless otherwise specified: T A = - C to + C, V CC = +. V to V, I F(on) = ma to ma, V F(off) = - V to. V Parameter Symbol Device Min. Typ.* Max. Units Test Conditions Fig. Note Current Transfer Ratio CTR 9 % I F = ma, V O =. V Low Level Output Current I OL. 9. ma I F = ma,, V O =. V Low Level Output Voltage V OL.. V I O =. ma Input Threshold Current I TH HCPL-. ma V O =. V, HCPL- I O =. ma HCNW HCPL-J. High Level Output Current I OH µa V F =. V High Level Supply Current I CCH.. ma V F =. V, V O = Open Low Level Supply Current I CCL.. ma I F = ma, V O = Open Input Forward Voltage V F HCPL-.. V I F = ma HCPL- HCPL-J...9 HCNW.. Temperature Coefficient V F / T A HCPL- -. mv/ C I F = ma of Forward Voltage HCPL- HCPL-J HCNW -. Input Reverse Breakdown BV R HCPL- V I R = µa Voltage HCPL- HCPL-J I R = µa HCNW Input Capacitance C IN HCPL- pf f = MHz, HCPL- V F = V HCPL-J HCNW Internal Pull-up Resistor R L kω T A = C, Internal Pull-up Resistor R L / T A. kω/ C Temperature Coefficient *All typical values at C, V CC = V. V F(off) = - V to. V for HCPL-J, HCNW.
Switching Specifications (R L = kω External) Over recommended operating conditions unless otherwise specified: T A = - C to + C, V CC = +. V to V, I F(on) = ma to ma, V F(off) = - V to. V Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Propagation Delay T PHL ns C L = pf I F(on) = ma,,,, Time to Logic HCPL-J V F(off) =. V, -, Low at Output C L = pf V CC =. V, Propagation Delay T PLH ns C L = pf V THLH =. V, Time to High V THHL =. V Output Level C L = pf Pulse Width PWD ns C L = pf Distortion Propagation Delay t PLH -t PHL - ns Difference Between Any Parts Output High Level CM H kv/µs I F = ma, V CC =. V, Common Mode V O >. V C L = pf, Transient Immunity V CM = V p-p Output Low Level CM L kv/µs I F = ma T A = C 9 Common Mode Transient Immunity V O <. V Switching Specifications (R L = Internal Pull-up) Over recommended operating conditions unless otherwise specified: T A = - C to + C, V CC = +. V to V, I F(on) = ma to ma, V F(off) = - V to. V Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Propagation Delay t PHL ns I F(on) = ma, V F(off) =. V,, 9 -, Time to Logic HCPL-J V CC =. V, C L = pf, Low at Output V THLH =. V, V THHL =. V Propagation Delay Time t PLH ns to High Output Level Pulse Width PWD ns Distortion Propagation Delay t PLH -t PHL - ns Difference Between Any Parts Output High Level CM H kv/µs I F = ma, V CC =. V, Common Mode V O >. V C L = pf, Transient Immunity V CM = V p-p, Output Low Level CM L kv/µs I F = ma, T A = C 9 Common Mode V O <. V Transient Immunity Power Supply PSR. V p-p Square Wave, t RISE, t FALL Rejection > ns, no bypass capacitors *All typical values at C, V CC = V. V F(off) = - V to. V for HCPL-J, HCNW.
Package Characteristics Over recommended temperature (T A = - C to C) unless otherwise specified. Parameter Sym. Device Min. Typ.* Max. Units Test Conditions Fig. Note Input-Output Momentary V ISO HCPL- V rms RH < %,, Withstand Voltage HCPL- t = min. HCPL-J T A = C,, HCPL-,9, Option HCNW,9, Resistance R I-O HCPL- V I-O = Vdc (Input-Output) HCPL-J Ω HCPL- HCNW Capacitance C I-O HCPL-. pf f = MHz (Input-Output) HCPL- HCPL-J. HCNW. *All typical values at C, V CC = V. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN -- Insulation Related Characteristics Table (if applicable), your equipment level safety specification or Agilent Application Note entitled Optocoupler Input-Output Endurance Voltage, publication number 9-E. Notes:. Derate linearly above 9 C free-air temperature at a rate of. ma/ C.. Derate linearly above 9 C free-air temperature at a rate of. ma/ C.. Derate linearly above 9 C free-air temperature at a rate of. mw/ C.. Derate linearly above 9 C free-air temperature at a rate of. mw/ C.. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (I O ) to the forward LED input current (I F ) times.. Device considered a two-terminal device: Pins,,, and shorted together and Pins,,, and shorted together.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for second (leakage detection current limit, I I-O µa).. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for second (leakage detection current limit, I i-o µa). 9. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for second (leakage detection current limit, I I-O µa).. This test is performed before the % Production test shown in the IEC/EN/DIN EN -- Insulation Related Characteristics Table, if applicable.. Pulse: f = khz, Duty Cycle = %.. The internal kω resistor can be used by shorting pins and together.. Due to tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved by using an external kω % load resistor. For more information on how propagation delay varies with load resistance, see Figure.. The R L = kω, C L = pf load represents a typical IPM (Intelligent Power Module) load.. See Option data sheet for more information.. Use of a. µf bypass capacitor connected between pins and can improve performance by filtering power supply line noise.. The difference between t PLH and t PHL between any two devices under the same test condition. (See IPM Dead Time and Propagation Delay Specifications section.). Common mode transient immunity in a Logic High level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a Logic High state (i.e., V O >. V). 9. Common mode transient immunity in a Logic Low level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a Logic Low state (i.e., V O <. V).. Pulse Width Distortion (PWD) is defined as t PHL - t PLH for any given device.
I O OUTPUT CURRENT ma V O =. V C C - C NORMALIZED OUTPUT CURRENT...9.9. I F = ma V O =. V. - - I OH HIGH LEVEL OUTPUT CURRENT µa.... V F =. V V CC = V O =. V OR V. V V - - I F FORWARD LED CURRENT ma T A TEMPERATURE C T A TEMPERATURE C Figure. Typical Transfer Characteristics. Figure. Normalized Output Current vs. Temperature. Figure. High Level Output Current vs. Temperature. I F FORWARD CURRENT ma...... HCPL-/ V F + I F T A = C... V F FORWARD VOLTAGE VOLTS. I F INPUT FORWARD CURRENT ma.. T A = C V F + HCPL-J/HCNW I F........ V F INPUT FORWARD VOLTAGE V Figure. HCPL- and HCPL- Input Current vs. Forward Voltage. Figure. HCPL-J and HCNW Input Current vs. Forward Voltage. I F(ON) = ma + V kω. µf C L * kω V OUT + V CC = V I f V O t f 9% 9% t r V THHL % % V THLH *TOTAL LOAD CAPACITANCE t PHL t PLH Figure. Propagation Delay Test Circuit.
V CM B I F A kω. µf kω V OUT + V CC = V OV t δv δt = V CM t V FF + pf* * pf TOTAL CAPACITANCE V O SWITCH AT A: I F = ma V O SWITCH AT B: I F = ma V CC V OL + V CM = V Figure. CMR Test Circuit. Typical CMR Waveform. t P PROPAGATION DELAY ns t PLH t PHL I F = ma V CC = V CL = pf RL = kω (EXTERNAL) - - T A TEMPERATURE C t P PROPAGATION DELAY ns I F = ma V CC = V CL = pf RL = kω (INTERNAL) T A TEMPERATURE C t PLH t PHL - - t P PROPAGATION DELAY ns I F = ma V CC = V CL = pf T A = C t PLH t PHL RL LOAD RESISTANCE kω Figure. Propagation Delay with External kω RL vs. Temperature. Figure 9. Propagation Delay with Internal kω RL vs. Temperature. Figure. Propagation Delay vs. Load Resistance. t P PROPAGATION DELAY ns I F = ma V CC = V RL = kω T A = C t PLH t PHL CL LOAD CAPACITANCE pf t P PROPAGATION DELAY ns I F = ma CL = pf RL = kω T A = C t PLH t PHL V CC SUPPLY VOLTAGE V t P PROPAGATION DELAY ns t PLH t PHL V CC = V CL = pf RL = kω T A = C I F FORWARD LED CURRENT ma Figure. Propagation Delay vs. Load Capacitance. Figure. Propagation Delay vs. Supply Voltage. Figure. Propagation Delay vs. Input Current.
OUTPUT POWER P S, INPUT CURRENT I S () HCPL- OPTION /HCPL-J P S (mw) I S (ma) FOR HCPL- OPTION I S (ma) FOR HCPL-J T S CASE TEMPERATURE C OUTPUT POWER P S, INPUT CURRENT I S 9 () HCPL- OPTION /HCNW P S (mw) FOR HCNW I S (ma) FOR HCNW P S (mw) FOR HCPL- OPTION I S (ma) FOR HCPL- OPTION T S CASE TEMPERATURE C Figure. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN --. + V kω. µf kω + V CC = V C LEDP kω CMOS Ω pf V OUT C LEDN * pf TOTAL CAPACITANCE Figure. Recommended LED Drive Circuit. Figure. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. + V kω C LEDP C LED kω. µf C LED Ω kω + V CC = V C LEDN CMOS pf V OUT * pf TOTAL CAPACITANCE Figure. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. Figure. LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended).
I TOTAL* Ω I CLEDP C LED I F C LEDP I CLED C LEDN kω C LED V OUT kω pf Ω + V R ** C LEDP C LED C LEDN I CLEDN* kω C LED V OUT kω pf * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. + V CM * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. ** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH PERFORMANCE. V R < V F (OFF) DURING +dv CM /dt. + V CM Figure 9. AC Equivalent Circuit for Figure During Common Mode Transients. Figure. AC Equivalent Circuit for Figure During Common Mode Transients. + V kω Q C LEDP C LED C LEDN I CLEDN* kω C LED V OUT kω pf Q * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. + V CM Figure. Not Recommended Open Collector LED Drive Circuit. Figure. AC Equivalent Circuit for Figure During Common Mode Transients. + V kω Figure. Recommended LED Drive Circuit for Ultra High CMR.
HCPL- V CC + V I LED kω. µf kω IPM +HV Ω V OUT CMOS Q M HCPL- V CC HCPL- Q + V I LED kω. µf kω HCPL- HCPL- -HV Ω V OUT HCPL- CMOS HCPL- Figure. Typical Application Circuit. I LED V OUT V OUT Q ON Q OFF Q OFF Q ON I LED I LED V OUT V OUT I LED Q ON Q OFF t PLH Q OFF Q ON t PLH MIN. t PLH PDD* t PHL MIN. t PHL DEAD TIME t PHL MIN. PDD* = (t PLH- t PHL ) = t PLH - t PHL MIN. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE PDD ARE TAKEN AT EQUAL TEMPERATURES. MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PLH - t PLH MIN. ) + (t PHL - t PHL MIN. ) = (t PLH - t PHL MIN. ) - (t PLH MIN. - t PHL ) = PDD* - PDD* MIN. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES. Figure. Minimum LED Skew for Zero Dead Time. Figure. Waveforms for Dead Time Calculation.
9 LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure. The HCPL- series improve CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pins and output ground as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure ), can achieve kv/µs CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure to keep the LED off when the gate is in the high state. Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through C LEDO and C LEDO in Figure. Many factors influence the effect and magnitude of the direct coupling including: the use of an internal or external output pull-up resistor, the position of the LED current setting resistor, the connection of the unused input package pins, and the value of the capacitor at the optocoupler output (C L ). Techniques to keep the LED in the proper state and minimize the effect of the direct coupling are discussed in the next two sections. CMR with the LED On (CMR L ) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of ma provides adequate margin over the maximum I TH of. ma (see Figure ) to achieve kv/µs CMR. Capacitive coupling is higher when the internal load resistor is used (due to C LEDO ) and an I F = ma is required to obtain kv/µs CMR. The placement of the LED current setting resistor effects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to the optocoupler output. For example, the LED resistor in Figure is connected to the anode. Figure 9 shows the AC equivalent circuit for Figure during common mode transients. During a +dvcm/dt in Figure 9, the current available at the LED anode (Itotal) is limited by the series resistor. The LED current (I F ) is reduced from its DC value by an amount equal to the current that flows through C LEDP and C LEDO. The situation is made worse because the current through C LEDO has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure ) places the current setting resistor in series with the LED cathode. Figure is the AC equivalent circuit for Figure during common mode transients. In this case, the LED current is not reduced during a +dvcm/dt transient because the current flowing through the package capacitance is supplied by the power supply. During a -dvcm/dt transient, however, the LED current is reduced by the amount of current flowing through C LEDN. But, better CMR performance is achieved since the current flowing in C LEDO during a negative transient acts to keep the output low. Coupling to the LED and output pins is also affected by the connection of pins and. If CMR is limited by perturbations in the LED on current, as it is for the recommended drive circuit (Figure ), pins and should be connected to the input circuit common. However, if CMR performance is limited by direct coupling to the output when the LED is off, pins and should be left unconnected. CMR with the LED Off (CMR H ) A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a +dvcm/dt transient in Figure, the current flowing through C LEDN is supplied by the parallel combination of the LED and series resistor. As long as the voltage developed across the resistor is less than V F(OFF) the
LED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the pf capacitor from pins - will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure ) provides about V of margin between the lowest optocoupler output voltage and a V IPM threshold during a kv/µs transient with V CM = V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in Figure, to clamp the voltage across the LED below V F(OFF). Since the open collector drive circuit, shown in Figure, cannot keep the LED off during a +dvcm/dt transient, it is not desirable for applications requiring ultra high CMR H performance. Figure is the AC equivalent circuit for Figure during common mode transients. Essentially all the current flowing through C LEDN during a +dvcm/dt transient must be supplied by the LED. CMR H failures can occur at dv/dt rates where the current through the LED and C LEDN exceeds the input threshold. Figure is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state. IPM Dead Time and Propagation Delay Specifications The HCPL- series include a Propagation Delay Difference specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q and Q in Figure ) are off. Any overlap in Q and Q conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the IPM IGBT gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn-on (t PHL ) and turn-off (t PLH ) propagation delay specifications, preferably over the desired operating temperature range. The limiting case of zero dead time occurs when the input to Q turns off at the same time that the input to Q turns on. This case determines the minimum delay between LED turn-off and LED turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in Figure. A minimum dead time of zero is achieved in Figure when the signal to turn on LED is delayed by (t PLH max - t PHL min ) from the LED turn off. Note that the propagation delays used to calculate PDD are taken at equal temperatures since the optocouplers under consideration are typically mounted in close proximity to each other. (Specifically, t PLH max and t PHL min in the previous equation are not the same as the t PLH max and t PHL min, over the full operating temperature range, specified in the data sheet.) This delay is the maximum value for the propagation delay difference specification which is specified at ns for the HCPL- series over an operating temperature range of - C to C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest t PLH and another with the slowest t PHL are in the same inverter leg. The maximum dead time in this case becomes the sum of the spread in the t PLH and t PHL propagation delays as shown in Figure. The maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. The maximum dead time (due to the optocouplers) for the HCPL- series is ns (= ns - (- ns) ) over an operating temperature range of - C to C.
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