PSP model update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen (NXP Semiconductors) Ramses van der Toorn (Delft University of Technology) MOS-AK, San Francisco 12 December 2012
outline some history brief overview of PSP benefits for analog/rf design recent updates simulation speed (not shown) self heating improved thermal noise model implementation summary 2
history PSP is available as built-in model in all major circuit simulators Verilog-A code & documentation available from http://psp.ewi.tudelft.nl C-code (SiMKit) available from http://www.nxp.com/models 2005: PSP created by merging SP (Pennsylvania State University) and MOS Model 11 (Philips) 2005: PSP 102 is elected as CMC standard MOS model Arizona State University (formerly PennState): supporting institution NXP Semiconductors (formerly Philips): co-developer 2005-2010: several model improvements, introduction of PSP103 2011 cooperation CMC and Arizona State University ends NXP and Delft University of Technology start cooperation on PSP 2012 CMC re-instates PSP as CMC-standard model Delft University of Technology (Prof. Ramses v.d. Toorn): supporting institution December: first PSP release (103.2) from Delft University of Technology PSP-update, MOS-AK 12 December 2012 3
outline some history brief overview of PSP benefits for analog/rf design recent updates simulation speed (not shown) self heating improved thermal noise model implementation summary 4
s (V) oxide core model: surface potential calculation Poisson equation + Gauss s law leads to implicit equation for ψ s V GB V FB o s 2 e s B V e T e ψ s can be calculated with iterative methods (HiSIM, MM1102) with analytical approximations (PSP, SP, MM1101) PSP: explicit analytical approximation accuracy <1nV under all relevant conditions) T T s T s 1 T 1 1.2 0.8 0.4 0-0.4 gate ψ s E C E V substrate V = 0 V -1 0 1 2 V GB - V FB (V) 5
I D I D (ma) g DS g DS (A/V) long channel output conductance crucial for analog design! 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 V DS (V) I D -V DS and g DS -V DS for V SB =0V and T=25 C 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 0.0 0.2 0.4 0.6 0.8 1.0 V DS (V) V DS (V) symbols measurements lines PSP simulations 10µm/1µm NMOS (65nm process technology) 6
(A/V i g DSi DSi (A/V i ) m (A/V i ) g i mi (A/V i ) higher order conductance crucial for distortion (IP3) modeling g DSi (= i I D / V DSi ) vs. V DS measurement PSP g mi (= i I D / V GSi ) vs. V GS 10-1 g DS3 10-1 g m3 10-2 10-3 g DS2 g DS1 V GS =1.2V 10-2 10-3 10-4 10-5 g m1 V DS =1.2V g m2 0.0 0.3 0.6 0.9 0.0 0.4 0.8 1.2 V DS DS (V) 10/0.12 NMOS VV GS GS (V) good results due to PSP s mobility model and implementation of SCEs 7
I G (A) leakage: gate current 3 components: gate-to-channel current gate-overlap current gate-to-bulk current S I G I GS IGB I GOV I GD D 1.E-09 1.E-10 1.E-11 1.E-12 1.E-13 I GB Measurements measurements MM11 model 1.E-14-1.5-1 -0.5 0 0.5 1 1.5 V GS (V) I GOV I GS + I GD PSP features dynamic (bias dependent) S/D-partitioning of gate current 8
I gate-edge (A/m) I gate-edge (A/m) leakage: junction current 10-4 NMOS 10-4 PMOS T=200 0 C 10-6 BBT 10-6 10-8 10-8 T=-40 0 C 10-10 10-12 65nm technology 10-10 10-12 BBT -2.0-1.5-1.0-0.5 0 0.5-2.0-1.5-1.0-0.5 0 0.5 junction voltage (V) junction voltage (V) advanced CMOS: increasing importance of BBT 9
Non-quasi-static effects Im( Y 11) ( 1 ) 10-1 10-2 10-3 imag(y11) L=2um (90nm technology), NMOS, various V GS Im( Y 21) ( 1 ) 10-1 10-2 10-3 10-4 imag(y21) measurement PSP 10-4 V DS = 1. 2 V 10 7 10 8 10 9 10 10 10 11 10 12 F (Hz) 10-5 V DS = 1. 2 V 10 7 10 8 10 9 10 10 10 11 10 12 F (Hz) PSP NQS model based on spline collocation method predictive model (no parameter extraction needed) based on same physics as segmentation more computationally efficient 10
phase noise (dbc/hz) phase noise (dbc/hz) thermal noise modeling thermal noise originates from resistive nature of MOSFET channel PSP has a predictive model for thermal noise based on pure thermal noise includes drain current noise, induced gate noise, and correlation proper integration along channel, correct transfer to terminals valid in all operating regions (linear, saturation, sub-threshold) -70-80 Digitally controlled oscillator (center frequency 3.43 GHz) PSP with induced gate noise measurements induced gate noise correlation -90-100 PSP w/o induced gate noise 10-1 10 0 10 1 ofoffset fset frequenc frequency y (MHz) source local noise source gate drain drain current noise 11
outline some history brief overview of PSP benefits for analog/rf design recent updates simulation speed (not shown) self heating improved thermal noise model implementation summary 12
new in PSP: self heating (i) motivation: create possibility to use PSP in macro model for DMOS devices possibly also useful for normal high-power devices useful when analyzing simulation/measurement discrepancies simple RC thermal network, external thermal node V(dt)=ΔT I 0 = P diss = I ds * V ds +... dt I 0 R th C th 13
new in PSP: self heating (ii) identical parameter sets; with and without self heating Id vs. Vd PSP103 PSP103t gds vs. frequency (dc-simulation) (ac-simulation) 14
new in PSP: self heating (iii) Vds=2V, pulse Vgs 02V and 20V PSP103 PSP103t ΔT (tr-simulation) 15
outline some history brief overview of PSP benefits for analog/rf design recent updates simulation speed (not shown) self heating improved thermal noise model implementation summary 16
new in PSP: improved noise implementation (i) simplified verilog-a implementation originally: three independent white noise sources (+ four controlled sources) new: two independent white noise sources (+ four controlled sources) two independent sources are sufficient to create two (partially) correlated sources noise powers and transfer ratios adjusted to ensure unchanged results noise powers now all have physical values 17
new in PSP: improved noise implementation (ii) improved symmetry PSP 103.1.1 and before: S ig -source changes location when V ds crosses 0 causes a discontinuity in drain current noise around V ds =0 only visible at very high frequency thought to be harmless recently found that this may cause non-convergence in transient noise analysis S ig s g V ds > 0 d s V ds < 0 g d S ig N.B. V X on drain, -V X on source 18
new in PSP: improved noise implementation (iii) solution: induced gate noise partitioning over source and drain fully physical, bias-dependent, partitioning seems over-the-top PSP103.2: 50/50 partitioning (removes discontinuity and solves convergence issue) g S ig /2 S ig /2 s all V ds d older PSP PSP 103.2 PSP 103.2 N.B. A truly symmetrical plot is obtained when plotting S Id +S Is, but such a plot fails to show the original problem in S Id itself! 19
new in PSP: improved noise implementation (iv) bonus from 50/50 partitioning: 1 st -order NQS effect in S id! explanation: induced gate noise is essentially a NQS effect same effect gives f-dependence on S id old model (PSP103.1.1 and before): induced gate noise source between g & s no NQS effect in drain current noise new model (PSP 103.2.0): 50/50 partitioning induced-gate noise partly flows to drain correct 1 st -order f-dependence in S id! comparison of segmentation (1, 2, 4, 8 segments) with 1-segment model with 50/50 partitioning 20
summary PSP is re-instated as CMC-standard model supporting institution: Delft University of Technology Prof. Ramses van der Toorn also hosts MEXTRAM model co-developer: NXP Semiconductors new PSP 103.2 recently released improved simulation speed self heating improved implementation of thermal noise model 21 PSP-update, MOS-AK 12 December 2012
self heating: scaling geometrical scaling adapted from first version: more PSP-like parameter names and constant term added T-scaling for RTH exponential T-scaling with parameter STRTH base on ambient temperature (not device-t), to avoid convergence issues 23
induced gate noise & S/D interchange (iv) For comparison: BSIM4, 4.7, tnoimod=2 same problem as previously in PSP, but smaller magnitude in BSIM4, induced gate noise is limited to 2x drain current noise as a consequence, discontinuity cannot be larger than factor of 2 24