DUA DECADE ER; DUA -STAGE BINARY ER The SN5/7S and SN5/7S each contain a pair of high-speed -stage ripple counters. Each half of the S is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input for each section. The two sectio can be connected to count in the... BCD code or they can count in a biquinary sequence to provide a square wave (5% duty cycle) at the final output. Each half of the S operates as a Modulo-6 binary divider, with the last three stages triggered in a ripple fashion. In both the S and the S, the flip-flops are triggered by a IG-to-OW traition of their CP inputs. Each half of each circuit type has a Master Reset input which responds to a IG signal by forcing all four outputs to the OW state. Dual Versio of S and S S has Separate Clocks Allowing,.5, 5 Individual Asynchronous Clear for Each Counter Typical Max Count Frequency of 5 Mz Input Clamp Diodes Minimize igh Speed Termination Effects SN5/7S SN5/7S DUA DECADE ER; DUA -STAGE BINARY ER 6 6 OW POWER SCOTTKY J SUFFIX CERAMIC CASE 6- N SUFFIX PASTIC CASE 6- CONNECTION DIAGRAM DIP (TOP VIEW) SN5/ 7S 6 D SUFFIX SOIC CASE 75B- J SUFFIX CERAMIC CASE 6- SN5/ 7S NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. N SUFFIX PASTIC CASE 66-6 D SUFFIX SOIC CASE 75A- ORDERING INFORMATION SN5SXXXJ Ceramic SN7SXXXN Plastic SN7SXXXD SOIC FAST AND S TT DATA 5-5
SN5/7S SN5/7S PIN NAMES OADING (Note a) IG OW CP Clock (Active OW going edge) Input to +6 (S).5 U... U.. CP Clock (Active OW going edge) Input to (S).5 U... U.. CP Clock (Active OW going edge) Input to 5 (S).5 U...5 U.. MR Master Reset (Active IG) Input.5 U...5 U.. Q Q Flip-Flop outputs (Note b) U.. 5 (.5) U.. NOTES: a) TT Unit oad (U..) = µa IG/.6 ma OW. b) The Output OW drive factor is.5 U.. for Military (5) and 5 U.. for Commercial (7) b) Temperature Ranges. FUNCTIONA DESCRIPTION Each half of the SN5/7S operates in the Modulo 6 binary sequence, as indicated in the 6 Truth Table. The first flip-flop is triggered by IG-to-OW traitio of the CP input signal. Each of the other flip-flops is triggered by a IG-to-OW traition of the Q output of the preceding flip-flop. Thus state changes of the Q outputs do not occur simultaneously. This mea that logic signals derived from combinatio of these outputs will be subject to decoding spikes and, therefore, should not be used as clocks for other counters, registers or flip-flops. A IG signal on MR forces all outputs to the OW state and prevents counting. Each half of the S contai a 5 section that is independent except for the common MR function. The 5 section operates in.. binary sequence, as shown in the 5 Truth Table, with the third stage output exhibiting a % duty cycle when the input frequency is cotant. To obtain a function having a 5% duty cycle output, connect the input signal to CP and connect the Q output to the CP input; the Q output provides the desired 5% duty cycle output. If the input frequency is connected to CP and the Q output is connected to CP, a decade divider operating in the... BCD code is obtained, as shown in the BCD Truth Table. Since the flip-flops change state asynchronously, logic signals derived from combinatio of S outputs are also subject to decoding spikes. A IG signal on MR forces all outputs OW and prevents counting. SN5/ 7S OGIC DIAGRAM (one half shown) SN5/ 7S OGIC DIAGRAM (one half shown) FAST AND S TT DATA 5-55
SN5/7S SN5/7S SN5/7S BCD TRUT TABE (Input on CP; Q CP) SN5/7S 5 TRUT TABE (Input on CP) SN5/ 7S TRUT TABE Q Q Q Q Q Q Q Q Q Q Q 5 6 7 SN5/7S (5% @ Q) TRUT TABE (Input on CP, Q to CP) Q Q Q Q 5 6 7 5 5 = IG Voltage evel = OW Voltage evel 6 7 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 5 7.5.75 5. 5. 5.5 5.5 V TA Operating Ambient Temperature Range 5 7 55 5 5 5 7 C IO Output Current igh 5, 7. ma IO Output Current ow 5 7.. ma FAST AND S TT DATA 5-56
SN5/7S SN5/7S DC CARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits Symbol Parameter Min Typ Max Unit Test Conditio VI Input IG Voltage. V VI Input OW Voltage 5.7 7. V Guaranteed Input IG Voltage for All Inputs Guaranteed Input OW Voltage for All Inputs VIK Input Clamp Diode Voltage.65.5 V VCC = MIN, IIN = ma VO VO Output IG Voltage Output OW Voltage 5.5.5 V VCC = MIN, IO = MAX, VIN = VI 7.7.5 V or VI per Truth Table 5, 7.5. V IO =. ma VCC = VCC MIN, VIN = VI or VI 7.5.5 V IO =. ma per Truth Table II Input IG Current MR. ma µa VCC = MAX, VIN =.7 V. ma VCC = MAX, VIN = 7. V II Input OW Current CP, CP.6 ma VCC = MAX, VIN =. V CP. ma IOS Short Circuit Current (Note ) ma VCC = MAX ICC Power Supply Current 6 ma VCC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CARACTERISTICS (TA = 5C, VCC = 5. V) imits Symbol Parameter Min Typ Max Unit Test Conditio fmax Maximum Clock Frequency CP to Q 5 5 Mz fmax Maximum Clock Frequency CP to Q Mz tp tp Propagation Delay, CP to Q S tp tp CP to Q S tp tp tp tp CP to Q CP to Q S S 7 6 6 6 6 C = 5 pf tp tp CP to Q S tp tp CP to Q S 6 tp tp CP to Q S tp MR to Any Output S/ FAST AND S TT DATA 5-57
SN5/7S SN5/7S AC SETUP REQUIREMENTS (TA = 5C, VCC = 5. V) imits Symbol Parameter Min Typ Max Unit Test Conditio tw Clock Pulse Width S tw CP Pulse Width S tw CP Pulse Width S VCC = 5. V tw MR Pulse Width S/ trec Recovery Time S/ 5 AC WAVEFORMS Figure Figure *The number of Clock Pulses required between t P and t P measurements can be determined from the appropriate Truth Table. FAST AND S TT DATA 5-5
-A- Case 75B- D Suffix 6-Pin Plastic SO-6 6 -B- P -T- D G K C M R X 5 F J -A- Case 6- N Suffix 6-Pin Plastic 6 B F S C -T- G D K J M -A- Case 6- J Suffix 6-Pin Ceramic Dual In-ine 6 -B- C -T- K E N F G J D M FAST AND S TT DATA 5-5
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