Daashee, Version 2.1, 30 Jun 2006 PWM-FF IC ICE2AS01/S01G Off-Line SMPS Curren Mode Conroller Power Managemen & Supply Never sop hinking.
Revision Hisory: 2006-06-30 Daashee Previous Version: V2.0 Page Subjecs (major changes since las revision) 3,5,15,23 updae o PB-free package For quesions on echnology, delivery and prices please conac he Infineon Technologies Offices in Germany or he Infineon Technologies Companies and Represenaives worldwide: see our webpage a hp:// www.infineon.com CoolMOS, CoolSET are rademarks of Infineon Technologies AG. We Lisen o Your Commens Any informaion wihin his documen ha you feel is wrong, unclear or missing a all? Your feedback will help us o coninuously improve he qualiy of his documen. Please send your proposal (including a reference o his documen) o: mcdocu.commens@infineon.com Ediion 2006-06-30 Published by Infineon Technologies AG, S.-Marin-Srasse 53, D-81541 München Infineon Technologies AG 1999. All Righs Reserved. Aenion please! The informaion herein is given o describe cerain componens and shall no be considered as warraned characerisics. Terms of delivery and righs o echnical change reserved. We hereby disclaim any and all warranies, including bu no limied o warranies of non-infringemen, regarding circuis, descripions and chars saed herein. Infineon Technologies is an approved CECC manufacurer. Informaion For furher informaion on echnology, delivery erms and condiions and prices please conac your neares Infineon Technologies Office in Germany or our Infineon Technologies Represenaives worldwide (see address lis). Warnings Due o echnical requiremens componens may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies Office. Infineon Technologies Componens may only be used in life-suppor devices or sysems wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem, or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body, or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.
Off-Line SMPS Curren Mode Conroller Produc Highlighs Enhanced Proecion Funcions all wih Auo Resar Lowes Sandby Power Dissipaion Very Accurae Curren Limiing PB-free Plaing and RoHS complian P-DIP-8-4 PG-DIP-8 P-DSO-8-3 PG-DSO-8 Feaures Only few exernal Componens required Inpu Undervolage Lockou 67kHz/100kHz fixed Swiching Frequency Max Duy Cycle 72% Low Power Sandby Mode o suppor Blue Angel Norm Lached Thermal Shu Down Overload and Open Loop Proecion Overvolage Proecion during Auo Resar Adjusable Peak Curren Limiaion via Exernal Resisor Overall Tolerance of Curren Limiing < ±5% Inernal Leading Edge Blanking Sof Sar Sof gae driving for Low EMI Descripion This sand alone conroller provides several special enhancemens o saisfy he needs for low power sandby and proecion feaures. In sandby mode frequency reducion is used o lower he power consumpion and provide a sable oupu volage in his mode. The frequency reducion is limied o 20kHz / 21.5 khz (yp.) o avoid audible noise. In case of failure modes like open loop, overvolage or overload due o shor circui he device swiches in Auo Resar Mode which is conrolled by he inernal proecion uni. By means of he inernal precise peak curren limiaion he dimension of he ransformer and he secondary diode can be lower which leads o more cos efficiency. Typical Applicaion + 85... 270 VAC R Sar-up Snubber Converer DC Oupu - VCC C VCC Low Power SandBy Power Managemen Feedback C Sof Sar SofS Sof-Sar Conrol PWM Conroller Curren Mode Precise Low Tolerance Peak Curren Limiaion Gae Isense FB Proecion Uni GND R Sense Feedback ICE2AS01(G) / ICE2BS01(G) Type Frequency Package ICE2AS01 100kHz PG-DIP-8 ICE2AS01G 100kHz PG-DSO-8 ICE2BS01 67kHz PG-DIP-8 ICE2BS01G 67kHz PG-DSO-8 Daashee 3 30 Jun 2006
Table of Conens Page 1 Pin Configuraion and Funcionaliy.............................5 1.1 Pin Configuraion..............................................5 1.2 Pin Funcionaliy..............................................5 2 Represenaive Blockdiagram..................................6 3 Funcional Descripion........................................7 3.1 Power Managemen............................................7 3.2 Improved Curren Mode.........................................7 3.2.1 PWM-OP..................................................8 3.2.2 PWM-Comparaor...........................................8 3.3 Sof-Sar....................................................9 3.4 Oscillaor and Frequency Reducion..............................10 3.4.1 Oscillaor.................................................10 3.4.2 Frequency Reducion........................................10 3.5 Curren Limiing..............................................10 3.5.1 Leading Edge Blanking......................................10 3.5.2 Propagaion Delay Compensaion..............................11 3.6 PWM-Lach.................................................11 3.7 Driver......................................................11 3.8 Proecion Uni (Auo Resar Mode)..............................12 3.8.1 Overload & Open loop wih normal load.........................12 3.8.2 Overvolage due o open loop wih no load.......................13 3.8.3 Thermal Shu Down.........................................14 4 Elecrical Characerisics.....................................15 4.1 Absolue Maximum Raings.....................................15 4.2 Operaing Range.............................................15 4.3 Characerisics...............................................16 4.3.1 Supply Secion.............................................16 4.3.2 Inernal Volage Reference...................................16 4.3.3 Conrol Secion............................................16 4.3.4 Proecion Uni.............................................17 4.3.5 Curren Limiing............................................17 4.3.6 Driver Secion.............................................17 5 Typical Performance Characerisics...........................19 6 Ouline Dimension...........................................23 Daashee 4 30 Jun 2006 Preliminary Daa
1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion 1.2 Pin Funcionaliy Pin Symbol Funcion 1 N.C. No conneced 2 SofS Sof Sar & Auo Resar Conrol 3 FB Regulaion Feedback 4 Isense Conroller Curren Sense Inpu 5 Gae Driver Oupu 6 VCC Conroller Supply Volage 7 GND Conroller Ground 8 N.C. No conneced Package PG-DIP-8 G-Package PG-DSO-8 SofS (Sof Sar & Auo Resar Conrol) This pin combines he funcion of Sof Sar in case of Sar Up and Auo Resar Mode and he conrolling of he Auo Resar Mode in case of an error deecion. FB (Feedback) The informaion abou he regulaion is provided by he FB Pin o he inernal Proecion Uni and o he inernal PWM-Comparaor o conrol he duy cycle. Isense (Curren Sense) The Curren Sense pin senses he volage developed on he series resisor insered in he source of he exernal Power Swich. When Isense reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is disabled. By his mean he Over Curren Deecion is realized. Furhermore he curren informaion is provided for he PWM-Comparaor o realize he Curren Mode. N.C. 1 8 N.C. Gae (Driver Oupu) The curren and slew rae capabiliy of his pin are suied o drive Power MOSFETs. SofS FB Isense 2 3 4 7 6 5 GND VCC Gae VCC (Power supply) This pin is he posiive supply of he IC. The operaing range is beween 8.5V and 21V. To provide overvolage proecion he driver ges disabled when he volage becomes higher han 16.5V during Sar up Phase. Figure 1 Pin Configuraion (op view) GND (Ground) This pin is he ground of he primary side of he SMPS. Daashee 5 30 Jun 2006 Preliminary Daa
Represenaive Blockdiagram 2 Represenaive Blockdiagram 85... 270 VAC SofS C Sof-Sar FB T1 R Sar-up VCC 16.5V C1 6.5V 4.0V C2 G1 R Sof-Sar 5.6V C4 5.3V G2 6.5V R FB 4.8V C3 Thermal Shudown T j >140 C Proecion Uni ICE2AS01(G) / ICE2BS01(G) GND C Line C VCC Undervolage Lockou 13.5V Power Managemen Inernal Bias 8.5V Power-Down Rese Power-Up Rese Volage Reference 6.5V 5.3V 4.8V 4.0V Oscillaor Duy Cycle max Clock 0.72 Sof Sar Sof-Sar Comparaor PWM-Lach S Q G3 f norm f sandby Spike Blanking 5µs f osc Sandby Uni S Q R Q Error-Lach U FB 0.3V 0.8V PWM Comparaor C5 x3.65 PWM OP Improved Curren Mode G4 Curren-Limi Comparaor Propagaion-Delay Compensaion Curren Limiing R Q V csh Gae Driver Leading Edge Blanking 200ns 10kΩ D1 Frequency in Normal Mode f norm : ICE2BS01(G) ICE2AS01(G) 67kHz 100kHz Frequency in Sandby Mode f sandby : 20kHz 21.5kHz Snubber Gae Isense R Sense Opocoupler + Converer DC Oupu V OUT - Figure 2 Daashee 6 30 Jun 2006
Funcional Descripion 3 Funcional Descripion 3.1 Power Managemen 3.2 Improved Curren Mode Main Line (100V-380V) Sof-Sar Comparaor R Sar-Up Primary Winding C VCC VCC Power Managemen Undervolage Lockou Inernal Bias 13.5V 8.5V Power-Down Rese 6.5V 5.3V Volage 4.8V Reference Power-Up 4.0V Rese R Q PWM-Lach 6.5V S Q R Sof-Sar SofS Error-Lach Sof-Sar Comparaor C Sof-Sar T1 Error-Deecion FB 0.8V PWM Comparaor PWM OP x3.65 Improved Curren Mode PWM-Lach Figure 4 Curren Mode Curren Mode means ha he duy cycle is conrolled by he slope of he primary curren. This is done by comparison he FB signal wih he amplified curren sense signal. R S Q Q Isense Driver Amplified Curren Signal Figure 3 Power Managemen The Undervolage Lockou moniors he exernal supply volage V VCC. In case he IC is inacive he curren consumpion is max. 55µA. When he SMPS is plugged o he main line he curren hrough R Sar-up charges he exernal Capacior C VCC. When V VCC exceeds he on-hreshold V CCon =13.5V he inernal bias circui and he volage reference are swiched on. Afer i he inernal bandgap generaes a reference volage V REF =6.5V o supply he inernal circuis. To avoid unconrolled ringing a swich-on a hyseresis is implemened which means ha swich-off is only afer acive mode when Vcc falls below 8.5V. In case of swich-on a Power Up Rese is done by reseing he inernal error-lach in he proecion uni. When V VCC falls below he off-hreshold V CCoff =8.5V he inernal reference is swiched off and he Power Down rese le T1 discharging he sof-sar capacior C Sof-Sar a pin SofS. Thus i is ensured ha a every swich-on he volage ramp a pin SofS sars a zero. FB 0.8V Driver T on Figure 5 Pulse Widh Modulaion In case he amplified curren sense signal exceeds he FB signal he on-ime T on of he driver is finished by reseing he PWM-Lach (see Figure 5). Daashee 7 30 Jun 2006 Preliminary Daa
Funcional Descripion The primary curren is sensed by he series resisor R Sense insered in he source of he exernal Power Swich. By means of Curren Mode he regulaion of he secondary volage is insensiive on line variaions. Line variaion causes variaion of he increasing curren slope which conrols he duy cycle. The exernal R Sense allows an individual adjusmen of he maximum source curren of he exernal Power Swich. V OSC max. Duy Cycle Sof-Sar Comparaor PWM Comparaor FB PWM-Lach Volage Ramp 0.8V FB 0.3V Oscillaor V OSC 0.3V C5 Gae Driver Gae Driver T 2 R 1 C 1 0.8V 10kΩ 20pF V 1 x3.65 PWM OP Figure 7 Ligh Load Condiions Volage Ramp Figure 6 Improved Curren Mode To improve he Curren Mode during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T 2, he volage source V 1 and he 1s order low pass filer composed of R 1 and C 1 (see Figure 6, Figure 7). Every ime he oscillaor shus down for max. duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he Gae Driver T2 is opened so ha he volage ramp can sar (see Figure 7). In case of ligh load he amplified curren ramp is o small o ensure a sable regulaion. In ha case he Volage Ramp is a well defined signal for he comparison wih he FB-signal. The duy cycle is hen conrolled by he slope of he Volage Ramp. By means of he C5 Comparaor he Gae Driver is swiched-off unil he volage ramp exceeds 0.3V. I allows he duy cycle o be reduced coninuously ill 0% by decreasing V FB below ha hreshold. 3.2.1 PWM-OP The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor R Sense conneced o pin ISense. R Sense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.65 by PWM OP. The oupu of he PWM-OP is conneced o he volage source V1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM- Comparaor, C5 and he Sof-Sar-Comparaor. 3.2.2 PWM-Comparaor The PWM-Comparaor compares he sensed curren signal of he exernal Power Swich wih he feedback signal V FB (see Figure 8). V FB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pullup resisor R FB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he exernal Power Swich exceeds he signal V FB he PWM-Comparaor swiches off he Gae Driver. Daashee 8 30 Jun 2006 Preliminary Daa
Funcional Descripion R FB FB Opocoupler 6.5V Sof-Sar Comparaor PWM-Lach PWM Comparaor 0.8V PWM OP Isense x3.65 pullup resisor R Sof-Sar. The Sof-Sar-Comparaor compares he volage a pin SofS a he negaive inpu wih he ramp signal of he PWM-OP a he posiive inpu. When Sof-Sar volage V SofS is less han Feedback volage V FB he Sof-Sar-Comparaor limis he pulse widh by reseing he PWM-Lach (see Figure 9). In addiion o Sar-Up, Sof-Sar is also acivaed a each resar aemp during Auo Resar. By means of he above menioned C Sof-Sar he Sof-Sar can be defined by he user. The Sof-Sar is finished when V SofS exceeds 5.3V. A ha ime he Proecion Uni is acivaed by Comparaor C4 and senses he FB by Comparaor C3 weher he volage is below 4.8V which means ha he volage on he secondary side of he SMPS is seled. The inernal Zener Diode a SofS wih breakhrough volage of 5.6V is o preven he inernal circui from sauraion (see Figure 10). 5.6V 6.5V Power-Up Rese Improved Curren Mode SofS R Sof-Sar Error-Lach R Q Figure 8 PWM Conrolling 3.3 Sof-Sar V SofS 6.5V 5.3V FB 4.8V R FB C4 C3 Clock G2 S R S Q Q Q PWM-Lach Gae Driver 5.6V 5.3V T Sof-Sar Gae Driver Figure 10 Acivaion of Proecion Uni The Sar-Up ime T Sar-Up wihin he converer oupu volage V OUT is seled mus be shorer han he Sof- Sar Phase T Sof-Sar (see Figure 11). C Sof Sar = R T Sof Sar Sof Sar 1,69 By means of Sof-Sar here is an effecive minimizaion of curren and volage sresses on he exernal Power Swich, he clamp circui and he oupu overshoo and prevens sauraion of he ransformer during Sar-Up. Figure 9 Sof-Sar Phase The Sof-Sar is realized by he inernal pullup resisor R Sof-Sar and he exernal Capacior C Sof-Sar (see Figure 2). The Sof-Sar volage V SofS is generaed by charging he exernal capacior C Sof-Sar by he inernal Daashee 9 30 Jun 2006 Preliminary Daa
Funcional Descripion V SofS khz f norm 5.3V f OSC T Sof-Sar V FB f sandby 1,0 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2 V 4.8V f norm : V FB ICE2BS01(G) 67kHz ICE2AS01(G) 100kHz V OUT f sandby : 20kHz 21.5kHz Figure 12 Frequency Dependence V OUT 3.5 Curren Limiing Figure 11 T Sar-Up Sar Up Phase 3.4 Oscillaor and Frequency Reducion 3.4.1 Oscillaor The oscillaor generaes a frequency f swich = 100kHz. A resisor, a capacior and a curren source and curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed, in order o achieve a very accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a max. duy cycle limiaion of D max =0.72. 3.4.2 Frequency Reducion The frequency of he oscillaor is depending on he volage a pin FB. The dependence is shown in Figure 12. This feaure allows a power supply o operae a lower frequency a ligh loads hus lowering he swiching losses while mainaining good cross regulaion performance and low oupu ripple. In case of low power he power consumpion of he whole SMPS can now be reduced very effecive. The minimal reachable frequency is limied o 20kHz / 21.5 khz o avoid audible noise in any case. There is a cycle by cycle curren limiing realised by he Curren-Limi Comparaor o provide an overcurren deecion. The source curren of he exernal Power Swich is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense. When he volage V Sense exceeds he inernal hreshold volage V csh he Curren-Limi-Comparaor immediaely urns off he gae drive. To preven he Curren Limiing from disorions caused by leading edge spikes a Leading Edge Blanking is inegraed a he Curren Sense. Furhermore a Propagaion Delay Compensaion is added o suppor he immediae shu down of he Power Swich in case of overcurren. 3.5.1 Leading Edge Blanking V csh V Sense LEB = 220ns Figure 13 Leading Edge Blanking Each ime when he exernal Power Swich is swiched on a leading spike is generaed due o he primary-side capaciances and secondary-side recifier reverse Daashee 10 30 Jun 2006 Preliminary Daa
Funcional Descripion recovery ime. To avoid a premaure erminaion of he swiching pulse his spike is blanked ou wih a ime consan of LEB = 220ns. During ha ime he oupu of he Curren-Limi Comparaor canno swich off he gae drive. V OSC max. Duy Cycle 3.5.2 Propagaion Delay Compensaion In case of overcurren deecion he shu down of he exernal Power Swich is delayed due o he propagaion delay of he circui. This delay causes an overshoo of he peak curren I peak which depends on he raio of di/d of he peak curren (see Figure 14).. V csh V Sense off ime Propagaion Delay Signal2 Signal1 I Sense Propagaion Delay I peak2 I peak1 I Limi I Overshoo2 Figure 15 Signal1 Signal2 Dynamic Volage Threshold V csh I Overshoo1 wih compensaion wihou compensaion Figure 14 Curren Limiing The overshoo of Signal2 is bigger han of Signal1 due o he seeper rising waveform. A propagaion delay compensaion is inegraed o bound he overshoo dependen on di/d of he rising primary curren. Tha means he propagaion delay ime beween exceeding he curren sense hreshold V csh and he swich off of he exernal Power Swich is compensaed over emperaure wihin a range of a leas. di peak 0 R d Sense 1 dv d Sense So curren limiing is now capable in a very accurae way (see Figure 16). E.g. I peak = 0.5A wih R Sense = 2. Wihou propagaion delay compensaion he curren sense hreshold is se o a saic volage level V csh =1V. A curren ramp of di/d = 0.4A/µs, ha means dv Sense /d = 0.8V/µs, and a propagaion delay ime of i.e. Propagaion Delay =180ns leads hen o an I peak overshoo of 14.4%. By means of propagaion delay compensaion he overshoo is only abou 2% (see Figure 15). The propagaion delay compensaion is done by means of a dynamic hreshold volage V csh (see Figure 15). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. V Sense V 1,3 1,25 1,2 1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 Figure 16 Overcurren Shudown 3.6 PWM-Lach The oscillaor clock oupu applies a se pulse o he PWM-Lach when iniiaing he exernal Power Swich conducion. Afer seing he PWM-Lach can be rese by he PWM-OP, he Sof-Sar-Comparaor, he Curren-Limi-Comparaor, Comparaor C3 or he Error-Lach of he Proecion Uni. In case of reseing he driver is shu down immediaely. 3.7 Driver dv Sense d The driver is a fas oem pole gae drive, which is designed o avoid cross conducion currens and which is equipped wih a Zener diode Z1 (see Figure 17) in order o improve he conrol of he gae aached power V µ s Daashee 11 30 Jun 2006 Preliminary Daa
Funcional Descripion ransisors as well as o proec hem agains undesirable gae overvolages. PWM-Lach 1 VCC Z1 Gae failure modes are lached by an Error-Lach. Addiional hermal shudown is lached by he Error-Lach. In case of hose failure modes he Error-Lach is se afer a blanking ime of 5µs and he exernal Power Swich is shu down. Tha blanking prevens he Error-Lach from disorions caused by spikes during operaion mode. 3.8.1 Overload & Open loop wih normal load Overload & Open loop/normal load FB 5µs Blanking 4.8V Failure Deecion Figure 17 Gae Driver A volages below he undervolage lockou hreshold V VCCoff he gae drive is acive low. The driver-sage is opimized o minimize EMI and o provide high circui efficiency. This is done by reducing he swich on slope when reaching he exernal Power Swich hreshold. This is achieved by a slope conrol of he rising edge a he driver s oupu (see Figure 18). SofS 5.3V Driver Sof-Sar Phase T Burs1 T Resar V Gae ca. = 130ns 5V C Load = 1nF VCC 13.5V 8.5V Figure 18 Gae Rising Slope Thus he leading swich on spike is minimized. When he exernal Power Swich is swiched off, he falling shape of he driver is slowed down when reaching 2V o preven an overshoo below ground. Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. Figure 19 Auo Resar Mode Figure 19 shows he Auo Resar Mode in case of overload or open loop wih normal load. The deecion of open loop or overload is provided by he Comparaor C3, C4 and he AND-gae G2 (see Figure20). 3.8 Proecion Uni (Auo Resar Mode) An overload, open loop and overvolage deecion is inegraed wihin he Proecion Uni. These hree Daashee 12 30 Jun 2006 Preliminary Daa
6.5V Power Up Rese ICE2AS01/S01G Funcional Descripion 3.8.2 Overvolage due o open loop wih no load SofS R Sof-Sar Open loop & no load condiion FB 5µs Blanking C Sof-Sar FB T1 5.3V 4.8V C4 C3 G2 Error-Lach 4.8V SofS Failure Deecion Sof-Sar Phase R FB 6.5V 5.3V 4.0V Overvolage Deecion Phase Figure 20 FB-Deecion The deecion is acivaed by C4 when he volage a pin SofS exceeds 5.3V. Till his ime he IC operaes in he Sof-Sar Phase. Afer his phase he comparaor C3 can se he Error-Lach in case of open loop or overload which leads he feedback volage V FB o exceed he hreshold of 4.8V. Afer laching VCC decreases ill 8.5V and inacivaes he IC. A his ime he exernal Sof-Sar capacior is discharged by he inernal ransisor T1 due o Power Down Rese. When he IC is inacive VCC increases ill V CCon = 13.5V by charging he Capacior C VCC by means of he Sar-Up Resisor R Sar-Up. Then he Error-Lach is rese by Power Up Rese and he exernal Sof-Sar capacior C Sof-Sar is charged by he inernal pullup resisor R Sof- Sar. During he Sof-Sar Phase which ends when he volage a pin SofS exceeds 5.3V he deecion of overload and open loop by C3 and G2 is inacive. In his way he Sar Up Phase is no deeced as an overload. Bu he Sof-Sar Phase mus be finished wihin he Sar Up Phase o force he volage a pin FB below he failure deecion hreshold of 4.8V. Driver VCC 16.5V 13.5V 8.5V T Burs2 T Resar Overvolage Deecion Figure 21 Auo Resar Mode Figure 21 shows he Auo Resar Mode for open loop and no load condiion. In case of his failure mode he converer oupu volage increases and also VCC. An addiional proecion by he comparaors C1, C2 and he AND-gae G1 is implemened o consider his failure mode (see Figure 22). Daashee 13 30 Jun 2006 Preliminary Daa
Funcional Descripion VCC 6.5V 16.5V C1 G1 Error Lach R Sof-Sar SofS 4.0V C2 C Sof-Sar T1 Power Up Rese Figure 22 Overvolage Deecion The overvolage deecion is provided by Comparaor C1 only in he firs ime during he Auo Resar Mode ill he Sof-Sar volage exceeds he hreshold of he Comparaor C2 a 4.0V and he volage a pin FB is above 4.8V. When VCC exceeds 16.5V during he overvolage deecion phase C1 can se he Error-Lach and he Burs Phase during Auo Resar Mode is finished earlier. In ha case T Burs2 is shorer han T Sof- Sar. By means of C2 he normal operaion mode is prevened from overvolage deecion due o varying of VCC concerning he regulaion of he converer oupu. When he volage V SofS is above 4.0V he overvolage deecion by C1 is deacivaed. 3.8.3 Thermal Shu Down Thermal Shu Down is lached by he Error-Lach when juncion emperaure T j of he pwm conroller is exceeding an inernal hreshold of 140 C. In ha case he IC swiches in Auo Resar Mode. Noe: All he values which are menioned in he funcional descripion are ypical. Please refer o Elecrical Characerisics for min/max limi values. Daashee 14 30 Jun 2006 Preliminary Daa
Elecrical Characerisics 4 Elecrical Characerisics 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 6 (VCC) is discharged before assembling he applicaion circui. Parameer Symbol Limi Values Uni Remarks min. max. V CC Supply Volage V CC -0.3 22 V FB Volage V FB -0.3 6.5 V SofS Volage V SofS -0.3 6.5 V ISense I Sense -0.3 3 V Juncion Temperaure T j -40 150 C Conroller & CoolMOS Sorage Temperaure T S -50 150 C Thermal Resisance R hja - 90 K/W PG-DIP-8 Juncion-Ambien Thermal Resisance R hja - 185 K/W PG-DSO-8 Juncion-Ambien ESD Capabiliy 1) V ESD - 2 kv Human Body Model 1) Equivalen o discharging a 100pF capacior hrough a 1.5 kω series resisor 4.2 Operaing Range Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. max. V CC Supply Volage V CC V CCoff 21 V Juncion Temperaure of Conroller T JCon -25 130 C limied due o hermal shu down of conroller Daashee 15 30 Jun 2006
Elecrical Characerisics 4.3 Characerisics Noe: The elecrical characerisics involve he spread of values guaraneed wihin he specified supply volage and juncion emperaure range T J from 25 C o 125 C.Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 15 V is assumed. 4.3.1 Supply Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCC1-27 55 µa V CC =V CCon -0.1V Supply Curren wih Inacive Gae Supply Curren wih Acive Gae ICE2AS01/G Supply Curren wih Acive Gae ICE2BS01/G VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hyseresis I VCC2-5.3 7 ma V SofS = 0 I FB = 0 I VCC3-6.5 8 ma V SofS = 5V I FB = 0 C Gae = 1nF I VCC3-6 7.5 ma V SofS = 5V I FB = 0 C Gae = 1nF V CCon V CCoff V CCHY 13-4.5 13.5 8.5 5 14-5.5 V V V 4.3.2 Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF 6.37 6.50 6.63 V measured a pin FB 4.3.3 Conrol Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Oscillaor Frequency f OSC1 93 100 107 khz V FB = 4V ICE2AS01/G Oscillaor Frequency f OSC3 62 67 72 khz V FB = 4V ICE2BS01/G Reduced Osc. Frequency f OSC2-21.5 - khz V FB = 1V ICE2AS01/G Reduced Osc. Frequency ICE2AS01/G f OSC4-20 - khz V FB = 1V Daashee 16 30 Jun 2006
Elecrical Characerisics Frequency Raio f osc1 /f osc2 4.5 4.65 4.9 ICE2AS01/G Frequency Raio f osc3 /f osc4 3.18 3.35 3.53 ICE2BS01/G Max Duy Cycle D max 0.67 0.72 0.77 Min Duy Cycle D min 0 - - V FB < 0V PWM-OP Gain A V 3.45 3.65 3.85 Max. Level of Volage Ramp V Max-Ramp - 0.85 - V V FB Operaing Range Min Level V FBmin 0.3 - - V V FB Operaing Range Max level V FBmax - - 4.6 V Feedback Resisance R FB 3.0 3.7 4.9 kω Sof-Sar Resisance R Sof-Sar 42 50 62 kω 4.3.4 Proecion Uni Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Over Load & Open Loop V FB2 4.65 4.8 4.95 V V SofS > 5.5V Deecion Limi Acivaion Limi of Overload & Open Loop Deecion V SofS1 5.15 5.3 5.46 V V FB > 5V Deacivaion Limi of Overvolage Deecion V SofS2 3.88 4.0 4.12 V V FB > 5V V CC > 17.5V Overvolage Deecion Limi V VCC1 16 16.5 17.2 V V SofS < 3.8V V FB > 5V Lached Thermal Shudown T jsd 130 140 150 C guaraneed by design Spike Blanking Spike - 5 - µs 4.3.5 Curren Limiing Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Peak Curren Limiaion (incl. Propagaion Delay Time) (see Figure 7) V csh 0.95 1.00 1.05 V dv sense / d = 0.6V/µs Leading Edge Blanking LEB - 220 - ns Daashee 17 30 Jun 2006
Elecrical Characerisics 4.3.6 Driver Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. GATE Low Volage V GATE - 0.95 1.2 V V VCC = 5 V I Gae = 5 ma - 1.0 1.5 V V VCC = 5 V I Gae = 20 ma - 0.88 - V I Gae = 0 A - 1.6 2.2 V I Gae = 50 ma -0.2 0.2 - V I Gae = -50 ma GATE High Volage V GATE - 11.5 - V V VCC = 20V C L = 4.7nF - 10 - V V VCC = 11V C L = 4.7nF - 7.5 - V V VCC = V VCCoff + 0.2V C L = 4.7nF GATE Rise Time r - 160 - ns V Gae = 2V...9V 1) C L = 4.7nF GATE Fall Time f - 65 - ns V Gae = 9V...2V 1) GATE Curren, Peak, Rising Edge GATE Curren, Peak, Falling Edge 1) Transien reference value 2) Design characerisics (no mean for producion esing) C L = 4.7nF I GATE -0.5 - - A C L = 4.7nF 2) I GATE - - 0.7 A C L = 4.7nF 2) Daashee 18 30 Jun 2006
5 Typical Performance Characerisics ICE2AS01/S01G Typical Performance Characerisics Sar Up Curren I VCC1 [µa] 40 38 36 34 32 30 28 26 24 22 Juncion Temperaure [ C] Figure 23 Sar Up Curren I VCC1 vs. T j PI-001-190101 VCC Turn-On Threshold V CCon [V] 13,58 13,56 13,54 13,52 13,50 13,48 13,46 13,44 13,42 Juncion Temperaure [ C] Figure 26 VCC Turn-On Threshold V VCCon vs. T j PI-004-190101 Supply Curren I VCC2 [ma] 6,0 5,7 5,4 5,1 4,8 4,5 Juncion Temperaure [ C] Figure 24 Supply Curren I VCC2 vs. T j PI-003-190101 VCC Turn-Off Threshold V VCCoff [V] 8,67 8,64 8,61 8,58 8,55 8,52 8,49 8,46 8,43 8,40 Juncion Temperaure [ C] Figure 27 VCC Turn-Off Threshold V VCCoff vs. T j PI-005-190101 Figure 25 Supply Curren I VCC3 vs. T j VCC Turn-On/Off Hyseresis V CCHY [V] 5,10 5,07 5,04 5,01 4,98 4,95 4,92 4,89 4,86 4,83 Juncion Temperaure [ C] Figure 28 VCC Turn-On/Off Hyseresis V VCCHY vs. T j PI-006-190101 Daashee 19 30 Jun 2006 Preliminary Daa
Typical Performance Characerisics Trimmed Reference Volage V REF [V] 6,55 6,54 6,53 6,52 6,51 6,50 6,49 6,48 6,47 6,46 6,45 Juncion Temperaure [ C] Figure 29 Trimmed Reference V REF vs. T j PI-007-190101 Figure 32 Reduced Osc. Frequency f OSC2 vs. T j Figure 30 Oscillaor Frequency f OSC1 vs. T j Figure 33 Reduced Osc. Frequency f OSC4 vs. T j Figure 31 Oscillaor Frequency f OSC3 vs. T j Figure 34 Frequency Raio f OSC1 / f OSC2 vs. T j Daashee 20 30 Jun 2006 Preliminary Daa
Typical Performance Characerisics Figure 35 Frequency Raio f OSC3 / f OSC4 vs. T j Feedback Resisance R FB [kohm] 4,00 3,95 3,90 3,85 3,80 3,75 3,70 3,65 3,60 3,55 3,50 Juncion Temperaure [ C] Figure 38 Feedback Resisance R FB vs. T j PI-013-190101 Max. Duy Cycle 0,730 0,728 0,726 0,724 0,722 0,720 0,718 0,716 0,714 0,712 0,710 Juncion Temperaure [ C] Figure 36 Max. Duy Cycle vs. T j PI-011-190101 Sof-Sar Resisance R Sof-Sar [kohm] 58 56 54 52 50 48 46 44 42 40 Juncion Temperaure [ C] Figure 39 Sof-Sar Resisance R Sof-Sar vs. T j PI-014-190101 3,70 3,69 4,85 4,84 PWM-OP Gain A V 3,68 3,67 3,66 3,65 3,64 3,63 3,62 PI-012-190101 Deecion Limi V FB2 [V] 4,83 4,82 4,81 4,80 4,79 4,78 4,77 PI-015-190101 3,61 4,76 3,60 Juncion Temperaure [ C] Figure 37 PWM-OP Gain A V vs. T j 4,75 Juncion Temperaure [ C] Figure 40 Deecion Limi V FB2 vs. T j Daashee 21 30 Jun 2006 Preliminary Daa
Typical Performance Characerisics Deecion Limi V Sof-Sar1 [V] 5,35 5,34 5,33 5,32 5,31 5,30 5,29 5,28 5,27 5,26 5,25 Juncion Temperaure [ C] Figure 41 Deecion Limi V Sof-Sar1 vs. T j PI-016-190101 Peak Curren Limiaion V csh [V] 1,010 1,008 1,006 1,004 1,002 1,000 0,998 0,996 0,994 0,992 0,990 Juncion Temperaure [ C] Figure 44 Peak Curren Limiaion V csh vs. T j PI-019-190101 Deecion Limi V Sof-Sar2 [V] 4,05 4,04 4,03 4,02 4,01 4,00 3,99 3,98 3,97 3,96 3,95 Juncion Temperaure [ C] Figure 42 Deecion Limi V Sof-Sar2 vs. T j PI-017-190101 Leading Edge Blanking LEB [ns] 280 270 260 250 240 230 220 210 200 190 180 Juncion Temperaure [ C] Figure 45 Leading Edge Blanking V VCC1 vs. T j PI-020-190101 Overvolage Deecion Limi V VCC1 [V] 16,80 16,75 16,70 16,65 16,60 16,55 16,50 16,45 16,40 16,35 16,30 16,25 16,20 Juncion Temperaure [ C] Figure 43 Overvolage Deecion Limi V VCC1 vs. T j PI-018-190101 Daashee 22 30 Jun 2006 Preliminary Daa
Ouline Dimension 6 Ouline Dimension PG-DSO-8 (Plasic Dual Small Ouline) Figure 46 PG-DIP-8 (Plasic Dual In-line Package) Figure 47 Dimensions in mm Daashee 23 30 Jun 2006
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