FSUSB43 Low-Power, Two-Port, High-Speed, USB2.0 (480Mbps) Switch

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FSUSB43 Low-Power, Two-Port, High-Speed, USB2.0 (480Mbps) Switch Features Over-Voltage Tolerance (OVT) on all USB Ports up to 5.25V without External Components Low On Capacitance: 3.7pF Typical Low On Resistance: 3.9Ω Typical Low Power Consumption: 1μA Maximum - 20μA Maximum I CCT over an Expanded Voltage Range (V IN=1.8V, V CC=4.3V) Wide -3db Bandwidth: > 720MHz Packaged in 10-Lead MicroPak (1.6 x 2.1mm) 8kV ESD Rating, >16kV Power/ ESD Rating Power-Off Protection on All Ports when V CC=0V - D+/D- Pins Tolerate up to 5.25V Applications Cell phone, PDA, Digital Camera, and Notebook LCD Monitor, TV, and Set-Top Box IMPORTANT NOTE: For additional performance information, please contact analogswitch@fairchildsemi.com. Description December 2009 The FSUSB43 is a bi-directional, low-power, two-port, high-speed, USB2.0 switch. Configured as a doublepole, double-throw (DPDT) switch, it is optimized for switching between two high-speed (480Mbps) sources or a high-speed and full-speed (12Mbps) source. The FSUSB43 is compatible with the requirements of USB2.0 and features an extremely low on capacitance (C ON) of 3.7pF. The wide bandwidth of this device (720MHz) exceeds the bandwidth needed to pass the third harmonic, resulting in signals with minimum edge and phase distortion. Superior channel-to-channel crosstalk also minimizes interference. The FSUSB43 contains special circuitry on the switch I/O pins for applications where the V CC supply is powered-off (V CC=0), which allows the device to withstand an over-voltage condition. This minimizes current consumption even when the control voltage applied to the SEL pin is lower than the supply voltage (V CC). This feature is especially valuable to mobile applications, such as cell phones, allowing for direct interface with the general-purpose I/Os of the baseband processor. Other applications include switching and connector sharing in portable cell phones, PDAs, digital cameras, printers, and notebook computers. HSD1+ HSD2+ D+ HSD1- HSD2- Sel Control D- /OE Figure 1. Analog Symbol Ordering Information Part Number Top Mark Operating Temperature Range Eco Status Package FSUSB43L10X JH -40 to +85 C Green MicroPak is a trademark of Fairchild Semiconductor Corporation. 10-Lead MicroPak 1.6 x 2.1mm, JEDEC MO-255B For Fairchild s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. FSUSB43 Rev. 1.0.2

Pin Configuration Pin Definitions Pin # Name Description 1 HSD1+ Multiplexed Source Inputs 2 HSD1- Multiplexed Source Inputs 3 HSD2+ Multiplexed Source Inputs 4 HSD2- Multiplexed Source Inputs 5 Ground 6 /OE Switch Enable 7 D- USB Data Bus 8 D+ USB Data Bus 9 SEL Switch Select 10 V CC Supply Voltage V cc HSD1+ 1 10 9 SEL HSD1-2 8 D+ HSD2+ 3 7 D- HSD2-4 6 /OE 5 Figure 2. Pin Assignment (Top Through View) Truth Table SEL /OE Function X HIGH Disconnect LOW LOW D+, D-=HSD1+, HSD1- HIGH LOW D+, D-=HSD2+, HSD2- FSUSB43 Rev. 1.0.2 2

Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC Supply Voltage -0.5 +5.5 V V CNTRL DC Input Voltage (Sel, /OE) (1) -0.5 V CC V V SW ALL PINS for V CC 0 to 5.5V -0.5 5.5 V I IK DC Input Diode Current -50 ma I OUT DC Output Current 100 ma T STG Storage Temperature -65 +150 C ESD Human Body Model: JEDEC JESD22-A114 All Pins 8 I/O to 9 Power to 16 Charged Device Model: JEDEC JESD22-C101 2 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V CC Supply Voltage 3.0 4.3 V V CNTRL Control Input Voltage (2) (Sel, /OE) 0 V CC V V SW Switch I/O Voltage -0.5 4.5 V T A Operating Temperature -40 +85 C 2. The control input must be held HIGH or LOW; it must not float. kv FSUSB43 Rev. 1.0.2 3

DC Electrical Characteristics All typical values are at 25 C unless otherwise specified. Symbol Parameter Conditions V CC (V) T A =- 40ºC to +85ºC Min. Typ. Max. V IK Clamp Diode Voltage I IN=-18mA 3.0-1.2 V V IH V IL Input Voltage High Input Voltage Low Units 3.0 to 3.6 1.3 V 4.3 1.7 V 3.0 to 3.6 0.5 V 4.3 0.7 V I IN Control Input Leakage V SW=0 to V CC 4.3-1.0 1.0 µa I OZ I OFF Off State Leakage Power-Off Leakage Current (All I/O Ports) 0 Dn, HSD1n, HSD2n 3.6V V SW=0V to 4.3V, V CC=0V Figure 4 (3) VSW=0.4V, ION=-8mA R ON HS Switch On Resistance Figure 3 R ON HS Delta R ON (4) 4.3-2.0 2.0 µa 0-2 2 µa 3.0 3.9 6.5 Ω V SW=0.4V, I ON=-8mA 3.0 0.65 Ω I Q Quiescent Supply Current V CNTRL=0 or V CC, I OUT=0 4.3 1.0 µa I CCT Increase in I Q Current per Control Voltage and V CC V CNTRL=2.6V, V CC=4.3V 4.3 10.0 µa V CNTRL=1.8V, V CC=4.3V 4.3 20.0 µa Notes: 3. Measured by the voltage drop between HSDn and Dn pins at the indicated current through the switch. On resistance is determined by the lower of the voltage on the two (HSDn or Dn ports). 4. Guaranteed by characterization. FSUSB43 Rev. 1.0.2 4

AC Electrical Characteristics All typical values are for V CC=3.3V at 25 C unless otherwise specified. Symbol Parameter Conditions V CC (V) t ON t OFF Turn-On Time SEL, /OE to Output Turn-Off Time SEL, /OE to Output R L=50Ω, C L=5pF, V SW=0.8V Figure 5, Figure 6 R L=50Ω, C L=5pF, V SW=0.8V Figure 5, Figure 6 (5) RL=50Ω, CL=5 pf t PD Propagation Delay Figure 5, Figure 7 t BBM Break-Before-Make Time (5) R L=50Ω, C L=5pF V SW1=V SW2=0.8V Figure 9 (5) RL=50Ω, f=240mhz OIRR Off Isolation Figure 11 Xtalk Non-Adjacent Channel Crosstalk (5) R L=50Ω, f=240mhz Figure 12 BW -3db Bandwidth (5) Figure 10 R L=50Ω, C L=5pF R L=50Ω, C L=0pF Figure 10 5. Guaranteed by characterization. T A =- 40ºC to +85ºC Min. Typ. Max. Units 3.0 to 3.6 13 30 ns 3.0 to 3.6 12 25 ns 3.3 0.25 ns 3.0 to 3.6 2.0 6.5 ns 3.0 to 3.6-30 db 3.0 to 3.6-45 db 3.0 to 3.6 USB High-Speed-Related AC Electrical Characteristics Symbol Parameter Conditions V CC (V) t SK(P) Skew of Opposite Transitions of the Same Output (6) R L=50Ω, C L=5pF Figure 8 720 MHz 550 MHz T A =- 40ºC to +85ºC Min. Typ. Max. Units 3.0 to 3.6 20 ps t J Total Jitter (6) t r=t f=500ps (10-90%) at R L=50Ω, C L=5pf, 480Mbps, (PRBS=2 15 1) 6. Guaranteed by characterization. 3.0 to 3.6 200 ps Capacitance Symbol Parameter Conditions T A =- 40ºC to +85ºC Min. Typ. Max. Units C IN Control Pin Input Capacitance (7) V CC=0V 1.5 (7) VCC=3.3V, /OE=0V, f=240mhz C ON D+/D- On Capacitance Figure 14 C OFF (7) D1n, D2n Off Capacitance VCC and /OE=3.3V Figure 13 7. Guaranteed by characterization. 3.7 2.0 pf FSUSB43 Rev. 1.0.2 5

Test Diagrams V SW V SW V ON R ON = V ON /I ON Dn Select = 0 orvcc Figure 3. On Resistance Dn C L I ON R L,,andC L are functions of the application environment (see AC Tables for specific values) C L includes test fixture and stray capacitance. R L Figure 5. AC Test Circuit Load NC I Dn(OFF) A Select = 0 orvcc **Each switch port is tested separately Figure 4. Off Leakage t RISE =2.5ns V CC Input V /OE, 90% 90% V CC /2 V CC /2 V OH V SW t FALL = 2.5ns 90% 90% Output- V OL t ON t OFF Figure 6. Turn-On / Turn-Off Waveforms t RISE= 500ps t FALL =500ps Input 0V t PLH 50% 50% 400mV t PHL +400mV -400mV 0V 90% 90% Output 50% 50% V OH V OL Output t PHL t PLH Figure 7. Propagation Delay (t rt f 500ps) Figure 8. Intra-Pair Skew Test t SK(P) FSUSB43 Rev. 1.0.2 6

Test Diagrams (Continued) V SW1 V SW2 and are functions of the application environment (see AC Tables for specific values). Figure 10. Bandwidth Dn C L R L t RISE = 2.5ns V cc Input - 0V 0.9*V out 90% V cc /2 t BBM R L,,andC L are functions of the application environment (see AC Tables for specific values) C L includes test fixture and stray capacitance. Figure 9. Break-Before-Make Interval Timing Network Analyzer V IN V S NC and are functions of the application environment (see AC Tables for specific values). 0.9*V out Network Analyzer V IN V S Off isolation = 20 Log ( / V IN ) Figure 11. Channel Off Isolation Network Analyzer V IN V S and are functions of the application environment (see AC Tables for specific values). Crosstalk = 20 Log ( / V IN ) Figure 12. Non-Adjacent Channel-to-Channel Crosstalk Capacitance Meter S = 0 or V cc Capacitance Meter S = 0 or V cc Figure 13. Channel Off Capacitance Figure 14. Channel On Capacitance FSUSB43 Rev. 1.0.2 7

Physical Dimensions 2X PIN1 IDENT IS 2X LONGEHAN OTHER LINES 0.05 C DETAIL A 0.35 0.25 (0.29) 0.10 C C 0.50 TOP VIEW SIDE VIEW D 0.65 0.55 2.10 1 4 10 5 9 6 1.62 BOTTOM VIEW (0.36) A 0.25 9X 0.15 B 1.60 0.05 0.00 0.56 2X 0.35 9X 0.25 0.10 C 0.55 MAX 0.05 C 0.10 C A B 0.05 C ALL FEATURES (0.15) 1.12 (0.11) 0.56 0.50 1.62 (0.35) 10X (0.25) 10X RECOMMENDED LAND PATTERN (0.20) 0.35 0.25 0.35 0.25 DETAIL A 2X SCALE KEEPOUT ZONE, NO TRACES OR VIAS ALLOWED NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. PRESENCE OF CENTER PAD IS PACKAGE SUPPLIER DEPENDENT. IF PRESENT IT IS NOT INTENDED TO BE SOLDERED AND HAS A BLACK OXIDE FINISH. E. DRAWING FILENAME: MKT-MAC10Arev5. Figure 15. 10-Lead MicroPak Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor s online packaging area: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. FSUSB43 Rev. 1.0.2 8

FSUSB43 Rev. 1.0.2 9