NC7WZ07 TinyLogic UHS Dual Buffer (Open-Drain Outputs)
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1 April 2013 NC7WZ07 TinyLogic UHS Dual Buffer (Open-Drain Outputs) Features Ultra-High Speed: t PZL 2.3 ns (Typical) High I OL Output Drive: ±24 ma at 3 CC Broad CC Operating Range: 1.65 to 5.50 Power Down High Impedance Inputs/Outputs Over-oltage Tolerance Inputs Facilitate 5 to 3 Translation Proprietary Noise/EMI Reduction Circuitry Ultra-Small MicroPak Packages Description The NC7WZ07 is a dual buffer with open-drain outputs from Fairchild s Ultra-High Speed (UHS) series of TinyLogic. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive, while maintaining low static power dissipation over a broad CC operating range. The device is specified to operate over a very broad CC operating range. The device is specified to operate over the 1.65 to 5.5 CC range. The inputs and outputs are high impedance when CC is 0. Inputs tolerate voltages up to 7 independent of CC operating voltage. Ordering Information Part Number Top Mark Package Packing Method NC7WZ07P Z07 6-Lead SC70, EIAJ SC mm Wide 3000 Units on Tape & Reel NC7WZ07L D3 6-Lead MicroPak, 1.00 mm Wide 5000 Units on Tape & Reel NC7WZ07FHX D3 6-Lead, MicroPak2, 1x1 mm Body,.35 mm Pitch 5000 Units on Tape & Reel Connection Diagrams IEEE/IEC Figure 1. Logic Symbol NC7WZ07 Rev
2 Pin Configurations Figure 2. SC70 (Top iew) Figure 3. MicroPak (Top Through iew) Figure 4. Pin 1 Orientation Notes: 1. AAA represents product code top mark (see Ordering Information). 2. Orientation of top mark determines pin one location. 3. Reading the top mark left to right, pin one is the lower left pin. Pin Definitions Pin # SC70 Pin # MicroPak Name Description 1 1 A 1 Input 2 2 GND Ground 3 3 A 2 Input 4 4 Y 2 Output 5 5 CC Supply oltage 6 6 Y 1 Output Function Table Y= A Inputs A LOW Logic Level HIGH Logic Level Output Y LOW Logic Level High Impedance Output State, Open Drain NC7WZ07 Rev
3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit CC Supply oltage IN DC Input oltage OUT DC Output oltage I IK DC Input Diode Current IN < ma I OK DC Output Diode Current OUT < ma I OUT DC Output Current ±50 ma I CC or I GND DC CC or Ground Current ±100 ma T STG Storage Temperature Range C T J Junction Temperature Under Bias +150 C T L Junction Lead Temperature (Soldering, 10 Seconds) +260 C P D ESD Power Dissipation at +85 C SC MicroPak MicroPak Human Body Model, JEDEC:JESD22-A Charge Device Model, JEDEC:JESD22-C mw Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Conditions Min. Max. Unit CC Supply oltage Operating Supply oltage Data Retention IN Input oltage OUT Output oltage t r, t f Input Rise and Fall Times CC at 1.8, ±0.15, 2.5 ± CC at 3.3 ± CC at 5.0 ± T A Operating Temperature C JA Thermal Resistance Note: 4. Unused inputs must be held HIGH or LOW. They may not float. SC MicroPak MicroPak ns/ C/W NC7WZ07 Rev
4 DC Electrical Characteristics Symbol Parameter CC Conditions T A =+25 C T A =-40 to +85 C Min. Typ. Max. Min. Max. Units IH HIGH Level Input oltage 1.65 to CC 0.75 CC 2.30 to CC 0.70 CC IL I LKG OL I IN I OFF I CC LOW Level Input oltage HIGH Level Output Leakage Current LOW Level Output oltage Input Leakage Current Power Off Leakage Current Quiescent Supply Current 1.65 to CC 0.25 CC 2.30 to CC 0.30 CC 1.65 to IN = IH, OUT = CC or GND ±5 ±10 µa IN = IL, I OL =100 µa I OL =4 ma I OL =8 ma I OL =16 ma I OL =24 ma I OL =32 ma to IN 5.5 ±0.1 ±1.0 µa 0 IN or OUT = µa 1.65 to 5.50 IN =5.5, GND 1 10 µa NC7WZ07 Rev
5 AC Electrical Characteristics Symbol Parameter CC Conditions t PZL, t PLZ Propagation Delay 1.65 T A =+25 C Min. Typ. Max. Min. Max C L =50 pf, ± 0.20 RU=500 RD= ± 0.30 I =2 x CC ± C L =50 pf, ± 0.20 RU=500 RD= ± 0.30 I =2 x CC ± T A =-40 to +85 C Units Figure C IN Input Capacitance pf C OUT Output Capacitance C PD Power Dissipation Capacitance (5) ns Figure 5 Figure 6 pf Figure 7 Note: 5. C PD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I CCD ) at no output loading and operating at 50% duty cycle. C PD is related to I CCD dynamic operating current by the expression: I CCD =(C PD )( CC )(f IN )+(I CC static). Notes: 6. C L includes load and stray capacitance. 7. Input PRR = 1.0MHz, t W = 500ns. Figure 5. AC Test Circuit Figure 6. AC Waveforms Note: 8. Input=AC Waveform; t r =t f =1.8ns. 9. PRR=ariable; Duty Cycle=50%. Figure 7. I CCD Test Circuit NC7WZ07 Rev
6 Physical Dimensions 2.00±0.20 A SYMM CL MIN 6 4 B PIN ONE 1.25± (0.25) A B MIN LAND PATTERN RECOMMENDATION SEE C SEATING PLANE 0.10 C 2.10±0.30 GAGE PLANE 0.20 (R0.10) NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO EIAJ SC-88, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. D) DRAWING FILENAME: MKT-MAA06ARE SCALE: 60X Figure 8. 6-Lead, SC70, EIAJ SC88, 1.25 mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed P Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed NC7WZ07 Rev
7 Physical Dimensions 2X 1.45 B 2X (1) (0.254) 1.00 (0.49) 5X (0.75) PIN 1 IDENTIFIER 5 TOP IEW 0.55MAX C A (0.52) 1X PIN C B A (0.30) RECOMMENED LAND PATTERN X Notes: (0.05) 0.5 BOTTOM IEW X 45 CHAMFER 1. CONFORMS TO JEDEC STANDARD M0-252 ARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M FILENAME AND REISION: MAC06ARE4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. 5X (0.13) 4X PIN 1 TERMINAL Figure 9. 6-Lead, MicroPak, 1.0 mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed L Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed NC7WZ07 Rev
8 Physical Dimensions X 1.00 B A 5X 0.40 PIN 1 MIN 250uM X TOP IEW 2X 0.19 RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 0.90 C 0.55MAX 5X 0.52 SIDE IEW 0.73 (0.08) 4X X X 0.25 NOTES: BOTTOM IEW 0.60 (0.08) 4X A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REISION: MGF06ARE3 Figure C B A.05 C 0.075X45 CHAMFER (0.05) 0.20 ALTERNATIE LAND PATTERN FOR UNIERSAL APPLICATION PIN 1 LEAD SCALE: 2X 6-Lead, MicroPak2, 1x1 mm Body,.35 mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed FHX Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed NC7WZ07 Rev
9 NC7WZ07 Rev NC7WZ07 TinyLogic UHS Dual Buffer (Open-Drain Outputs)
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