NC7SZ66 Low Voltage Single SPST Normally Open Bus Switch

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Allen Snow
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1 September 2013 NC7SZ66 Low Voltage Single SPST Normally Open Bus Switch Features Broad V CC Operating Range: 1.65 V to 5.5 V Rail-to-Rail Signal Handling Power Down High-Impedance Inputs/Outputs 5 Ω Switch Connection between Two Ports Minimal Propagation Delay through the Switch Low I CC Zero Bounce in Flow-Through Mode Control Input Compatible with CMOS Input Levels Ultra-Small MicroPak Packages Space-Saving SOT23 and SC70 Packages Description The NC7SZ66 is a ultra high-speed (UHS) CMOS compatible single-pole/single-throw (SPST) bus switch. The LOW on resistance of the switch allows inputs to be connected to outputs with minimal propagation delay and without generating additional ground bounce noise. The device is organized as a 1-bit switch with a switch enable (OE) signal. When OE is HIGH, the switch is on and port A is connected to port B. When OE is LOW, the switch is open and a high-impedance state exists between the two ports.. Ordering Information Part Number Top Mark Package Packing Method NC7SZ66M5X 7Z66 5-Lead SOT23, JEDEC MO mm 3000 Units on Tape & Reel NC7SZ66P5X Z66 5-Lead SC70, EIAJ SC-88a, 1.25 mm Wide 3000 Units on Tape & Reel NC7SZ66L6X EE 6-Lead, MicroPak, 1x1 mm Wide 5000 Units on Tape & Reel NC7SZ66 Rev

2 Connection Diagrams Pin Configurations Figure 1. Logic Symbol Figure 2. SC70 and SOT23 (Top View) Figure 3. MicroPak (Top Through View) Pin Definitions Pin # SC70 / SOT23 Pin # MicroPak Name Description 1 1 A Bus A I/O 2 2 B Bus B I/O 3 3 GND Ground 4 4 OE Switch Enable Input 5 6 V CC Supply Voltage 5 NC No Connect Function Table OE B 0 Function L High Z-State Disconnected H A 0 Connect H = HIGH Logic Level L = LOW Logic Level NC7SZ66 Rev

3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V S DC Switch Voltage (1) -0.5 V CC to 0.5 V V IN DC Input Voltage V I IK DC Input Diode Current V IN < 0 V -50 ma I OUT DC Output Sink Current 128 ma I CC or I GND DC V CC or Ground Current ±100 ma T STG Storage Temperature Range C T J Junction Temperature Under Bias +150 C T L Junction Lead Temperature (Soldering, 10 Seconds) +260 C P D ESD Power Dissipation at +85 C SOT SC Human Body Model, JEDEC:JESD22-A Charge Device Model: JEDEC:JESD22-C Note: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. mw V Symbol Parameter Conditions Min. Max. Unit V CC Supply Voltage Operating V V IN Input Voltage V V S Switch Input Voltage 0 V CC V V OUT Output Voltage 0 V CC V V CC =2.3 V V 0 10 t r, t f Input Rise and Fall Times V CC =4.5 V 5.5 V 0 5 ns/v Switching I/O 0 DC T A Operating Temperature C θ JA Thermal Resistance SOT SC Note: 2. Unused inputs must be held HIGH or LOW; they may not float. C/W NC7SZ66 Rev

4 DC Electrical Characteristics All typical values are at the specified V CC, and T A = 25 C. Symbol Parameter V CC Conditions V IH V IL I IN I OFF R ON R flat I CC HIGH Level Input Voltage LOW Level Input Voltage Control Input Leakage Current Off Leakage Current Switch On Resistance (3) On Resistance Flatness (3,4,5) Quiescent Supply Current 1.65 to to to to 5.50 T A =-40 to +85 C T A =+25 C Min. Typ. Max. Min. Typ V CC 0.7 V CC 0.25 V CC 0.3 V CC Units 0 to V IN 5.5 V ±0.05 ±1.00 µa 1.65 to to A, B V CC ±0.05 ±10.00 µa V IN =0 V, I IN =30 ma 3 7 V IN =2.4 V, I IN =15 ma 5 12 V IN =4.5 V, I IN =30 ma 7 15 V IN =0 V, I IN =24 ma 4 9 V IN =3 V, I IN =24 ma V IN =0 V, I IN =8 ma 5 12 V IN =2.3 V, I IN =8 ma V IN =0 V, I IN =4 ma 7 28 V IN =1.8 V, I IN =4 ma I A =-30 ma, 0 V Bn V CC I A =-24 ma, 0 V Bn V CC I A =-8mA, 0 V Bn V CC I A =-4 ma, 0 V Bn V CC V IN = V CC or GND, I OUT = µa Notes: 3. Measured by the voltage drop between pins A and B at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. 4. Parameter is characterized but not tested in production. 5. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. V V Ω Ω NC7SZ66 Rev

5 AC Electrical Characteristics All typical values are at the specified V CC, and T A = 25 C. Symbol Parameter V CC Conditions t PHL, t PLH t PZL, t PZH t PLZ, t PHZ C IN C I/O Propagation Delay Bus-to-Bus (6) Output Enable Time Output Disable Time Control Pin Input Capacitance Input / Output Capacitance T A =-40 to +85 C, C L =50Pf. RU=RD=500 Ω Min. Typ. Max to to V IN =0PEN 3.0 to to to to to 3.6 V IN =2 x V CC for t PZL, V IN =0 V for t PZH to to to to 3.6 V IN =2 x V CC for t PLZ, V IN =0 V for t PHZ to Units V CC =0 2 pf V CC =05.0 V 6 pf ns ns ns Figure Figure 5 Figure 6 Figure 5 Figure 6 Figure 5 Figure 6 Note: 6. This parameter is guaranteed by design but is not tested. The switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). Notes: 7. Input driven by 50 Ω; source terminated in 50 Ω. 8. C L includes load and stray capacitance. 9. Input PRR=1.0 MHz; t w =500 ns. Figure 4. AC Test Circuit Figure 5. AC Waveforms NC7SZ66 Rev

6 Physical Dimensions (0.30) TOP VIEW 4 3 A B C A B 1.45 MAX GAGE PLANE 0.25 C 0.10 C 1.00 SYMM C L LAND PATTERN RECOMMENDATION SEE DETAIL A NOTES: UNLESS OTHEWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev REF SEATING PLANE Figure 6. 5-Lead SOT23, JEDEC MO mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status M5X Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed NC7SZ66 Rev

7 Physical Dimensions Figure 7. 5-Lead, SC70, EIAJ SC-88a, 1.25 mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status P5X Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed NC7SZ66 Rev

8 Physical Dimensions 2X 0.05 C PIN 1 IDENTIFIER C DETAIL A (0.05) 6X 0.55MAX C 1.45 (0.254) TOP VIEW BOTTOM VIEW B 2X 0.05 C Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 8. 6-Lead, MicroPak, 1.0 mm Wide 6X A 0.05 C (0.49) 5X (0.52) 1X PIN C B A 0.05 C 5X 5X (0.13) 4X X 45 CHAMFER (1) (0.30) 6X RECOMMENED LAND PATTERN X (0.75) DETAIL A PIN 1 TERMINAL Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status L6X Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed NC7SZ66 Rev

9 NC7SZ66 Rev

10 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor: NC7SZ66P5X_Q NC7SZ66M5 NC7SZ66M5X_Q

NC7SZ125 TinyLogic UHS Buffer with Three-State Output

NC7SZ125 TinyLogic UHS Buffer with Three-State Output January 2014 NC7SZ125 TinyLogic UHS Buffer with Three-State Output Features Ultra-High Speed: t PD 2.6 ns (Typical) into 50 pf at 5 CC High Output