OP Precision Dual Difet OPERTIONL MPLIFIER FETURES VERY LOW NOISE: nv/ Hz at khz LOW V OS : µv max LOW DRIFT: µv/ C max LOW I B : p max FST SETTLING TIME: µs to.% UNITY-GIN STBLE PPLICTIONS DT CQUISITION DC OUTPUT MPLIFIER OPTOELECTRONICS HIGH-IMPEDNCE SENSOR MPS HIGH-PERFORMNCE UDIO CIRCUITRY MEDICL EQUIPMENT, CT SCNNERS DESCRIPTION The OP dual operational amplifier provides precision Difet performance with the cost and space savings of a dual op amp. It is useful in a wide range of precision and low-noise analog circuitry and can be used to upgrade the performance of designs currently using BIFET type amplifiers. In (, ) +VS () The OP is fabricated on a proprietary dielectrically isolated (Difet ) process. This holds input bias currents to very low levels without sacrificing other important parameters, such as input offset voltage, drift and noise. Laser-trimmed input circuitry yields excellent DC performance. Superior dynamic performance is achieved, yet quiescent current is held to under.m per amplifier. The OP is unitygain stable. The OP is available in plastic DIP, metal TO- 99, and SOIC packages. Industrial and Military temperature range versions are available. +In (, ) Cascode Output (, ) VS () Difet Burr-Brown Corp. BIFET National Semiconductor International irport Industrial Park Mailing ddress: PO Box Tucson, Z Street ddress: S. Tucson Blvd. Tucson, Z Tel: () - Twx: 9-9- Cable: BBRCORP Telex: -9 FX: () 9- Immediate Product Info: () - 99 Burr-Brown Corporation PDS-B Printed in U.S.. October, 99
SPECIFICTIONS T = + C, V S = ±V unless otherwise noted. OPM, SM, P, U OPBM PRMETER CONDITION MIN TYP MX MIN TYP MX UNITS OFFSET VOLTGE () Input Offset Voltage V CM = V mv µv Over Specified Temperature.. mv SM Grade.. mv verage Drift Over Specified Temperature µv/ C Power Supply Rejection V S = ± to ±V 9 db INPUT BIS CURRENT () Input Bias Current V CM = V p Over Specified Temperature... n SM Grade n Input Offset Current V CM = V. p Over Specified Temperature. n SM Grade n INPUT NOISE Voltage: f = Hz R S = * nv/ Hz f = Hz * nv/ Hz f = khz 9 * nv/ Hz f = khz * nv/ Hz BW =. to Hz. * µvp-p BW = to khz. * µvrms Current: f =.Hz thru khz..9 f/ Hz BW =.Hz to Hz fp-p INPUT IMPEDNCE Differential * Ω pf Common-Mode * Ω pf INPUT VOLTGE RNGE Common-Mode Input Range ±. ± * * V Over Specified Temperature ±. ±. * * V SM Grade ± ±. V Common-Mode Rejection V CM = ±V 9 db OPEN-LOOP GIN Open-Loop Voltage Gain V O = ±V, R L = kω 9 db Over Specified Temperature 9 9 db SM Grade 9 db DYNMIC RESPONSE Slew Rate G = + * * V/µs Settling Time:.% G =, V Step. * µs.% * µs Gain-Bandwidth Product G =. * MHz THD + Noise G = +, f = khz. * % Channel Separation f = Hz, R L = kω * db POWER SUPPLY Specified Operating Voltage ± * V Operating Voltage Range ±. ± * * V Current ±. ± * * m OUTPUT Voltage Output R L = kω ± ± * * V Over Specified Temperature ±. ±. * * V SM Grade ±. ±. V Short Circuit Current ± ± * * m Output Resistance, Open-Loop MHz * Ω Capacitive Load Stability G = + * pf TEMPERTURE RNGE Specification P, U, M, BM + * * C SM + C Operating P, U + C M, BM, SM + * * C Storage P, U + C M, BM, SM + * * C Thermal Resistance (θ J- ) P 9 C/W U C/W M, BM, SM * C/W * Specifications same as OPM. NOTE: () Specified with devices fully warmed up. OP
BSOLUTE MXIMUM RTINGS Supply Voltage... ±V Input Voltage Range... ±V S ±V Differential Input Voltage... Total V S ±V Operating Temperature M Package... C to + C P and U Packages... C to + C Storage Temperature M Package... C to + C P and U Packages... C to + C Output Short Circuit to Ground (T = + C)... Continuous Junction Temperature... + C Lead Temperature M and P Packages (soldering, s)... + C U Package, SOIC (s)... + C PCKGE INFORMTION PCKGE DRWING MODELS PCKGE NUMBER () OPP Plastic DIP OPM Metal TO-99 OPBM Metal TO-99 OPSM Metal TO-99 OPU SO- SOIC NOTE: () For detailed drawing and dimension table, please see end of data sheet, or ppendix D of Burr-Brown IC Data Book. ORDERING INFORMTION SPECIFICTION MODELS PCKGE TEMPERTURE RNGE OPP Plastic DIP to + C OPM Metal TO-99 to + C OPBM Metal TO-99 to + C OPSM Metal TO-99 to + C OPU SO- SOIC to + C US OEM PRICES - -99 + $. $. $.... 9..9.9..9 9.... PIN CONFIGURTIONS Top View M Package Top View P & U Packages +V S and Case Out Out B Out +VS In B In B In +In B Out B In B +In +In B V S +In B V S DICE INFORMTION PD FUNCTION Out In +In V S +In B In B Out B +V S Substrate Bias: V S MECHNICL INFORMTION OP DIE TOPOGRPHY MILS (.") MILLIMETERS Die Size 9 x ±. x.9 ±. Die Thickness ±. ±. Min. Pad Size x. x. Transistor Count Backing None OP
TYPICL PERFORMNCE CURVES T = + C, V S = ±V unless otherwise noted. k INPUT VOLTGE ND CURRENT NOISE SPECTRL DENSITY vs FREQUENCY k TOTL INPUT VOLTGE NOISE SPECTRL DENSITY at khz vs SOURCE RESISTNCE E O Voltage Noise (nv/ Hz) Voltage Noise Current Noise Current Noise Voltage Noise Current Noise (ƒ/ Hz) Voltage Noise, E (n/v/ Hz) O R S OP + Resistor Resistor Noise Only. k k k M k k k M M M Source Resistance ( Ω) n BIS ND OFFSET CURRENT vs TEMPERTURE n BIS ND OFFSET CURRENT vs INPUT COMMON-MODE VOLTGE n n Bias Current (p) Bias Current Offset Current (p) Bias Current (p). Offset Current. Offset Current (p) Offset Current. + + + mbient Temperature ( C). + +.. + + + Common-Mode Voltage (V) POWER SUPPLY ND COMMON-MODE REJECTION vs FREQUENCY +PSR COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTGE Power Supply Rejection (db) PSR CMR Common-Mode Rejection (db) Common-Mode Rejection (db) 9 k k k M M + + + Common-Mode Voltage (V) OP
TYPICL PERFORMNCE CURVES (CONT) T = + C, V S = ±V unless otherwise noted. OPEN-LOOP FREQUENCY RESPONSE MXIMUM OUTPUT VOLTGE SWING vs FREQUENCY Voltage Gain (db) R = KΩ L C = pf L OL φ 9 Phase Shift (Degrees) Output Voltage (Vp-p) R L = kω k k k M M k k M M GIN-BNDWIDTH ND SLEW RTE vs TEMPERTURE GIN-BNDWIDTH ND SLEW RTE vs SUPPLY VOLTGE Gain-Bandwidth (MHz) Gain-Bandwidth Slew Rate Slew Rate (V/µs) Gain-Bandwidth (MHz) V = + R L = kω Slew Rate Slew Rate (V/µs) + + + + + mbient Temperature ( C) Gain-Bandwidth Supply Voltage (±V S ) SETTLING TIME vs CLOSED-LOOP GIN SUPPLY CURRENT vs TEMPERTURE Settling Time (µs).%.% V O = V Step R L = kω C L = pf Supply Current (m) Total of Both Op mps Closed-Loop Gain (V/V) + + + + + mbient Temperature ( C) OP
TYPICL PERFORMNCE CURVES (CONT) T = + C, V S = ±V unless otherwise noted. CHNNEL SEPRTION vs FREQUENCY OPEN-LOOP GIN vs SUPPLY VOLTGE Channel Separation (db) R = L R L = k Ω Voltage Gain (db) 9 k k k Supply Voltage (±V S ) TOTL HRMONIC DISTORTION vs FREQUENCY THD + NOISE vs FREQUENCY ND OUTPUT VOLTGE THD + Noise (%rms).. R S = +V/V V = +V/V V.Vrms kω V = +V/V. k k k THD + Noise (%rms).. R S OP LRGE-SIGNL RESPONSE OP SMLL-SIGNL RESPONSE Output Voltage (V/div) Output Voltage (mv/div) kω Noise Limited Noise Limited = +V/V V Noise Limited Vp-p Vp-p Vp-p. k k k Time (µs/div) Time (ns/div) OP
PPLICTIONS INFORMTION ND CIRCUITS The OP is unity-gain stable and has excellent phase margin. This makes it easy to use in a wide variety of applications. Power supply connections should be bypassed with capacitors positioned close to the amplifier pins. In most cases,.µf ceramic capacitors are adequate. pplications with larger load currents and fast transient signals may need up to µf tantalum bypass capacitors. INPUT BIS CURRENT The OP s Difet input stages have very low input bias current an order of magnitude lower than BIFET op amps. Circuit board leakage paths can significantly degrade performance. This is especially evident with the SO- surfacemount package where pin-to-pin dimensions are particularly small. Residual soldering flux, dirt, and oils, which conduct leakage current, can be removed by proper cleaning. In most instances a two-step cleaning process is adequate using a clean organic solvent rinse followed by de-ionized water. Each rinse should be followed by a -minute bake at C. circuit board guard pattern effectively reduces errors due to circuit board leakage (Figure ). By encircling critical high impedance nodes with a low impedance connection at the same circuit potential, any leakage currents will flow harmlessly to the low impedance node. Guard traces should be placed on all levels of a multiple-layer circuit board. Inverting Buffer In +In R G / OP IN R F kω kω kω Ω R F kω kω kω B / OP Differential Voltage Gain = + R F /R G = I B = p Max Gain = CMRR ~ 9dB R IN = Ω FIGURE. FET Input Instrumentation mplifier. E In R G E +In / OP IN R F kω kω kω Ω R F kω kω kω B / OP Output E O Output In Non-Inverting Out In Out TO-99 Bottom View E O = [ ( + R F /R G ) (E E )] = (E E ) Using the IN for an output difference amplifier extends the input common-mode range of an instrumentation amplifier to ±V. conventional I with a unity-gain difference amplifier has an input common-mode range limited to ±V for an output swing of ±V. This is because a unitygain difference amp needs ±V at the input for V at the output, allowing only V additional for common-mode range. In Out FIGURE. Precision Instrumentation mplifier. Teflon E. I. Du Pont de Nemours & Co. FIGURE. Connection of Input Guard. BORD LYOUT FOR INPUT GURDING Guard top and bottom of board. lternate: use Teflon standoff for sensitive input pins. The information provided herein is believed to be reliable; however, BURR- BROWN assumes no responsibility for inaccuracies or omissions. BURR- BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR- BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. OP
PCKGE DRWINGS OP