Nano-crystalline Oxide Semiconductor Materials for Semiconductor and Display Technology Sanghun Jeon Ph.D. Associate Professor Department of Applied Physics Korea University
Personnel Profile (Affiliation and Employment) Affiliation Associate Professor in the Department of Applied Physics at Korea University Employment Education 03 Ph.D. Electronic Materials (Semiconductor Device, MOS dev. & Tr. Tech (w/ Best Paper Award & Young Researcher Award) Young Researcher Award at Int. Conf. on SSDM Nagoya Japan 2002) ~ 10 Yr experience at Samsung Adv. Inst. Tech., and Samsung Electronics in Semiconductor Area for Last a Decade with 6 research awards. 12~ Samsung Adv. Inst. Tech., SEC. Principal Research Staff Member Project leader of Haptic materials and devices (Tactile sensor) 09~11 Samsung Adv. Inst. Tech., SEC. Principal Research Staff Member Ox-based Device, Lead Device Physicist and Process Integrator Photo/Image Sensor, Interactive Display, Integrated Circuits, High Power Device Transparent device, 3D device, Electrical/Reliability/Modeling works. 05~09 Memory Business Division of SEC, Senior Research Staff Member Charge Trap Flash (8, 16, 32Gb). Process Integrator and Device Engineer. 03~05 Samsung Adv. Inst. Tech., [SAIT] Senior Research Staff Member Initiative Study on Charge Trap Flash Memory Device.
Technology Transfer @ Samsung Two-time tech. transfer from SAIT to business divisions of SEC, memory division (2005-2009) and display division (2011) 8Gb Flash Device 16Gb Flash Tech. Memory Division of SEC (2005-2009) 32Gb Flash Tech. 1T DRAM Display Division of SEC (2011) SAIT (2003-2005) Tech. Transfer SAIT (2009-2012) Basic Research on CTF Meeting Specification of NAND for 40nm gen. Understanding on science of oxide Demonstration Various of Ox. Sensor Sensors for Array E-Body
VOUT (V) VOUT (V) VIN (V) I DS [A] I DS @ V GS -V TH =-1V [A] Power, BV I on [W] Contents For nc-ox. device, I present various applications. Image Sensor Memory 10-11 Bilayer oxide transistor exhibits remarkable performance such as, high mobility (23~47cm 2 /Vs) and high breakdown voltage (BV) of 60~340V despite low process temperatures (<300 C), which can be integrated on metal pad. 10-3 HIZO(200Å )-IZO Bi-layer IZO: 100Å 10-5 IZO: 200Å IZO: 400Å 10-7 IZO: 600Å HIZO:400Å 10-9 Single Layer V DS :10V 10-13 -20-15 -10-5 0 5 10 15 20 V GS [V] Power IZO Thickness 50 10-7 Single 0.20 200Å 400Å HIZO:400Å 100Å 600Å 40 10-9 HIZO-IZO 0.15 30 Bi-layer 0.10 20 10-11 200Å -HIZO/IZO IZO: 100Å IZO: 200Å 0.05 10 IZO: 400Å 10-13 IZO: 600Å Single Bi-layer 0.00 0 0 100 200 300 400 500 HIZO HIZO-IZO Bi-Layer V DS [V] Sample sat [cm 2 /Vs] Display H H High Data Latch Output TFT Response Speed L H L 0.0 2.0m 4.0m 6.0m Time (sec) IN OUT L S nq Low Data Latch Output 0.000 0.001 0.002 0.003 0.004 Time (sec) Q R Monitoring signal 50nsec 40mv =>800uA Sample signal VLSI 2012
The Evolution of Devices CMOS Logic Device (Si III-V/ Graphene on Si) Si based Integration III-V Integration Graphene High-k metal gate Memory (Planar Vertical/Hybrid Integration) Planar Structure, IEDM 2006 VNAND, VLSI 2009 AOS TFT Key Trend: Alternative Materials and 3D Stack RRAM, Adv. Fuct. Mat. 2008 Transition Ox. Based RRAM
Benefit of nc-ingazno, nc-hfinzno, and nc-inzno Optical transparency due to large band-gap of ~3.4eV Stackable process nature due to low temp. process capability Nano-crystalline structure in amorphous matrix (negligible DV th ) but High (>10) The integration of nc-oxide semiconductor onto Si circuits is possible. CCD Spectrum profile CCD Spectrum profile HIZO Drift corrected spectrum profile Scanning SiO 2 GIZO IZO Spectrum profile Scanning GIZO Mo Mo IZO CCD Spectrum profile CCD Spectrum profile GIZO GIZO 1 CCD Spectrum profile SiO 2 HIZO IZO CCD Spectrum profile CCD Spectrum profile CCD Spectrum profile CCD Spectrum profile GIZO IZO IZO GIZO CCD Spectrum profile
CMOS Image Sensor Applications
Pixel Size Pixel (nm) Size (um) Resolution (Mega Pixel) Resolution (Mega Pixel) Current Status of CIS Devices Like others, CIS devices are facing physical limitation Shrinking the pixel size is a major driver for imaging business Pixel performance is inversely proportional to the size of CIS At a pace which counteract both, new technique is needed Conventional Architecture New architecture 100 6 Conventional Architecture New architecture 5 80 100 6 FSIS BSIS BSIS+ α 3D Stack 4 (3D Stack) 5 60 80 3 4 40 2 60 3 1 20 40 2 0 1 0 20 2000-2H 2004-2H 2007-2H 2010-2H 2012-2H 2015-2H Time FSIS: 0 Front side image sensor BSIS: Back side image sensor 2000-2H 2004-2H 2007-2H 2010-2H 2012-2H 2015-2H Time FSIS: Front side image sensor BSIS: Back side image sensor 0 Color filter Metal 2 Metal 1 Photo diode Front side image sensor Light source Light path Blocked/deflected light Color filter Photo diode Metal 1 Metal 2 Back side image sensor
Column Bus Pixel Circuit of CMOS Image Sensor A pixel consists of 1 Photodiode (PD) and 4 Transistors. Pixel Tr.s (Reset, SF, RS) are shared with neighboring pixels Interestingly, all pixel transistors are NMOSFET Pixel Tr.s (Reset, SF, RS) with less stringent requirement can be replaced with oxide TFT TX: Transfer Gate Transistor Reset: Reset Transistor SF: Source Follower Transistor RS: Row Select Transistor PD: Photodiode FD: Floating Diode Reset TX11 TX12 TX21 TX22 PD FD RS SF V DD
Our Approach The integration of electronically active oxide device onto silicon circuit. Here we propose a novel hybrid CIS architecture utilizing nanometer scale nano-crystalline oxide TFT with a photodiode. S. Jeon et al., ACS Applied Mat. Int. 2011 S. Jeon et al., IEEE IEDM 2010 Micro-lens Metal line Transparent conducting line nc-oxide TFT
Structural Comparison (1st layer) This demonstrates how Si PD in active can be enlarged. Novel Hybrid Transfer Gate Si Transistor Other Pixel Transistors Conventional Transfer Gate Transistor Si PD Si PD
Structural Comparison (2nd layer) The 2 nd layer of a novel hybrid four-pixel CIS structure consists of inter-connect metal lines and other pixel transistors. Some interconnect metal lines for delivering constant voltage, V DD, are replaced by a TCO Novel Hybrid Conventional Micro-lens Micro-lens Transparent Conducting Line Metal line TFT nc-igzo TFT
Simulation Results Electromagnetic power density contour plots were calculated by Sentaurus electromagnetic solver. The simulation results reveals a quantum efficiency increase of 143% 116%, and 120% at blue, green, and red wavelengths, respectively. Novel Hybrid Conventional Pixel Wavelength (nm) Quantum Efficiency (%) Ratio (%) Conventional Hybrid + TCO Interconnect Line Conventional Hybrid + TCO Interconnect Line Conventional Hybrid + TCO Interconnect Line 450 540 650 34.3-49.2 143 61.9-71.5 116 41.3-49.4 120
I DS (A) Structural Analysis & Electrical Analysis Self aligned top gate structure Dual gate stack (SiO 2 /Al 2 O 3 ) Trapezoidal active channel nc-oxide semiconductor b S. Jeon et al., Applied Physics Letters 2011 Z Y X X-X 180nm a-igzo 10-4 10-5 Mo Al 2 O 3 SiO 2 IGZO Mo IGZO 5 nm Y-Y 10-6 10-7 10-8 10-9 10-10 10-11 10-12 Vd=0.1V Vd=1.0V Vd=2.0V Vd=3.0V Vd=4.0V Vd=5.0V -4-2 0 2 4 V GS (V)
Memory Applications
Essential Device Architecture for V-NAND Even with revolutionary transition, the core stack remains the same. Vertical NAND for 1 terabit and beyond Planar NAND Revolutionary Transition Core CTF Stack for Vertical NAND S. Jeon et al., US 7,391,075 High F M metal High k SiN SiO 2 Si
Three dimensional approach to high density memory The schematics of 3D approach Depletion load inverter by hybrid channel Oxide TFT for 3D logic a b Vertical NAND Flash Stackable RRAM Memory Layer 3D Logic Bottom Logic Bottom Si Layer:CMOS Integrated circuits: Ring oscillator & NOR decoder Conventional Architecture 3D Logic Architecture Oxide-based integrated circuits can be applied to integrated sensors. IEDM 2009, IEEE TED 2011, ACS Appl. Mat. Int. 2011
Power Applications
Conventional Power and This System Different device specifications of PMIC & gate driver hinders on-chip integration even with the merits, such as low cost, reduced form factor, and low noise. S. Jeon et al., VLSI 2012 Conventional Power System Conventional Power system PMIC Currently Proposed System Power system with gate driver PMIC PMIC Oxide Gate DRV using ox. Tr. Gate DRV Gate DRV Power TR. Power TR. Power TR.
VOUT (V) VOUT (V) VIN (V) I DS [A] I DS @ V GS -V TH =-1V [A] Power, BV I on [W] 10-3 10-5 10-7 10-9 10-11 High Power Oxide Transistor Technology Bilayer oxide transistor exhibits remarkable performance such as, high mobility (23~47cm 2 /Vs) and high breakdown voltage (BV) of 60~340V despite low process temperatures (<300 C), which can be integrated on metal pad. HIZO(200Å )-IZO IZO: 100Å IZO: 200Å IZO: 400Å IZO: 600Å Bi-layer HIZO:400Å Single Layer V DS :10V 10-13 -20-15 -10-5 0 5 10 15 20 V GS [V] 10-7 10-9 10-11 10-13 Single HIZO:400Å HIZO-IZO Bi-layer 200Å -HIZO/IZO IZO: 100Å IZO: 200Å IZO: 400Å IZO: 600Å 0 100 200 300 400 500 V DS [V] 0.20 0.15 0.10 0.05 0.00 Single HIZO IZO Thickness 200Å 400Å 100Å 600Å Bi-layer HIZO-IZO Bi-Layer Sample 50 40 30 20 10 0 sat [cm 2 /Vs] H H High Data Latch Output TFT Response Speed L H IN OUT S nq Q R Monitoring signal 50nsec L 0.0 2.0m 4.0m 6.0m Time (sec) Low Data Latch Output L 0.000 0.001 0.002 Time (sec) 0.003 0.004 40mv =>800uA Sample signal VLSI 2012
Display Applications
In-cell touch technologies Displays with touch functionality are in great demand. In-cell touch display is an industrial goal (integration of sensor into LCD cell) Even with various approaches, there is no clear solution to realize large area interactive display. Previous photo-sensor technologies based on a-si are not applicable for large area touch screen due to low speed. Information Display 2010
Motivation of oxide photo-sensor Large Area Interactive Display Large size High resolution (FHD UD) Motion picture (>120Hz) Display size is limited by driving speed. 5 cm 2 /ev/s for UD-level High oxide TFT for display Process compatibility: oxide sensor Display Region R G B Sensor Region
I DS [A] Gated Three Terminal Sensor Architecture High photo-current for oxide sensor leads to simple pixel structure 2 TFT architecture: One sensor TFT & one switch TFT (Shield Metal) Transparent photo-sensor array due to simple structure a-si Photo TFT array Oxide Photo TFT array S. Jeon et al., Nature Materials 2012 S. Jeon et al., Adv. Mat. 2012 S. Jeon et al., IEEE IEDM 2010 S. Jeon et al., IEEE IEDM 2011 Sensor Switch Source/Drain Shield Metal 10-7 Ox. TFT 10-9 10-11 a-si TFT 10-13 10-1 10 1 10 3 10 5 10 7 10 9 Pulse Cycle [#] Light Dark Switch Sensor GIZO IZO GIZO Gate Ox. Gate Isolation Ox. Fully Transparent Ox. Sensor Array Passivation
Demonstration of photo-sensor array and Interactive Display Photo-sensor in 2010 Interactive Display in 2011 Array : 192 x 256 lines (49,152 pixels) S. Jeon, Nature Materials S. Jeon IEDM 2010, Adv. Mat. 2012, SID 2012
Summary NC-oxide semiconductor devices present various device applications. We proposes a novel hybrid CMOS image sensor utilizing oxide TFT and demonstrating excellent device performance of 180nm L g TFT for future high density CIS devices. We present the three-dimensionally alternating integration of stackable logic devices with memory cells We present high performance bilayer oxide semiconductor such as HfInZnO/InZnO transistor for high power application We have integrated photo-tfts in a transparent active-matrix photosensor array that can be operated at high frame rates and that has potential applications in contact-free interactive displays