19-3972; Rev ; 2/6 Triple Video Switch General Description The triple, high-frequency switch is intended for notebooks and monitors to permit RGB signals to be switched from one driver to one of two loads (1:2) or one of two sources to be connected to one load (2:1). The high-performance switch utilizes n-channel architecture with internal high-drive pullup from a lownoise charge pump, resulting in very low on-capacitance. The features 5Ω (typ) on-resistance switches with 1pF on-capacitances for routing RGB video signals. A logic input enables or disables the internal charge pump for optimal frequency performances when operating at lower input voltages resulting in standby supply current less than 3µA. All RGB inputs/outputs are ESD protected to ±8kV Human Body Model (HBM) and feature a global input (EN) that places all inputs and outputs in a high-impedance state. The is available in a small 3mm x 3mm, 16- pin TQFN package for ease of assembly and flowthrough layout, resulting in minimum space requirement and simplicity in board layout. The operates over the -4 C to +85 C temperature range. Notebook Computers Servers and Routers Docking Stations PC/HDTV Monitors +3.3V Applications +3V/+5V Single-Supply Operation Low R ON 5Ω ( = 5V) Low 1pF (typ) C ON Features Global ENABLE Input to Turn On/Off Switches Break-Before-Make Switching ±8kV HBM ESD Protection per IEC1-4-2 on I/Os Less than 1mA Supply Current (Charge Pump Enabled) Less than 3µA Standby Mode Charge-Pump Noise Lower than 163µV P-P Flowthrough Layout for Easy Board Layout Space-Saving Lead-Free (3mm x 3mm) 16-Pin TQFN Package PART ETE TEMP RANGE -4 C to +85 C Ordering Information PIN- PACKAGE 16 TQFN-EP* 3mm x 3mm TOP MARK PKG CODE AEF T1633-4 *EP = Exposed paddle. The is available only in a lead-free package. Specify lead-free by adding the + symbol at the end of the part number when ordering. Typical Operating Circuit +5V 75Ω 75Ω 75Ω V CC.1µF VGA D/A CONVERTER R G B R1 G1 B1 VGA CONNECTOR 1 FROM CONTROL SIGNALS EN QP GND R2 G2 B2 DOCKING STATION VGA CONNECTOR 2 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.)...-.3V to +6V R_, G_, B_,, QP, EN (Note 1)...-.3V to ( +.3V) Continuous Current through Any Switch...±12mA Peak Current through Any Switch (pulsed at 1ms, 1% duty cycle)...±24ma Continuous Power Dissipation (T A = +7 C) 16-Pin Thin QFN-EP (derate 15.6mW/ C above +7 C)...125mW Operating Temperature Range...-4 C to +85 C Storage Temperature Range...-65 C to +15 C Junction Temperature...+15 C Lead Temperature (soldering, 1s)...+3 C Note 1: Signals exceeding or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS 5V SUPPLY ( = 5V, QP = GND, T A = T MIN to T MAX. Typical values are at T A = +25 C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power-Supply Voltage Range 4.5 5.5 V Quiescent Supply Current I + = +5.5V RGB SWITCHES QP = GND.5 1 ma QP = 1 3 µa V QP = GND 5 6.5 On-Resistance R IN = +1.5V, ON I IN = -25mA QP = 6 7.5.3V < V QP = GND.5 1.3 On-Resistance Matching R IN < +2V, ON I IN = -25mA (Note 3) QP =.7 1.5 On-Resistance Flatness R FLAT(ON) < V IN < +1.5V, I IN = -25mA < V IN < +2V, QP = GND.5 1 I IN = -25mA QP =.7 1.8 QP =.7 1.55 On-Leakage Current I L(ON) R_, G_, B_ =.7V, 4.8V; EN = GND -1 +1 µa Off-Leakage Current I L(OFF) R_, G_, B_ =.7V, 4.8V; EN = GND 3 pa LOGIC INPUTS (, EN, QP) = 4.5V.8 Input Low Voltage V IL = 5.5V.8 Ω Ω Ω V = 4.5V 2. Input High Voltage V IH = 5.5V 2. V Input Leakage Current I LEAK -1 +1 µa ESD PROTECTION ESD Protection Human Body Model, R_, G_, B_ ±8 Human Body Model,, EN, QP ±2 kv 2
AC ELECTRICAL CHARACTERISTICS 5V SUPPLY ( = +5V, QP = GND, T A = T MIN to T MAX. Typical values are at T A = +25 C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Charge-Pump Noise V QP R S = R L = 5Ω 163 µv P-P Turn-On Time t ON V IN = +4.5V, R L = 1Ω, Figure 2 2 µs Charge Injection V GE N = V, R GE N = Ω, C L = 1.nF, Fi g ur e 3 28 pc Propagation Delay t PLH /t PHL C L = 1p F, R S = R L = 5Ω, Fi g ur e 4 (Note 3) 4 ps Output Skew Between Ports t SKEW Skew between any two ports: R, G, B; Figure 4 (Note 3) 35 ps 3dB Bandwidth f MAX R S = R L = 5Ω, Figure 6 5 MHz Off-Isolation R S = R L = 5Ω, V IN _ = 1V P-P, f = 5MHz, Figure 5 1MHz < f < 5MHz, QP = GND.5 Insertion Loss I LOS R S = R L = 5Ω QP =.5-58 db db Crosstalk V CT f < 5MHz, V IN = 1V P-P, R S = R L = 5Ω, Figure 5-4 db Off-Capacitance C OFF f = 1MHz, (R,G,B) to (R,G,B) 1,2 6 pf On-Capacitance C ON f = 1MHz 1 pf ELECTRICAL CHARACTERISTICS 3.3V SUPPLY ( = +3.3V, QP = GND, T A = T MIN to T MAX. Typical values are at T A = +25 C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power-Supply Voltage Range 3. 3.6 V Quiescent Supply Current I + = +3.6V.5 1 ma RGB SWITCHES On-Resistance R ON V = +3V, V IN = +1.5V, I IN = -25mA 6 7 Ω On-Resistance Matching R ON < V IN < +2V, I IN = -25mA (Note 3).8 1.2 Ω On-Resistance Flatness R FLAT(ON) < V IN < +2V, I IN = -25mA.9 1.4 Ω On-Leakage Current I L(ON) R_, G_, B_ = V or +3.6V, EN = GND -1 +1 µa Off-Leakage Current I L(OFF) R_, G_, B_ = V or +3.6V, EN = 2 pa LOGIC INPUTS (, EN, QP) = 3.V.8 Input Low Voltage V IL = 3.6V.8 V = 3.V 2. Input High Voltage V IH = 3.6V 2. V Input Leakage Current I LEAK -1 +1 µa ESD PROTECTION ESD Protection Human Body Model, R_, G_, B_ ±8 Human Body Model,, EN, QP ±2 kv 3
AC ELECTRICAL CHARACTERISTICS 3.3V SUPPLY ( = +3.3V, QP = GND, T A = T MIN to T MAX. Typical values are at T A = +25 C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Charge-Pump Noise V QP R S = R L = 5Ω 1 µv P-P Turn-On Time t ON V IN = +3V, R L = 1Ω, Figure 2 25 µs Charge Injection V GEN = V, R GEN = Ω, C L = 1.nF, Figure 3 21 pc Propagation Delay t PHL /t PLH C L = 1p F, R S = R L = 5Ω, Fi g ur e 4 ( N ote 3) 4 ps Output Skew Between Ports t SKEW Skew between any two ports: R, G, B, Figure 5 (Note 3) 35 ps 3dB Bandwidth f MAX R S = R L = 5Ω, Figure 5 5 MHz Insertion Loss I LOS 1MHz < f < 5MHz, R S = R L = 5Ω.6 db Crosstalk V CT f < 5MHz, R S = R L = 5Ω, Figure 5-4 db Off-Isolation R S = R L = 5Ω, V IN _ = 1V P-P, f = 5MHz, Figure 5-55 db Off-Capacitance C OFF f = 1MHz, (R,G,B) to (R,G,B) 1,2 6 pf On-Capacitance C ON f = 1MHz 1 pf Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Device is production tested at T A = +85 C. Note 3: Guaranteed by design. 4
(T A = +25 C, unless otherwise noted.) ON-RESISTANCE (Ω) 5. 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 QP = LOW ON-RESISTANCE vs. = 3.3V = 3V = 3.6V toc1 ON-RESISTANCE (Ω) 1 9 8 7 6 5 4 3 2 1 = 3.3V QP = LOW ON-RESISTANCE vs. V RGB T A = +85 C T A = +25 C T A = -4 C Typical Operating Characteristics toc2 ON-RESISTANCE (Ω) 5. 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 QP = LOW ON-RESISTANCE vs. = 4.5V = 5V = 5.5V toc3 4..6 1.2 1.8 2.4 3. 3.6 V RGB (V).3.6.9 1.2 1.5 1.8 2.1 2.4 2.7 3. 3.3 V RGB (V) 4..5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 V RGB (V) ON-RESISTANCE (Ω) 1 9 8 7 6 5 4 3 2 1 ON-RESISTANCE vs. V RGB T A = +85 C T A = +25 C T A = -4 C.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. V RGB (V) toc4 ON-RESISTANCE (Ω) 6 54 48 42 36 3 24 18 12 6 QP = HIGH ON-RESISTANCE vs. = 5.5V.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 V RGB (V) = 4.5V = 5V toc5 ON-RESISTANCE (Ω) 4 35 3 25 2 15 1 5 ON-RESISTANCE vs. V RGB T A = +85 C T A = +25 C.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. V RGB (V) T A = -4 C toc6 SUPPLY CURRENT (na) 7 65 6 55 5 45 4 35 3 25 2 QP = HIGH SUPPLY CURRENT vs. SUPPLY VOLTAGE 3. 3.5 4. 4.5 5. 5.5 (V) toc7 SUPPLY CURRENT (µa) 5 45 4 35 3 25 2 QP = LOW SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = +85 C T A = +25 C T A = -4 C 3. 3.5 4. 4.5 5. 5.5 (V) toc8 LEAKAGE CURRENT (na) 1 1 1 1.1.1.1 RGB ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE = 5V ON-LEAKAGE OFF-LEAKAGE -4-15 1 35 6 85 TEMPERATURE ( C) toc9 5
(T A = +25 C, unless otherwise noted.) LEAKAGE CURRENT (na) 1 1 1.1 RGB ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE = 3.3V ON-LEAKAGE toc1 TURN OFF TIMES (µs) Typical Operating Characteristics (continued) 6. 5.8 5.6 5.4 5.2 5. 4.8 4.6 TURN-ON TIMES vs. TEMPERATURE = 5V = 3.3V toc11 TURN-OFF TIMES (ns) 6 5 4 3 2 TURN-OFF TIMES vs. TEMPERATURE = 5V = 3.3V toc12.1 OFF-LEAKAGE 4.4 4.2 1.1-4 -15 1 35 6 85 TEMPERATURE ( C) 4. -4-15 1 35 6 85 TEMPERATURE ( C) -4-15 1 35 6 85 TEMPERATURE ( C) PROPAGATION DELAY (ps) 18 175 17 165 16 155 15 145 14 PROPAGATION DELAY vs. TEMPERATURE = 3.3V = 5V toc13 INSERTION LOSS (db) -1-2 -3-4 = 3.3V INSERTION LOSS vs. FREQUENCY toc14 INSERTION LOSS (db) -1-2 -3-4 = 5V INSERTION LOSS vs. FREQUENCY toc15 135 13-4 -15 1 35 6 85 TEMPERATURE ( C) -5.1 1 1 1 1 FREQUENCY (MHz) -5.1 1 1 1 1 FREQUENCY (MHz) -2 OFF-ISOLATION/CROSSTALK vs. FREQUENCY = +3.3V toc16-2 OFF-ISOLATION/CROSSTALK vs. FREQUENCY = +5V toc17 OFF-ISOLATION (db) -4-6 -8 CROSSTALK OFF-ISOLATION OFF-ISOLATION (db) -4-6 -8 CROSSTALK OFF-ISOLATION -1-1 -12.1 1 1 1 1 FREQUENCY (MHz) -12.1 1 1 1 1 FREQUENCY (MHz) 6
PIN NAME FUNCTION 1 Supply Voltage Input. Bypass to GND with a.1µf or larger ceramic capacitor. 2 R RGB Input/Output 3 G RGB Input/Output 4 B RGB Input/Output 5 GND Ground 6 EN Pin Description Active-Low Enable Input. Drive EN high to disable the. All I/Os are high impedance when the device is disabled. Drive EN low for normal operation. 7, 14 N.C. Not Internally Connected 8 R1 RGB Input/Output 9 G1 RGB Input/Output 1 B1 RGB Input/Output 11 B2 RGB Input/Output 12 G2 RGB Input/Output 13 R2 RGB Input/Output 15 Select Input. Logic input for switching RGB switches (see Table 1). 16 QP Active-Low Charge-Pump Enable. Drive QP high to disable the internal charge pump (for = 5V only). RGB switch operates with reduced performance when the charge pump is disabled. Drive QP low for normal operation. EP EP Exposed Pad. Connect exposed pad to ground plane. Detailed Description The triple, high-frequency switch is intended for notebooks and monitors permitting RGB (red, green, blue) signals to be switched from one driver to one of two loads (1:2) or one of two sources to be connected to one load (2:1). The provides three SPDT high-bandwidth switches to route standard VGA R, G, and B signals (see Table 1). A boosted gate-drive voltage is generated by an internal charge pump to enhance the performance of the RGB switches. The high-performance switch utilizes n-channel architecture with internal high-drive pullup from a low-noise charge pump resulting in very low on-capacitance. The RGB switches function with reduced performance when the charge pump is disabled ( > 5V). The s global input (EN) places all inputs/outputs in a high-impedance state, providing rejection of all signals. The R_, G_, and B_ analog switches are identical, and any of the three switches can be used to route red, green, or blue video signals. All RGB inputs/outputs are ESD protected to ±8kV Human Body Model (HBM). R G B EN SWITCH LOGIC CONTROL Figure 1. Functional Diagram CHARGE PUMP Analog Signal Levels Analog signal inputs over the full voltage range ( to ) are passed through the switch with minimal change in on-resistance (QP = low). When QP = high, the switches can operate within 1V of. The switches are bidirectional; therefore, R_, G_, and B_ can be either inputs or outputs. R1 R2 G1 G2 B1 B2 QP 7
SWITCH INPUT V IN RO, GO, BO R_, G_, B_ R L SWITCH OUTPUT V OUT C L Timing Diagrams/Test Circuits LOGIC INPUT V 5% t OFF tr < 5ns tf < 5ns LOGIC INPUT GND C L INCLUDES FIXTURE AND STRAY CAPACITANCE. RL V OUT = V IN ( R L + R ON ) V OUT SWITCH V OUTPUT t ON.9 x V UT.9 x V UT LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. Figure 2. Switching Time V OUT SWITCH INPUT V GEN R GEN RO, GO, BO R_, G_, B_ SWITCH OUTPUT C L V OUT V OUT GND LOGIC INPUT ( TO ) V OFF ON Q = ( V OUT )(C L ) OFF Figure 3. Charge Injection Charge Pump A low-noise charge pump with internal capacitors provides a doubled voltage for driving the RGB analog switches when operating the at low voltages ( < 5V). The charge pump adds less than 163µV P-P of noise to the switches. When operating with = 5V, the charge pump can be disabled to further reduce noise; however, the analog switch s performance is slightly degraded resulting in higher R ON and insertion loss. Drive QP high to disable the charge pump. Drive QP low for normal operation. When operating the at 3.3V, connect QP to GND. Logic Inputs (EN, ) The has two logic inputs that control the switch configuration and on/off function. Use to switch (RGB) to (RGB) 1 or (RGB) 2. Use EN to connect the switch inputs to the outputs. Drive EN low to enable the RGB switches inputs/outputs. Drive EN high to place all inputs/outputs in a high-impedance state. Table 1 illustrates the truth table. Table 1. Switch Truth Table EN FUNCTION (RGB) to (RGB) 1 1 (RGB) to (RGB) 2 1 X R_, B_, and G_ High Impedance 8
+5V.1µF R _,B_,G_ V OUT Timing Diagrams/Test Circuits (continued) R_.5 x V IN.5 x V IN V IN V IN 5Ω TRACE R_, G_,B_ GND QP EN 5Ω TRACE 1pF B_ R_ t PHL1.5 X V OUT t PLH1 V IN.5 x V IN.5 x V IN B_ t PLH2 t PHL2.5 X V OUT t SKEW = t PLH1 - t PLH2 OR t PHL1 = t PHL2 Figure 4. Propagation Delay and Skew Measurement Applications Information Power-Supply Bypassing and Sequencing Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the device. Always sequence on first, followed by R_, G_, or B_ and the logic inputs. Bypass to ground with a.1µf or larger ceramic capacitor as close to the device as possible. Layout High-speed switches such as the require proper PC board layout for optimum performance. Ensure that impedance-controlled PC board traces for high-speed signals are matched in length and as short as possible. Connect the exposed paddle to a solid ground plane. ESD Protection As with all Maxim devices, ESD-protection structures are incorporated to protect against electrostatic discharges encountered during handling and assembly on all pins. Additionally, the is protected to ±8kV Human Body Model (HBM) on all switches. Human Body Model Several ESD testing standards exist for measuring the robustness of ESD structures. The ESD protection of the is characterized with the Human Body Model. Figure 6 shows the model used to simulate an ESD event resulting from contact with the human body. The model consists of a 1pF storage capacitor that is charged to a high voltage, then discharged through a 1.5kΩ resistor. Figure 7 shows the current waveform when the storage capacitor is discharged into a low impedance. ESD Test Conditions ESD performance depends on a variety of conditions. Please contact Maxim for a reliability report documenting test setup, methodology, and results. Additional Applications Information Figure 8 illustrates the being used in a laptop in a 2:1 configuration (one of two sources connected to a load). The switch assumes the dedicated DVD player chip outputs R, G, B video, and the switches between normal VGA graphics and the dedicated DVD device. 9
BANDWIDTH NETWORK ANALYZER CROSSTALK NETWORK ANALYZER NETWORK ANALYZER OFF-ISOLATION NETWORK ANALYZER 5Ω TRACE (RGB) 5Ω TRACE 5Ω TRACE 5Ω TRACE R G (RGB) 1,2 R 1 G 1 (RGB) (RGB) 1,2 5Ω TRACE R13 49.9Ω R13 49.9Ω 5Ω TRACE NETWORK ANALYZER NETWORK ANALYZER AMPERES I P 1% 9% 36.8% 1% t RL Ir TIME t DL CURRENT WAVEFORM PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) R15 49.9Ω Figure 5. On-Loss, Off-Isolation, and Crosstalk Figure 7. HBM Discharge Current Waveform R C 1MΩ R D 15Ω +5V.1µF CHARGE-CURRENT- LIMIT RESISTOR DISCHARGE RESISTANCE HIGH- VOLTAGE DC SOURCE Cs 1pF STORAGE CAPACITOR DEVICE UNDER TEST VGA GRAPHIC GENERATOR R1 G1 B1 QP VGA Figure 6. Human Body ESD Test Model DEDICATED DVD PLAYER CHIP R2 G2 B2 EN GND FROM CONTROL LINE Figure 8. The Used in a 2:1 MUX Configuration 1
TOP VIEW R2 N.C. 13 14 15 Pin Configuration G2 B2 B1 G1 12 11 1 9 8 R1 7 N.C. 6 EN PROCESS: BiCMOS Chip Information QP 16 *EP 5 GND + 1 2 3 4 R G B (3mm x 3mm) Thin QFN *EXPOSED PADDLE. CONNECT TO GND. 11
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MARKING D D/2 E/2 E AAAA LC (ND - 1) X e e (NE - 1) X e D2/2 D2 12x16L QFN THIN.EPS LC k L E2/2 b.1 M C A B E2.1 C.8 C A A2 A1 L LC C L L e e PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x.8mm 1 21-136 G 2 PKG 8L 3x3 12L 3x3 16L 3x3 REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A.7.75.8.7.75.8.7.75.8 b.25.3.35.2.25.3.2.25.3 D 2.9 3. 3.1 2.9 3. 3.1 2.9 3. 3.1 E 2.9 3. 3.1 2.9 3. 3.1 2.9 3. 3.1 e.65 BSC..5 BSC..5 BSC. L.35.55.75.45.55.65.3.4.5 N 8 12 16 ND 2 3 4 NE 2 3 4 A1.2.5.2.5.2.5 A2.2 REF.2 REF.2 REF k.25 - -.25 - -.25 - - EXPOSED PAD VARIATIONS PKG. D2 E2 DOWN CODES PIN ID JEDEC BONDS MIN. NOM. MAX. MIN. NOM. MAX. ALLOWED TQ833-1.25.7 1.25.25.7 1.25.35 x 45 WEEC NO T1233-1.95 1.1 1.25.95 1.1 1.25.35 x 45 WEED-1 NO T1233-3.95 1.1 1.25.95 1.1 1.25.35 x 45 WEED-1 YES T1233-4.95 T1633-1.95 T1633F-3.65 T1633-4.95 1.1 1.1 1.25 1.25.95 1.1.8.95.65.8 1.1 1.25.95 1.1.95 1.1 1.25.35 x 45 1.25 WEED-1.35 x 45 WEED-2 T1633-2.95 1.1 1.25.95 1.1.35 x 45 1.25 WEED-2.95.225 x 45 WEED-2 T1633FH-3.65.8.95.225 x 45.65.8.95 WEED-2 N/A 1.25.35 x 45 WEED-2 YES NO YES N/A NO NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-12. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN.2 mm AND.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO22 REVISION C. 1. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x.8mm 2 21-136 G 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 26 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. Boblet