64K 8 ELECTRICLLY ERSBLE EPROM Table of Contents-. GENERL DESCRIPTION... 2 2. FETURES... 2 3. PIN CONFIGURTIONS... 3 4. BLOCK DIGRM... 4 5. PIN DESCRIPTION... 4 6. FUNCTIONL DESCRIPTION... 5 7. TBLE OF OPERTING MODES... 7 8. DC CHRCTERISTICS... 8 9. CPCITNCE... 9 0. C CHRCTERISTICS... 9. RED OPERTION DC CHRCTERISTICS... 0 2. RED OPERTION C CHRCTERISTICS... 0 3. DC PROGRMMING CHRCTERISTICS... 4. C PROGRMMING/ERSE CHRCTERISTICS... 2 5. TIMING WVEFORMS... 3 6. SMRT PROGRMMING LGORITHM... 5 7. SMRT PROGRMMING LGORITHM 2... 6 8. SMRT ERSE LGORITHM... 7 9. ORDERING INFORMTION... 8 20. PCKGE DIMENSIONS... 9 2. VERSION HISTORY... 20 Publication Release Date: January 9, 2006 - - Revision 6
. GENERL DESCRIPTION The W27C52 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65536 8 bits that operates on a single 5 volt power supply. The W27C52 provides an electrical chip erase function. 2. FETURES High speed access time: 45/70/90/20 ns (max.) Read operating current: 30 m (max.) Erase/Programming operating current: 30 m (max.) Standby current: m (max.) Single 5V power supply +4V erase/+2v programming voltage Fully static operation ll inputs and outputs directly TTL/CMOS compatible Three-state outputs vailable packages: 28-pin 600 mil DIP, 330 mil 32-pin PLCC - 2 -
3. PIN CONFIGURTIONS 5 2 7 6 5 4 3 2 0 Q0 Q Q2 GND 2 3 28 27 26 4 5 6 7 8 28-pin DIP 25 24 23 22 2 9 0 2 7 Q5 3 6 Q4 4 5 Q3 20 9 8 V CC 4 3 8 9 OE/Vpp 0 CE Q7 Q6 7 2 5 N C V C C 4 3 6 5 4 3 2 0 NC Q0 5 6 7 8 9 0 2 3 4 4 3 2 3 2 3 5 6 32-pin PLCC 7 8 9 3 0 29 28 27 26 25 24 23 2 0 22 2 8 9 NC OE/Vpp 0 CE Q7 Q6 Q Q G N Q Q Q 2 N C 3 4 5 D Publication Release Date: January 9, 2006-3 - Revision 6
4. BLOCK DIGRM OE/V CE PP CONTROL OUTPUT BUFFER Q0.. Q7 0.. DECODER CORE RRY 5 V CC GND 5. PIN DESCRIPTION SYMBOL 0 5 Q0 Q7 CE OE/VPP VCC GND NC DESCRIPTION ddress Inputs Data Inputs/Outputs Chip Enable Output Enable, Program/Erase Supply Voltage Power Supply Ground No Connection - 4 -
6. FUNCTIONL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C52 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE/VPP controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TCC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE/VPP, if TCC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C52 uses electrical erasure. Generally, the chip can be erased within 00 ms by using an EPROM writer with a special erase algorithm. Erase mode is entered when OE/VPP is raised to VPE (4V), VCC = VCE (5V), 9 = VPE (4V), 0 low, and all other address pins low and data input pins high. Pulsing CE low starts the erase operation. Erase Verify Mode fter an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "" or not. The erase verify mode ensures a substantial erase margin if VCC = VCE (3.75V), CE low, and OE/VPP low. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "" to "0." The program mode is entered when OE/VPP is raised to VPP (2V), VCC = VCP (5V), the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation. Program Verify Mode ll of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if OE/VPP low and CE low. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the CE and OE/VPP pins, the W27C52 may have common inputs. Publication Release Date: January 9, 2006-5 - Revision 6
Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE/VPP. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C52 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations n EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0. μ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. dditionally, for every eight devices, a 4.7 μf electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. - 6 -
7. TBLE OF OPERTING MODES (VPP = 2V, VPE = 4V, VHH = 2V, VCP = 5V, VCE = 5V, X = or VIL) MODE PINS CE OE/VPP 0 9 VCC OUTPUTS Read VIL VIL X X VCC DOUT Output Disable VIL X X VCC High Z Standby (TTL) X X X VCC High Z Standby (CMOS) VCC ±0.3V X X X VCC High Z Program VIL VPP X X VCP DIN Program Verify VIL VIL X X VCC DOUT Program Inhibit VPP X X VCP High Z Erase VIL VPE VIL VPE VCE DIH Erase Verify VIL VIL X X 3.75 DOUT Erase Inhibit VPE X X VCE High Z Product Identifier-manufacturer VIL VIL VIL VHH VCC D (Hex) Product Identifier-device VIL VIL VHH VCC 08 (Hex) Publication Release Date: January 9, 2006-7 - Revision 6
8. DC CHRCTERISTICS bsolute Maximum Ratings PRMETER RTING UNIT Operation Temperature 0 to +70 C Storage Temperature -65 to +25 C Voltage on all Pins with Respect to Ground Except OE/VPP, 9 and VCC Pins -0.5 to VCC +0.5 V Voltage on OE/VPP Pin with Respect to Ground -0.5 to +4.5 V Voltage on 9 Pin with Respect to Ground -0.5 to +4.5 V Voltage VCC Pin with Respect to Ground -0.5 to +7 V Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (T = 25 C ±5 C, VCC = 5.0V ±5%) PRMETER SYM. CONDITIONS LIMITS MIN. TYP. MX. Input Load Current ILI VIN = VIL or -0-0 μ VCC Erase Current ICP CE = VIL, OE/VPP = VPE VPP Erase Current IPP CE = VIL, OE/VPP = VPE UNIT - - 30 m - - 30 m Input Low Voltage VIL - -0.3-0.8 V Input High Voltage - 2.4-5.5 V Output Low Voltage (Verify) VOL IOL = 2. m - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 m 2.4 - - - 9 Erase Voltage VID - 3.75 4 4.25 V VPP Erase Voltage VPE - 3.75 4 4.25 V VCC Supply Voltage (Erase) VCE - 4.75 5.0 5.25 V VCC Supply Voltage (Erase Verify) VCE - 3.5 3.75 4.0 V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. - 8 -
9. CPCITNCE (VCC = 5V, T = 25 C, f = MHz) PRMETER SYMBOL CONDITIONS MX. UNIT Input Capacitance CIN VIN = 0V 6 pf Output Capacitance COUT VOUT = 0V 2 pf 0. C CHRCTERISTICS C Test Conditions PRMETER CONDITIONS 45/70 NS 90/20 NS Input Pulse Levels 0 to 3.0V 0.45V to 2.4V Input Rise and Fall Times 5 ns 0 ns Input and Output Timing Reference Level.5V/.5V 0.8V/2.0V Output Load C Test Load and Waveforms CL = 30 pf, IOH/IOL = -0.4 m/2. m CL = 00 pf, IOH/IOL = -0.4 m/2. m +.3V (IN94) 3.3K ohm D OUT 00 pf for 90/20 ns (Including Jig and Scope) 30 pf for 45/70 ns (Including Jig and Scope) Input Output For 90/20 ns 2.4V 0.45V Test Points 2.0V 0.8V 2.0V 0.8V Test Points Input Output For 45/70 ns 3.0V 0V Test Point.5V.5V Test Point Publication Release Date: January 9, 2006-9 - Revision 6
. RED OPERTION DC CHRCTERISTICS (VCC = 5.0V ±5%, T = 0 to 70 C) PRMETER SYM. CONDITIONS LIMITS MIN. TYP. MX. Input Load Current ILI VIN = 0V to VCC -5-5 μ Output Leakage Current ILO VOUT = 0V to VCC -0-0 μ Standby VCC Current ISB CE = - -.0 m (TTL input) Standby VCC Current ISB CE = VCC ±0.3V - 5 00 (CMOS input) μ VCC Operating Current ICC CE = VIL - - 30 m IOUT = 0 m, f = 5 MHz Input Low Voltage VIL - -0.3-0.8 V Input High Voltage - 2.2 - VCC +0.5 V Output Low Voltage VOL IOL = 2. m - - 0.45 V Output High Voltage VOH IOH = -0.4 m 2.4 - - V UNIT 2. RED OPERTION C CHRCTERISTICS (VCC = 5.0V ±5%, T = 0 to 70 C) PRMETER SYM. W27C52-45 W27C52-70 W27C52-90 W27C52-2 UNIT MIN. MX. MIN. MX. MIN. MX. MIN. MX. Read Cycle Time TRC 45-70 - 90-20 - ns Chip Enable ccess Time TCE - 45-70 - 90-20 ns ddress ccess Time TCC - 45-70 - 90-20 ns Output Enable ccess Time TOE - 20-30 - 40-55 ns OE /VPP High to High-Z Output TDF - 20-30 - 30-30 ns Output Hold from ddress Change TOH 0-0 - 0-0 - ns Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. - 0 -
3. DC PROGRMMING CHRCTERISTICS (VCC = 5.0V ±5%, T = 25 C ±5 C) PRMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MX. Input Load Current ILI VIN = VIL or -0-0 μ VCC Program Current VPP Program Current ICP IPP CE = VIL, OE / VPP = VPP - - 30 m CE = VIL, OE / VPP = VPP - - 30 m Input Low Voltage VIL - -0.3-0.8 V Input High Voltage - 2.4-5.5 V Output Low Voltage (Verify) VOL IOL = 2. m - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 m 2.4 - - V 9 Silicon I.D. Voltage VID -.5 2.0 2.5 V VPP Program Voltage VPP -.75 2.0 2.25 V VCC Supply Voltage (Program) VCP - 4.75 5.0 5.25 V Publication Release Date: January 9, 2006 - - Revision 6
4. C PROGRMMING/ERSE CHRCTERISTICS (VCC = 5.0V ±5%, T = 25 C ±5 C) PRMETER SYM. LIMITS MIN. TYP. MX. OE /VPP Pulse Rise Time TPRT 50 - - ns Data Setup Time TDS 2.0 - - μs CE Program Pulse Width TPWP 95 00 05 μs CE Erase Pulse Width TPWE 95 00 05 ms Data Hold Time TDH 2.0 - - μs OE /VPP Setup Time TOES 2.0 - - μs OE /VPP Hold Time TOEH 2.0 - - μs Data Valid from CE TDV 25 - μs Data Valid from ddress Change TDV2 25 - μs CE High to Output High Z TDFP 0-30 ns ddress Setup Time TS 2.0 - - μs ddress Hold Time TH 0 - - μs ddress Hold Time after CE High (Erase) THC 2.0 - - μs OE /VPP Valid after CE High TVS 2.0 - - μs OE /VPP Recovery Time TVR 2.0 - - μs ddress ccess Time During Erase Verify (VCC = 3.75V) TCV - - 250 ns Output Enable ccess Time during Erase Verify TOEV - - 50 ns (VCC = 3.75V) Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. UNIT - 2 -
5. TIMING WVEFORMS C Read Waveform ddress VIL ddress Valid CE OE/Vpp VIL TCE TDF Outputs VIL High Z TCC TOE Valid Output TOH High Z Erase Waveform Read Company SID 9 = 2.0V Read Device SID Chip Erase 9 = 4.0V Erase Verify Blank Check Read Verify ddress VIL Others = IL V 0 = VI 0 = L Others = IL V TCC TCC Others = VIL T S THC ddress Valid ddress Valid ddress Valid ddress Valid T CV =250 ns TCV =250 ns TCC Data D 08 Data ll One D OUT D OUT D OUT Vcc 5V T DS T DH T VCS 3.75V 4.0V T OES OE/Vpp VIL TOE TOE TOEH TOEV = 50 ns TOE CE V IL TCE TVS TPRT lways = IL V TPWE TVR Publication Release Date: January 9, 2006-3 - Revision 6
Timing Waveforms, continued Programming Waveform Program Program Verify Read Verify ddress ddress Stable ddress Stable ddress Stable ddress Valid ddress Valid V IL T S T H TS TH T OH T DFP Data V IL Data In Stable Data In Stable Data Out Data Out 2.0V T DS T DH TDS T DH TDV TDV2 TCC T OH OE/Vpp V IH TOES T OEH VIL VIL T PRT T PWP T VR TOE CE VIL TCE VIL CE should not be toggled during program verify period - 4 -
6. SMRT PROGRMMING LGORITHM Start ddress = First Location Vcc = 5.0V OE/Vpp = 2V Program One 00 μs Pulse Increment ddress No Last ddress? Yes ddress = First Location Increment ddress X = 0 No Last ddress? Pass Verify Byte Fail Increment X Yes Program One 00 μs Pulse No X = 25? Vcc = 5.0V OE/Vpp = VIL Yes Compare ll Bytes to Original Data Fail Device Failed Device Passed Pass Publication Release Date: January 9, 2006-5 - Revision 6
7. SMRT PROGRMMING LGORITHM 2 Start ddress = First Location Vcc = 5.0V X = 0 Program One 00 μs Pulse OE/V PP = 2V Increment X X = 25? Yes No Fail Verify One Byte OE/V = VIL PP Verify One Byte OE/V = VIL PP Fail Pass Pass Increment ddress No Last ddress? Yes Compare ll Bytes to Original Data Fail Pass Device Passed Device Failed - 6 -
8. SMRT ERSE LGORITHM Start X = 0 Vcc = 5V OE/Vpp = 4V 9 = 4V; 0 = VIL Chip Erase 00 ms Pulse ddress = First Location Increment X Vcc = 3.75V OE/Vpp = VIL Erase Verify Fail No X = 20? Increment ddress No Pass Last ddress? Yes Yes Vcc = 5V OE/Vpp = VIL Compare ll Bytes to FFs (HEX) Fail Pass Pass Device Fail Device Publication Release Date: January 9, 2006-7 - Revision 6
9. ORDERING INFORMTION PRT NO. CCESS TIME (ns) OPERTING CURRENT MX. (m) STNDBY CURRENT MX. (μ) PCKGE W27C52-45 45 30 00 600 mil DIP W27C52-70 70 30 00 600 mil DIP W27C52-90 90 30 00 600 mil DIP W27C52-2 20 30 00 600 mil DIP W27C52P-45 45 30 00 32-pin PLCC W27C52P-70 70 30 00 32-pin PLCC W27C52P-90 90 30 00 32-pin PLCC W27C52P-2 20 30 00 32-pin PLCC W27C52-45Z 45 30 00 600 mil DIP Lead Free W27C52P-45Z 45 30 00 32-pin PLCC Lead Free Notes:. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 8 -
20. PCKGE DIMENSIONS 28-pin P-DIP E 2 L 28 S B B D e 5 4 Base Plane Seating Plane a E e c Symbol B 2 B c D E E e L a e S Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.20 5.33 0.00 0.25 0.50 0.55 0.60 3.8 3.94 4.06 0.06 0.08 0.022 0.4 0.46 0.56 0.058 0.060 0.064.47.52.63 0.008 0.00 0.04 0.20 0.25 0.36.460.470 37.08 37.34 0.590 0.600 0.60 4.99 5.24 5.49 0.540 0.545 0.550 3.72 3.84 3.97 0.090 0.00 0.0 2.29 2.54 2.79 0.20 0.30 0.40 3.05 3.30 3.56 0 5 0 5 0.630 0.650 0.670 6.00 6.5 7.02 0.090 2.29 Notes:. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E does not include interlead flash. 3. Dimensions D & E include mold mismatch and are determined at the mold parting line. 4. Dimension B does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 32-pin PLCC H E E 5 4 32 30 29 D HD GD Symbol 2 b b c D E e Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.40 3.56 0.020 0.05 0.0 0.026 0.028 0.06 0.008 0.547 0.447 0.08 0.00 0.550 0.450 0.5 0.032 0.022 0.04 0.553 0.453 0.044 0.050 0.056 0.50 2.67 2.80 2.93 0.66 0.7 0.8 0.4 0.46 0.56 0.20 0.25 0.35 3.89 3.97 4.05.35.43.5.2.27.42 G D 0.490 0.50 0.530 2.45 2.95 3.46 3 2 G E H D 0.390 0.585 0.40 0.590 0.430 0.595 9.9 0.4 0.92 4.86 4.99 5. 4 20 c H E L y θ 0.485 0.075 0.490 0.090 0.495 0.095 0.004 2.32 2.45 2.57.9 2.29 2.4 0.0 0 0 0 0 L θ Seating Plane e G E b b 2 y Notes:. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection spec. Publication Release Date: January 9, 2006-9 - Revision 6
2. VERSION HISTORY VERSION DTE PGE DESCRIPTION Mar. 998 Initial Issued 2 Sep. 998 6 Correct Imput High Voltage () from 2.0 (min) to 2.2 (max) 4, 6 Correct VCC from 5.0 ±0% to 5.0 ±5% 3 ug. 999, 5, 6, 3 dd 45 ns bining 2, 3 Modify function description (VIL and ): VIL Low; High 4 Nov. 999 6 Typo correction 5 pril 4, 2005 5 dding important notice 6 Jan. 9, 2006 8 Ordering Information:dd W27C52-45Z and W27C52P-45Z Lead free part Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 20 -