UVEPROM SMJ27C K UVEPROM UV Erasable Programmable Read-Only Memory. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS
|
|
- Susan Walters
- 6 years ago
- Views:
Transcription
1 512K UVEPROM UV Erasable Programmable Read-Only Memory VILBLE S MILITRY SPECIFICTIONS SMD MIL-STD-883 FETURES Organized 65,536 x 8 High-reliability MIL-PRF processing Single +5V ±10% power supply Pin-compatible with existing 512K read-only memories (ROMs) and electrically programmable ROMs (EPROMs) ll inputs/outputs fully TTL compatible Power-saving CMOS technology Very high-speed SNP! Pulse Programming 3-state output buffers 400mV minimum DC noise immunity with standard TTL loads Latchup immunity of 250m on all input and output lines Low power dissipation (CMOS input levels) ctive - 193mW (MX) Standby - 1.7mW (MX) OPTIONS MRKING Timing 150ns access ns access ns access -25 Package(s) Ceramic DIP (600mils) J No. 110 Operating Temperature Ranges Military (-55 o C to +125 o C) For more products and information please visit our web site at M PIN SSIGNMENT (Top View) 28-Pin DIP (J) 600-Mils DQ0 DQ1 DQ2 GND GENERL DESCRIPTION The is a set of by 8-bit (524,288-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories. These devices are fabricated using powersaving CMOS technology for high speed and simple interface with MOS and bipolar circuits. ll inputs (including program data inputs can be driven by Series 54 TTL circuits without the use of external pullup resistors. Each output can drive one Series 54 TTL circuit without external resistors. The data outputs are 3-state for connecting multiple devices to a common bus. The is pin-compatible with existing 28-pin 512K ROMs and EPROMs. Because this EPROM operates from a single 5V supply (in the read mode), it is ideal for use in microprocessor-based systems. One other supply (13V) is needed for programming. ll programming signals are TTL level. This device is programmable by the SNP! Pulse programming algorithm. The SNP! Pulse programming algorithm uses a V PP of 13V and a V CC of 6.5V for a nominal programming time of seven seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random Vcc G\/V PP 10 E\ DQ7 DQ6 DQ5 DQ4 DQ3 Pin Name Function 0-15 ddress Inputs D0-DQ7 Inputs (programming)/outputs E\ Chip Enable/Power Down GND Ground G\ /V PP Output Enable/13V Programming V CC 5V Power Supply 1
2 FUNCTIONL BLOCK DIGRM* EPROM 65,536 x , E\ 20 [PWR DWN] 22 & G\ /V PP EN DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 * This symbol is in accordance with NSI/IEEE Std and IEC Publication OPERTION The seven modes of operation for the are listed in Table 1. The read mode requires a single 5V supply. ll inputs are TTL level except for V PP during programming (13V for SNP! Pulse), and 12V on 9 for signature mode. TBLE 1. OPERTION MODES FUNCTION (PINS) MODE* PROGRM STNDBY PROGRMMING VERIFY INHIBIT RED OUTPUT DISBLE E\ (20) V IL V IL V IH V IL V IL V IH G\ /V PP (22) V IL V IH X V PP V IL V PP V CC (28) V CC V CC V CC V CC V CC V CC SIGNTURE MODE V IL V IL V CC 9 (24) X X X X X X V ID V ID 0 (10) X X X X X X V IL V IH CODE DQ0-DQ7 Data Out High-Z High-Z Data In Data Out High-Z MFG DEVICE (11-13, 15-19) 97h 85h * X can be V IL or V IH 2
3 RED/OUTPUT DISBLE When the outputs of two or more are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from competing outputs of the other devices. To read the output of the selected, a low-level signal is applied to the E\ and G\ / V PP. ll other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7. LTCHUP IMMUNITY Latchup immunity on the is a minimum of 250m on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the printed circuit board level when the EPROM is interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup without compromising performance or packing density. POWER DOWN ctive I CC supply current can be reduced from 35m to 500μ(TTL-level inputs) or 300μ (CMOS-level inputs) by applying a high TTL/CMOS signal to the E\ pin. In this mode all outputs are in the high-impedance state. ERSURE Before programming, the is erased by exposing the chip through the transparent lid to a high-intensity ultraviolet (UV) light (wavelength 2537 Å). EPROM erasure before programming is necessary to assure that all bits are in the logic-high state. Logic lows are programmed into the desired locations. programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV intensity x exposure time) is 15 W. s/cm 2. typical 12mW/cm 2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5cm above the chip during erasure. fter erasure, all bits are in the high state. It should be noted that normal ambient light contains the correct wavelength for erasure; therefore, when using the, the window should be covered with an opaque label. SNP! PULSE PROGRMMING The is programmed using the SNP! Pulse programming algorithm as illustrated by the flowchart in Figure 1. This algorithm programs in a nominal time of seven seconds. ctual programming time varies as a function of the programmer used. Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E\ is pulsed. The SNP! Pulse programming algorithm uses an initial pulse of 100μs followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to ten 100μs pulses per byte are provided before a failure is recognized. The programming mode is achieved when G\ /V PP = 1 3 V, V CC = 6.5V, and E\ = V IL. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNP! Pulse programming routine is complete, all bits are verified with V CC = 5V, G\ /V PP = V IL, and E\ = V IL. PROGRM INHIBIT Programming can be inhibited by maintaining high level input on E\. PROGRM VERIFY Programmed bits can be verified with G\ /V PP and E\ = V IL. SIGNTURE MODE The signature mode provides access to a binary code identifying the manufacturer and device type. This mode is activated when 9 (terminal 24) is forced to 12V ±0.5V. Two identifier bytes are accessed by 0 (terminal 10); i.e., 0 = V IL accesses the manufacturer code, which is output on DQ0- DQ7; 0 = V IH accesses the device code, which is also output on DQ0-DQ7. ll other addresses must be held at V IL. Each byte possesses odd parity on bit DQ7. The manufacturer code for these devices is 97h and the device code is 85h. 3
4 FIGURE 1. SNP! PULSE PROGRMMING FLOW CHRT STRT ddress = First Location V CC = 6.5V ± 0.25V, G\ /V PP = 13V ± 0.25V Program One Pulse = t W = 100μs Increment ddress Program Mode Last ddress? No Yes ddress = First Location X = 0 Program One Pulse = t W = 100μs No Increment ddress Verify Word Fail X = X+1 X = 10? Pass Interactive Mode No Last ddress? Yes V CC = 5V ± 0.5V, G\ /V PP = V IL Yes Device Failed Compare ll Bytes to Original Data Fail Final Verification Pass Device Passed 4
5 BSOLUTE MXIMUM RTINGS* Supply Voltage Range, V CC ** V to +7.0V Supply Voltage Range, V pp ** V to +14.0V Input Voltage Range, ll inputs except 9** V to 6.5V V to +13.5V Output Voltage Range** V to V CC +1V Operating Cage Temperature Range, T C C to 125 C Storage Temperature Range, T stg C to 150 C *Stresses greater than those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** ll voltage values are with respect to GND. RECOMMENDED OPERTING CONDITIONS MIN NOM MX UNIT V CC Supply Voltage 1 Read Mode V SNP! Pulse programming algorithm V G\ /V PP 2 Supply Voltage SNP! Pulse programming algorithm V V ID Voltage level on 9 for signature mode V V IH High-level DC input voltage TTL 2 V CC +1 V CMOS V CC -0.2 V CC +1 V V IL Low-level DC input voltage TTL V CMOS V T C Operating case temperature C NOTES: 1. V CC must be applied before or at the same time as G\ /V PP and removed after or at the same time as G\ /V PP. The deivce must not be inserted into or removed from the board when G\ /V PP or V CC is applied. 2. G\ /V PP can be connected to V CC directly (except in the program mode). V CC supply current in this case is I CC + I PP. ELECTRICL CHRCTERISTICS OVER RECOMMENDED RNGES OF OPERTING CONDITIONS PRMETER TEST CONDITIONS MIN TYP 1 MX V OH High-level output voltage I OH = -400μ 2.4 V OL Low-level output voltage I OL = 2.1m 0.4 I I Input current (leakage) V I = 0V to 5.5V 10 I O Output current (leakage) V O = 0V to V CC 10 I PP G\ /V PP supply current (during program pulse) 2 G\ /V PP = 13V I CC1 V CC supply current (standby) TTL-Input Level V CC = 5.5V, E\=V IH 500 CMOS-Input Level V CC = 5.5V, E\=V CC 325 E\=V IL, V CC =5.5V I CC2 V CC supply current (active) t cycle = minimum cycle time, outputs open NOTES: 1. Typical values are at T C =25 C and nominal voltages. 2. This parameter has been characterized at 25 C and is not production tested
6 CPCITNCE OVER RECOMMENDED RNGES OF SUPPLY VOLTGE ND OPERTING CSE TEMPERTURE, f = 1MHz* PRMETER TEST CONDITIONS TYP** UNIT C I Input capacitance V I = 0V 6 pf C O Output capacitance V O = 0V 10 pf C G /V PP G\ /V PP input capacitance G\ /V PP = 0V 20 pf * Capacitance measurements are made on sample basis only. ** ll typical values are at T C = 25 C and nominal voltages. UVEPROM SWITCHING CHRCTERISTICS OVER RECOMMENDED RNGES OF SUPPLY VOLT- GE ND OPERTING CSE TEMPERTURE PRMETER TEST CONDITIONS 1, MIN MX MIN MX MIN MX t a() ccess time from address ns t a(e) ccess time from E\ ns t en(g) Output enable time from G\ /V PP ns t dis See Figure 2 Output disable time from G\ /V PP or E\, whichever occurs first ns t v() Output data valid time after change of address, E\, or G\, whichever occurs first ns NOTES: 1. Timing measurements are made at 2V for logic high and 0.8V for logic low. (see Figure 2) 2. Common test conditions apply for t dis except during programming. 3. Value calculated from 0.5V delta to measured output level. This parameter is only sampled and not 100% tested. UNIT RECOMMENDED TIMING REQUIREMENTS FOR PROGRMMING: V CC = 6.5V and G\ /V PP = 13V (SNP! Pulse), T C = 25 C (see Figure 2) MIN NOM MX UNIT t dis(e) Output Disable Time from E\ ns t h() Hold Time, address 0 μs t h(d) Hold Time, Data t h(vpp) Hold Time, G\ /V PP t w(ipgm) Pulse Duration, Initial Program μs t rec(pg) Recovery Time, G\ /V PP t su() Setup Time, ddress t su(d) Setup Time, Data t su(vpp) Setup Time, G\ /V PP t su(vcc) Setup Time, V CC t v(eld) Data Valid from E\ Low 1 μs t r(pg) G\ /V PP Rise Time 50 ns 6
7 PRMETER MESUREMENT INFORMTION 2.08V Output Under Test CL = 100 pf 1 R L = 800Ω NOTES: 1. C L includes probe and fixture capacitance. FIGURE 2. LOD CIRCUIT ND VOLTGE WVEFORM C testing inputs are driven at 2.4V for logic high and 0.4V for logic low. Timing measurements are made at 2V for logic high and 0.8V for logic low for both inputs and outputs. FIGURE 3. RED-CYCLE TIMING 7
8 FIGURE 4. PROGRM-CYCLE TIMING (SNP! PULSE PROGRMMING) NOTES: 1. G\ /V PP = 13V and V CC = 6.5V for SNP! Pulse programming. 8
9 MECHNICL DEFINITION* Micross Case #110 (Package Designator J) SMD , Case Outline X D S2 Q E L Pin 1 S1 b2 e b e c NOTE: These dimensions are per the SMD. Micross package dimensional limits may differ, but they will be within the SMD limits. *ll measurements are in inches. 9
10 ORDERING INFORMTION EXMPLE: -25JM Device Number Speed ns Package Type Operating Temp. -15 J * -20 J * -25 J * *VILBLE PROCESSES M = Extended Temperature Range -55 o C to +125 o C 10
11 MICROSS TO DSCC PRT NUMBER CROSS REFERENCE* Micross Package Designator J TI Part #** SMD Part # -15JM X -20JM X -25JM X * Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. ** Parts are listed on SMD under the old Texas Instruments part number. Micross purchased this product line in November of
TMS27C BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC BIT PROGRAMMABLE READ-ONLY MEMORY
This Data Sheet is Applicable to All TMS27C128s and TMS27PC128s Symbolized with Code B as Described on Page 12. Organization...16K 8 Single 5-V Power Supply Pin Compatible With Existing 128K MOS ROMs,
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Organization...131072 by 8 Bits Single 5-V Power Supply Operationally Compatible
More informationTMS27C BY 16-BIT UV ERASABLE TMS27PC BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES
Organization... 262144 by 16 Bits Single 5-V Power Supply All Inputs/ Outputs Fully TTL Compatible Static Operations (No Clocks, No Refresh) Max Access/Min Cycle Time V CC ± 10% 27C/ PC240-10 100 ns 27C/
More informationTMS27C BIT UV ERSABLE PROGRAMMABLE TMS27PC BIT PROGRAMMABLE READ-ONLY MEMORY
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY This Data Sheet is pplicable to ll TMS2C12s and TMS2PC12s Symbolized with Code B as Described on Page 182. Organization...64K
More informationTMS27C BIT UV ERASABLE PROGRAMMABLE TMS27PC BIT PROGRAMMABLE READ-ONLY MEMORY
Organization... 256K 8 Single 5-V Power Supply Operationally Compatible With xisting Megabit PROMs Industry Standard 32-Pin Dual-In-line Package and 32-Lead Plastic Leaded Chip Carrier All Inputs/ Outputs
More informationSOIC (SOP) NC A8 A9 A10 A11 A12 A13 A14 A15 A16 NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 BYTE/VPP GND O15/A-1 GND O7 O14 O6 O13 O5 O12 O4 VCC
Features Read Access Time - 100 ns Word-wide or Byte-wide Configurable 8-Megabit Flash and Mask ROM Compatable Low Power CMOS Operation -100 µa Maximum Standby - 50 ma Maximum Active at 5 MHz Wide Selection
More informationTMS27C BY 8-BIT UV ERASABLE TMS27PC BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
TMS27C512 65536 BY 8-BIT UV RSBL PROGRMMBL RD-ONLY MMORIS Organization...65536 by 8 Bits Single 5-V Power Supply Pin Compatible With xisting 512K MOS ROMs, PROMs, and PROMs ll Inputs/Outputs Fully TTL
More informationAm27C Megabit (524,288 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM
FINAL Am27C040 4 Megabit (524,288 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS Fast access time 90 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved pinout Plug in upgrade
More informationTMS27C BY 8-BIT UV ERASABLE TMS27PC BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
Organization...32768 by 8 Bits Single 5- Power Supply Pin Compatible With xisting 256K MOS ROMs, PROMs, and PROMs ll Inputs / Outputs Fully TTL Compatible Max ccess/min Cycle Time CC ± 10% 27C/ PC256-10
More informationPY263/PY264. 8K x 8 REPROGRAMMABLE PROM FEATURES DESCRIPTION. EPROM Technology for reprogramming. Windowed devices for reprogramming.
FEATURES EPROM Technology for reprogramming High Speed 25/35/45/55 ns (Commercial) 25/35/45/55 ns (Military) Low Power Operation: 660 mw Commercial 770 mw Military PY263/PY264 8K x 8 REPROGRAMMABLE PROM
More informationNTE27C256 12D, NTE27C256 15D, NTE27C256 70D Integrated Circuit 256 Kbit (32Kb x 8) UV EPROM 28 Lead DIP Type Package
NTE27C256 12D, NTE27C256 15D, NTE27C256 70D Integrated Circuit 256 Kbit (32Kb x 8) UV EPROM 28 Lead DIP Type Package NTE27C256 15P Integrated Circuit 256 Kbit (32Kb x 8) OTP EPROM 28 Lead DIP Type Packag
More informationNTE27C D Integrated Circuit 2 Mbit (256Kb x 8) UV EPROM
NTE27C2001 12D Integrated Circuit 2 Mbit (256Kb x 8) UV EPROM Description: The NTE27C2001 12D is an 2 Mbit UV EPROM in a 32 Lead DIP type package ideally suited for applications where fast turn around
More informationW27C512 64K 8 ELECTRICALLY ERASABLE EPROM. Table of Contents-
64K 8 ELECTRICLLY ERSBLE EPROM Table of Contents-. GENERL DESCRIPTION... 2 2. FETURES... 2 3. PIN CONFIGURTIONS... 3 4. BLOCK DIGRM... 4 5. PIN DESCRIPTION... 4 6. FUNCTIONL DESCRIPTION... 5 7. TBLE OF
More informationFM27C ,144-Bit (32K x 8) High Performance CMOS EPROM
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM General Description The FM27C256 is a 256K Electrically Programmable Read Only Memory. It is manufactured in Fairchild s latest CMOS split gate
More informationNMC27C32B Bit (4096 x 8) CMOS EPROM
NMC27C32B 32 768-Bit (4096 x 8) CMOS EPROM General Description The NMC27C32B is a 32k UV erasable and electrically reprogrammable CMOS EPROM ideally suited for applications where fast turnaround pattern
More informationNMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM General Description The NMC27C64 is a 64K UV erasable, electrically reprogrammable and one-time programmable (OTP) CMOS EPROM ideally suited for applications where
More information1-Megabit (128K x 8) Unregulated Battery-Voltage OTP EPROM AT27BV010
Features Fast Read Access Time 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power
More informationSGM7SZ04 Small Logic Inverter
Preliminary Datasheet SGM7SZ04 GENERL DESCRIPTION The SGM7SZ04 is a single inverter from SGMICRO s Small Logic series. The device is fabricated with advanced CMOS technology to achieve ultra-high speed
More informationNM27C ,288-Bit (64K x 8) High Performance CMOS EPROM
NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM General Description The NM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM). It is manufactured
More informationdescription TMS27PC240 FN PACKAGE ( TOP VIEW ) A17 A13 A12 A11 A10 A9 GND DQ2 DQ1 DQ0 DQ9 DQ8 GND NC DQ7 DQ6 A8 A7 A6 A5 DQ15 DQ14
Organization... 262144 by 16 Bits Single 5-V Power Supply All Inputs/Outputs Fully TTL Compatible Static Operations (No Clocks, No Refresh) Max Access/Min Cycle Time V CC ± 10% 27C/ PC240-10 100 ns 27C/
More informationNM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM General Description The NM27C010 is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory. It is organized
More information27C Bit ( x 8) UV Erasable CMOS PROM Military Qualified
27C256 262 144-Bit (32 768 x 8) UV Erasable CMOS PROM Military Qualified General Description The 27C256 is a high-speed 256K UV erasable and electrically reprogrammable CMOS EPROM ideally suited for applications
More information4-Megabit (512K x 8) OTP EPROM AT27C040
Features Fast Read Access Time 70 ns Low Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 32-lead PDIP 32-lead PLCC 32-lead TSOP 5V ± 10% Supply High Reliability
More informationNM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM General Description The NM27C040 is a high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory. It is organized
More informationKEY FEATURES. Immune to Latch-UP Fast Programming. ESD Protection Exceeds 2000 V Asynchronous Output Enable GENERAL DESCRIPTION TOP VIEW A 10
HIGH-SPEED 2K x 8 REGISTERED CMOS PROM/RPROM KEY FEATURES Ultra-Fast Access Time DESC SMD Nos. 5962-88735/5962-87529 25 ns Setup Pin Compatible with AM27S45 and 12 ns Clock to Output CY7C245 Low Power
More information256K (32K x 8) OTP EPROM AT27C256R
Features Fast Read Access Time 45 ns Low-Power CMOS Operation 100 µa Max Standby 20 ma Max Active at 5 MHz JEDEC Standard Packages 28-lead PDIP 32-lead PLCC 28-lead TSOP and SOIC 5V ± 10% Supply High Reliability
More informationNOTE: This product has been replaced with UT28F256QLE or SMD device types 09 and 10.
NOTE: This product has been replaced with UT28F256QLE or SMD 5962-96891 device types 09 and 10. 1 Standard Products UT28F256 Radiation-Hardened 32K x 8 PROM Data Sheet December 2002 FEATURES Programmable,
More information8Mb (1M x 8) One-time Programmable, Read-only Memory
Features Fast read access time 90ns Low-power CMOS operation 100µA max standby 40mA max active at 5MHz JEDEC standard packages 32-lead PLCC 32-lead PDIP 5V 10% supply High-reliability CMOS technology 2,000V
More informationHT27C020 OTP CMOS 256K 8-Bit EPROM
OTP CMOS 256K 8-Bit EPROM Features Operating voltage: +5.0V Programming voltage V PP=12.5V±0.2V V CC=6.0V±0.2V High-reliability CMOS technology Latch-up immunity to 100mA from -1.0V to V CC+1.0V CMOS and
More informationUNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD EIGHT HIGH OLTGE, HIGH CURRENT DRLINGTON RRYS DESCRIPTION The is a high voltage, high current Darlington array comprised of eight NPN Darlington pairs. The device features
More informationNM27P Bit (256k x 8) POP Processor Oriented CMOS EPROM
NM27P020 2 097 152-Bit (256k x 8) POPTM Processor Oriented CMOS EPROM General Description The NM27P020 is a 2 Mbit POP EPROM configured as 256k x 8 It s designed to simplify microprocessor interfacing
More information2K x 8 Reprogrammable PROM
2K x 8 Reprogrammable PROM Features Windowed for reprogrammability CMOS for optimum speed/power High speed 20 ns (Commercial) 35 ns (Military) Low power 660 mw (Commercial and Military) Low standby power
More information256K (32K x 8) CMOS EPROM TSOP A11 A3 14 V PP A12 A7 A6 A5 A4 A3 PLCC VSOP A13 A14 A Microchip Technology Inc.
This document was created with FrameMaker 44 256K (2K x 8) CMS EPRM 27C256 FEATURES High speed performance - 9 ns access time available CMS Technology for low power consumption - 2 ma Active current -
More informationEEPROM AS8ER128K32 FUNCTIONAL BLOCK DIAGRAM. 128K x 32 Radiation Tolerant EEPROM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS
128K x 32 Radiation Tolerant EEPROM AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38534 FEATURES Access time of 150ns, 200ns, 250ns Operation with single 5V + 10% supply Power Dissipation: Active: 1.43
More information8K x 8 EPROM CY27C64. Features. Functional Description. fax id: 3006
1CY 27C6 4 fax id: 3006 CY27C64 Features CMOS for optimum speed/power Windowed for reprogrammability High speed 0 ns (commercial) Low power 40 mw (commercial) 30 mw (military) Super low standby power Less
More information32K x 8 Power Switched and Reprogrammable PROM
1CY7C271A CY7C271A Features CMOS for optimum speed/power Windowed for reprogrammability High speed 25 ns (Commercial) Low power 275 mw (Commercial) Super low standby power Less than 85 mw when deselected
More informationFAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVER
IDT74FCT2245T/CT FST CMOS OCTL BIDIRECTIONL TRNSCEIVER FST CMOS OCTL BIDIRECTIONL TRNSCEIVER INDUSTRIL TEMPERTURE RNGE IDT74FCT2245T/CT FETURES: and C grades Low input and output leakage 1μ (max.) CMOS
More informationAddressable relay driver
ESCRIPTION The addressable relay driver is a high-current latched driver, similar in function to the 9934 address decoder. The device has 8 open-collector arlington power outputs, each capable of 150m
More informationM27128A. NMOS 128 Kbit (16Kb x 8) UV EPROM
NMOS 128 Kbit (16Kb x 8) UV EPROM NOT FOR NEW DESIGN FAST ACCESS TIME: 200ns EXTENDED TEMPERATURE RANGE SINGLE 5 V SUPPLY VOLTAGE LOW STANDBY CURRENT: 40mA max TTL COMPATIBLE DURING READ and PROGRAM FAST
More information4-Megabit (512K x 8) OTP EPROM AT27C040. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns Low Power CMOS Operation 100 µa max. Standby 30 ma max. Active at 5 MHz JEDEC Standard Packages 32-Lead 600-mil PDIP 32-Lead 450-mil SOIC (SOP) 32-Lead PLCC 32-Lead
More informationINTEGRATED CIRCUITS. 74LVC V Parallel printer interface transceiver/buffer. Product specification 1995 Nov 10 IC24 Low Voltage Handbook
INTEGRTED CIRCUITS 3.3V Parallel printer interface traceiver/buffer 1995 Nov 10 IC4 Low Voltage Handbook FETURES synchronous operation 4-Bit traceivers 3 additional buffer/driver lines TTL compatible inputs
More informationNTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package
NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package Description: The NTE74S188 Schottky PROM memory is organized in the popular 32 words by 8 bits configuration. A memory
More informationEEPROM AS58LC K x 8 EEPROM Radiation Tolerant. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535
128K x 8 EEPROM Radiation Tolerant AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535 FEATURES High speed: 250ns and 300ns Data Retention: 10 Years Low power dissipation, active current (20mW/MHz (TYP)),
More information2K x 8 Reprogrammable PROM
1CY 7C29 2A CY7C291A Features Windowed for reprogrammability CMOS for optimum speed/power High speed 20 ns (commercial) 25 ns (military) Low power 660 mw (commercial and military) Low standby power 220
More information32K x 8 Power Switched and Reprogrammable PROM
1 CY7C271 32K x Power Switched and Reprogrammable PROM Features CMOS for optimum speed/power Windowed for reprogrammability High speed 30 ns (Commercial) 3 ns (Military) Low power 660 mw (commercial) 71
More information4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT29BV040A
Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Software Protected Programming Fast Read Access Time 200 ns Low Power Dissipation 15 ma Active Current 50 µa CMOS Standby
More informationUT28F64 Radiation-Hardened 8K x 8 PROM Data Sheet
Standard Products UT28F64 Radiation-Hardened 8K x 8 PROM Data Sheet August 2001 FEATURES Programmable, read-only, asynchronous, radiationhardened, 8K x 8 memory - Supported by industry standard programmer
More information3V 10-Tap Silicon Delay Line DS1110L
XX-XXXX; Rev 1; 11/3 3V 1-Tap Silicon Delay Line General Description The 1-tap delay line is a 3V version of the DS111. It has 1 equally spaced taps providing delays from 1ns to ns. The series delay lines
More information2K x 8 Reprogrammable Registered PROM
1CY 7C24 5A CY7C245A 2K x 8 Reprogrammable Registered PROM Features Windowed for reprogrammability CMOS for optimum speed/power High speed 15-ns address set-up 10-ns clock to output Low power 330 mw (commercial)
More informationDS Tap High Speed Silicon Delay Line
www.dalsemi.com FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances
More informationBattery-Voltage. 1-Megabit (64K x 16) Unregulated. High-Speed OTP EPROM AT27BV1024. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Pin Compatible with JEDEC Standard AT27C1024 Low
More informationUT54LVDS032 Quad Receiver Advanced Data Sheet
Standard Products UT54LVDS032 Quad Receiver Advanced Data Sheet December 22,1999 FEATURES >155.5 Mbps (77.7 MHz) switching rates +340mV differential signaling 5 V power supply Ultra low power CMOS technology
More informationDS in-1 Silicon Delay Line
www.dalsemi.com FEATURES All-silicon time delay 3 independent buffered delays Delay tolerance ±2ns for -10 through 60 Stable and precise over temperature and voltage range Leading and trailing edge accuracy
More information128K (16K x 8-Bit) CMOS EPROM
1CY 27C1 28 fax id: 3011 CY27C128 128K (16K x 8-Bit) CMOS EPROM Features Wide speed range 45 ns to 200 ns (commercial and military) Low power 248 mw (commercial) 303 mw (military) Low standby power Less
More informationM74HCT04. Hex inverter. Features. Description
Hex inverter Features High speed: t PD = 11 ns (typ.) at =4.5V Low power dissipation: I CC = 1 μa (max.) at T A =25 C Compatible with TTL outputs: V IH = 2 V (min.) V IL = 0.8 V (max) Balanced propagation
More information256K (32K x 8) Paged Parallel EEPROM AT28C256
Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
More informationPIN ASSIGNMENT TAP 2 TAP 4 GND DS PIN DIP (300 MIL) See Mech. Drawings Section IN TAP 2 TAP 4 GND
DS1000 5-Tap Silicon Delay Line FEATURES All-silicon time delay 5 taps equally spaced Delays are stable and precise Both leading and trailing edge accuracy Delay tolerance +5% or +2 ns, whichever is greater
More information8K x 8 Power-Switched and Reprogrammable PROM
8K x 8 Power-Switched and Reprogrammable PROM Features CMOS for optimum speed/power Windowed for reprogrammability High speed 20 ns (commercial) 25 ns (military) Low power 660 mw (commercial) 770 mw (military)
More informationP4C164LL. VERY LOW POWER 8Kx8 STATIC CMOS RAM FEATURES DESCRIPTION V CC. Current (Commercial/Industrial) Operating: 55 ma CMOS Standby: 3 µa
P4C164LL VERY LOW POWER 8Kx8 STATIC CMOS RAM FEATURES Current (Commercial/Industrial) Operating: 55 ma CMOS Standby: 3 µa Access Times 80/100 (Commercial or Industrial) 90/120 (Military) Single 5 Volts
More informationDS in 1 High Speed Silicon Delay Line FEATURES PIN ASSIGNMENT
DS1044 4 in 1 High Speed Silicon Delay Line FEATURES All silicon timing circuit Four independent buffered delays Initial delay tolerance ±1.5 ns Stable and precise over temperature and voltage Leading
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Features Fast Read Access Time - 45 ns Low-Power CMOS Operation 100 µa max.
More informationFEATURES APPLICATIONS. SiP32467, SiP32468 C OUT EN EN GND. Fig. 1 - Typical Application Circuit
50 mω, Slew Rate Controlled Load Switch in WCSP DESCRIPTION The and are slew rate controlled integrated high side load switches that operate in the input voltage range from 1.2 V to 5.5 V. This series
More informationBattery-Voltage. 1-Megabit (128K x 8) Unregulated OTP EPROM AT27BV010. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. NMOS 64 Kbit (8Kb x 8) UV EPROM NOT FOR NEW DESIGN FAST ACCESS TIME: 180ns
More informationFEATURES APPLICATIONS. SiP32460, SiP32461, SiP32462 C OUT EN EN GND. Fig. 1 - Typical Application Circuit
50 mω, Slew Rate Controlled Load Switch in WCSP DESCRIPTION The SiP32460,, and SiP32462 are slew rate controlled integrated high side load switches that operate over the input voltage range from 1.2 V
More informationDS Tap Silicon Delay Line
www.dalsemi.com FEATURES All-silicon time delay 5 taps equally spaced Delay tolerance ±2 ns or ±3%, whichever is greater Stable and precise over temperature and voltage range Leading and trailing edge
More informationDS Tap Silicon Delay Line
www.dalsemi.com FEATURES All-silicon time delay 10 taps equally spaced Delays are stable and precise Leading and trailing edge accuracy Delay tolerance ±5% or ±2 ns, whichever is greater Economical Auto-insertable,
More informationQS54/74FCT373T, 2373T. High-Speed CMOS Bus Interface 8-Bit Latches MDSL QUALITY SEMICONDUCTOR, INC. 1 DECEMBER 28, 1998
Q QUALITY SEMICONDUCTOR, INC. QS54/74FCT373T, 2373T High-Speed CMOS Bus Interface 8-Bit Latches QS54/74FCT373T QS54/74FCT2373T FEATURES/BENEFITS Pin and function compatible to the 74F373 74FCT373 and 74ABT373
More informationDual Voltage Comparator
AVAILABLE AS MILITARY SPECIFICATIONS M38510/10305B MIL-STD-883, 1.2.1 FEATURES Wide operating supply range: ±15V to a single +5V Low input current: 6 na High sensitivity: 10μV Wide differential input range:
More informationP4C1257/P4C1257L. ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES DESCRIPTION. Full CMOS. Separate Data I/O
P4C1257/P4C1257L ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES Full CMOS High Speed (Equal Access and Cycle s) 12/15/20/25 ns (Commercial) 12/15/20/25 ns (Industrial) 25/35/45/55/70 ns (Military)
More informationBIDIRECTIONAL TRANSCEIVER
IDT/FCTT/T/CT FST CMOS OCTL BIDIRECTIONL TRNSCEIVER FST CMOS OCTL BIDIRECTIONL TRNSCEIVER MILITRY ND INDUSTRIL TEMPERTURE RNGES IDT/FCTT/T/CT FETURES: Std.,, and C grades Low input and output leakage µ
More information16M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr. 15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 16,789,216-bit high-speed Static Random Access Memory organized as 1M(2M) words
More informationSN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
More informationSRAM AS5C K x 8 SRAM Ultra Low Power SRAM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATION FEATURES GENERAL DESCRIPTION
512K x 8 Ultra Low Power AVAILABLE AS MILITARY SPECIFICATION SMD 5962-95613 1,2 MIL STD-883 1 FEATURES Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby) Fully Static, No
More informationDS in-1 Low Voltage Silicon Delay Line
3-in-1 Low Voltage Silicon Delay Line www.dalsemi.com FEATURES All-silicon timing circuit Three independent buffered delays Initial delay tolerance ±1.5 ns Stable and precise over temperature and voltage
More informationTITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 16- BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS, TTL COMPATIBLE, MONOLITHIC SILICON REVISIONS
REVISIONS LTR DESCRIPTION DTE PPROVED B Update boilerplate paragraphs to current requirements. - PHN Update boilerplate to current MIL-PRF-38535 requirements. - PHN 09-02-17 Charles F. Saffle 15-07-28
More informationUT54LVDM031LV Low Voltage Bus-LVDS Quad Driver Data Sheet September, 2015
Standard Products UT54LVDM031LV Low Voltage Bus-LVDS Quad Driver Data Sheet September, 2015 The most important thing we build is trust FEATURES >400.0 Mbps (200 MHz) switching rates +340mV nominal differential
More informationStandard Products UT54ACTS220 Clock and Wait-State Generation Circuit. Datasheet November 2010
Standard Products UT54ACTS220 Clock and Wait-State Generation Circuit Datasheet November 2010 www.aeroflex.com/logic FEATURES 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply
More informationP4C1299/P4C1299L. ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM FEATURES DESCRIPTION. Full CMOS, 6T Cell. Data Retention with 2.0V Supply (P4C1299L)
FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 15/20/25/35 ns (Commercial/Industrial) 15/20/25/35/45 ns (Military) Low Power Operation Single 5V±10% Power Supply Output Enable (OE)
More informationCDC LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442B FEBRUARY 1994 REVISED NOVEMBER 1995
Low Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation pplications Operates at 3.3-V LVTTL-Compatible Inputs and s Supports Mixed-Mode Signal Operation (-V Input and Voltages With 3.3-V )
More informationDS1040 Programmable One-Shot Pulse Generator
www.dalsemi.com FEATURES All-silicon pulse width generator Five programmable widths Equal and unequal increments available Pulse widths from 5 ns to 500 ns Widths are stable and precise Rising edge-triggered
More informationNM27C Bit (64K x 8) High Performance CMOS EPROM
February 1994 NM27C512 524 288-Bit (64K x 8) High Performance CMOS EPROM General Description The NM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM) It is
More informationSGM4582 High Voltage, CMOS Analog Multiplexer
High Voltage, CMOS nalog Multiplexer GENERL DESCRIPTION The is a high voltage, CMOS analog IC configured as two 4-channel multiplexers. This CMOS device can operate from ±1.8V to ±5.5V dual power supplies
More information54LVTH244A. 3.3V ABT 8-Bit Octal Buffers/Drivers FEATURES: DESCRIPTION: Logic Diagram
54LVTH244A 3.3V ABT 8-Bit Octal Buffers/Drivers FEATURES: Logic Diagram DESCRIPTION: 3.3V ABT octal buffers/drivers with 3-state outputs RAD-PAK radiation-hardened against natural space radiation Package:
More informationSN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
More informationP4C1041 HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM
HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) 10/12/15/20 ns (Commercial) 12/15/20 ns (Industrial/Military) Low Power Single 5.0V ± 10% Power Supply 2.0V
More information74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and
More information1Mb (128K x 8) Low Voltage, One-time Programmable, Read-only Memory
Features Fast read access time 70ns Dual voltage range operation Low voltage power supply range, 3.0V to 3.6V, or Standard power supply range, 5V 10% Compatible with JEDEC standard Atmel AT27C010 Low-power
More information54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
More informationCDC391 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 Low Skew for Clock-Distribution and Clock-Generation pplicatio TTL-Compatible Inputs and s Distributes One Clock Input to Six
More information2M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 2,097,152-bit high-speed Static Random Access Memory organized as 128K(256) words
More information4M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 4,194,304-bit high-speed Static Random Access Memory organized as 256K(512) words
More information1M Async Fast SRAM. Revision History CS16FS1024(3/5/W) Rev. No. History Issue Date
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014 2.0 Add 32TSOPII-400mil pin configuration and outline May 26, 2014 3.0 Delete 128kx8 products May 22, 2015 4.0 Add part no. CS16FS10245GC(I)-12
More informationDS1202, DS1202S. Serial Timekeeping Chip FEATURES PIN ASSIGNMENT. ORDERING INFORMATION DS pin DIP DS1202S 16 pin SOIC DS1202S8 8 pin SOIC
DS22, DS22S Serial Timekeeping Chip FEATURES Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation 2 x 8 RAM for scratchpad data
More informationua9637ac DUAL DIFFERENTIAL LINE RECEIVER
ua967ac Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and EIA/TIA--B and ITU Recommendations V. and V. Operates From Single -V Power Supply Wide Common-Mode Voltage Range High Input Impedance
More information8Mb (1M x 8) One-time Programmable, Read-only Memory
Features Fast read access time 90ns Low-power CMOS operation 100µA max standby 40mA max active at 5MHz JEDEC standard packages 32-lead PLCC 32-lead PDIP 5V 10% supply High-reliability CMOS technology 2,000V
More informationELECTROSÓN M27C Mbit (128Kb x8) UV EPROM and OTP EPROM
1 Mbit (128Kb x8) UV PROM and OTP PROM 5V ± 10% SUPPLY VOLTAG in RAD OPRATION ACCSS TIM: 35ns LOW POWR CONSUMPTION: Active Current 30mA at 5Mhz Standby Current 100µA PROGRAMMING VOLTAG: 12.75V ± 0.25V
More informationPRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink
More informationSN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and
More informationSingle-Ended 16-Channel/Differential 8-Channel CMOS ANALOG MULTIPLEXERS
MPC507 MPC50 MPC50 MPC507 Single-ded -Channel/Differential 8-Channel CMOS NLOG MULTIPLEXERS FETURES NLOG OVERVOLTGE PROTECTION: 70Vp-p NO CHNNEL INTERCTION DURING OVERVOLTGE BREK-BEFORE-MKE SWITCHING NLOG
More information