High-Performance Si Nanowire FET with a Semi Gate-Around Structure Suitable for Integration Soshi Sato 1, Hideyuki Kamimura 1, Hideaki Arai 1, Kuniyuki Kakushima 2, Parhat Ahmet 1, Kenji Ohmori 3, Keisaku Yamada 3 and Hiroshi Iwai 1 1 FRC, 2 IGSSE, Tokyo Institute of Technology 3 NRL, Waseda University 1
Outline Introduction of SiNW FET Purpose of this Study Device Fabrication Process Electrical Characterization I d V g I d V d Curves Carrier Mobility Performance Assessment of Si NW FET Conclusion 2
Introduction of Si Nanowire FET Gate Gate Drain Gate Source Drain Planar FET Source Source Source Gate Drain Multi Gate FET Nanowire BOX UTB SOI FET Effective electrostatic control of 1-D channel due to the gate all-around structure. Low I off can be achieved. Nanowire FET 3
Gate all-around SiNW FETs Ultra narrow NW FET N. Singh, IEDM 2006 SS~60mV/dec, I on /I off >10 6 Oxidation in 875 o C for 4 hours 3-Dimensionally Stacked NW multiple channels Excellent On-current 6.5mA/μm NMOS 3.3mA/μm PMOS SS: 68/65 mv/dec C. Dupre, IEDM 2008 Repetitive deposition of Si / SiGe Promising performance for future MOS device Dedicated process for SiNW FET is necessary 4
SiNW FET fabrication using conventional CMOS process Semi Gate-Around Structure Si NW channel connected with substrate (BOX Layer) so as not to be released. Suitable for application to industrial manufacturing 5
Purpose of This Work Fabrication of a semi-gate around SiNW FET using conventional CMOS processing Demonstration and analysis of FET performance Outlook of semi-gate around SiNW FET for future CMOS devices 6
Si NW FET Fabrication SEM XTEM Starting wafer: 300mm SOI (61 / 145 nm) S/D & Fin Patterning Sacrificial Oxidation & Oxide Removal DryOx 1000 o C for 1 hour (not completely released from BOX layer) 1μm 30nm Nanowire Sidewall Formation (Oxide Support Protector) Gate Oxidation & Poly-Si Deposition Ion Implantation (As) into gate Poly-Si Gate Lithography & RIE Etching Gate Sidewall Formation & S/D Implantation Ni SALISIDE Process (Ni 9nm / TiN 10nm) Standard Recipes for CMOS Processes 30nm 30nm 7
Images of Fabricated SiNW FET Semi Gate-Around ~300 o A Gate Drain SiN BOX SiN 30nm Source Gate A Fabricated Samples (a) (b) (c) D H 35nm 35nm 35nm D W 25nm 35nm 45nm 8
I d V g and I d V d Characteristics Drain Current (μa) 10 2 10 0 10-2 10-4 10-6 25nm V D =1.0V 35nm -1 c 0 V D =0.05V S.S.= 71mV/dec V th =-0.36V L g =200nm 1.0-0.5 0.0 0.5 1.0 Gate Voltage (V) Drain Current (μa) 50 40 30 20 10 0 On Current V g -V th =1.0V V g -V th =0.8V V g -V th =0.6V V g -V th =0.4V 0.0 0.2 0.4 0.6 0.8 1.0 Drain Voltage (V) Fairly nice FET operation with I on /I off ~10 7 Large I on of 49μA per wire was achieved 9
On Current (μa) On Current of Si NW FET 60 50 40 30 20 10 0 per wire Dw 45nm Dw 35nm Dw 25nm wider SiNW 0 100 200 300 400 500 600 Normalized by the peripheral Current Density (A/nm) 6x10 6.E-07-7 5x10 5.E-07-7 4x10 4.E-07-7 3x10 3.E-07-7 2x10 2.E-07-7 1x10 1.E-07-7 0.E+00 0 little difference Dw=25nm 45nm Dw=35nm Dw=45nm Dw 25nm 0 100 200 300 400 500 600 Lg(nm) Lg(nm) Carriers are formed on the surface of Si Nanowire 10
Effective electron mobility of SiNW FET μ eff (cm 2 /Vs) 800 600 400 200 L g =500nm 64 wires in parallel (a) Planar SiO 2 (100) 35nm Source Drain 5μm 0 25nm measured in room temperature 0.E+00 0 5x10 5.E+12 1x10 1.E+13 13 1.5x10 2.E+13 13 Inversion Carrier Density (cm -2 ) High effective mobility can be achieved with semi-gate around SiNW FET 11
Design of Channel Shape for High On-Current (a) (b) (c) 35nm 35nm 35nm 25nm 35nm 45nm The Si NW FET in this work is the surface channel device. Larger I on with longer peripheral length. Higher aspect ratio has advantage for large I ON The narrowest Si NW FET is the most efficient considering printed area 12
Benchmark of our SiNW FET High I on were obtained with semi-gate around Si NW FET Moreover, further performance can be expected with L g scaling 13
Expected On-current Evaluation with SiNW FET I on should be compared based on unit width. Unit Width [1μm] Unit Width [1μm] The number of NWs = 1000/ (S+W) Separation: S [nm] S S S W W W Diameter: W [nm] W Pitch: S+W [nm] 14
Estimation of the Number of Si NWs in the Unit Width 2010 2014 2016 MPU/ASIC M1 H.P. [nm] 45 28 22 The number of NWs 11 17 21 S S S W W W W Nanowire Pitch 2018 18 23 The number of NWs is calculated using H.P. of MPU/ASIC M1 pattern MPU/ASIC M1 Pitch = Half Pitch x 2 15
On-current assessment of SiNW FET in roadmap I on (μa/μm) 4000 3000 2000 1000 0 x1.5 L g =100nm x2 T ox =2.5nm T ox =5nm L g =200nm D w =25nm 2005 2010 2015 2020 2025 Year Requirement for Double Gate in ITRS 2007 With device scaling SiNW FET has a potential for future FET structure with high I ON 16
Conclusion Semi gate-around SiNW FET with conventional CMOS process has been successfully fabricated and performed I on /I off ~10 7 and I ON of 49.6μA. From peripheral normalization, surface channel are formed with high mobility. On-current evaluation reveals high potential of SiNW FET to be one of the candidates for future CMOS structure. 17
Acknowledgement This work is supported by METI, Japan The authors thank Front End Process Program and Aska II with Selete for device fabrication 18